JPH05264590A - Warp correction mechanism for probe card - Google Patents
Warp correction mechanism for probe cardInfo
- Publication number
- JPH05264590A JPH05264590A JP4090255A JP9025592A JPH05264590A JP H05264590 A JPH05264590 A JP H05264590A JP 4090255 A JP4090255 A JP 4090255A JP 9025592 A JP9025592 A JP 9025592A JP H05264590 A JPH05264590 A JP H05264590A
- Authority
- JP
- Japan
- Prior art keywords
- warp
- probe card
- correction
- voltage
- probe
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Testing Of Individual Semiconductor Devices (AREA)
- Measuring Leads Or Probes (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Measurement Of Length, Angles, Or The Like Using Electric Or Magnetic Means (AREA)
Abstract
Description
【0001】[0001]
【産業上の利用分野】この発明は、ウエハに形成された
LSIに対する検査用のプローブカードに生ずる反りを
補正する機構に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a mechanism for correcting a warp generated in a probe card for inspecting an LSI formed on a wafer.
【0002】[0002]
【従来の技術】図3(a) において、ウエハ1の表面には
多数のLSIチップ2が形成され、各LSIチップ2の
電子回路パターン2b は外部配線用のパッド端子2a に
接続されている。各LSIチップは1個づつ分割され、
パッド端子2a をリードフレームに接続してLSIデバ
イスが製作される。LSIチップ2は分割される前に、
ウエハに形成された段階でプローブカードにより特性が
検査される。図3(b) は検査に使用されるプローブカー
ドの一例を示し、プローブカード3は円形の基板3の中
心部に開口部3a を設け、その周辺に、パッド端子2a
に対応したプローブピン3b を配列して構成される。各
プローブピン3b は弾性を有し、その先端に探針3c が
植設されている。図3(c) はLSIチップ2の検査方法
を示す。ウエハ1は検査ステージ4に載置され、またプ
ローブカード3は外周がテストヘッド5の下面に固定さ
れる。まずウエハ1を高温(例えば+60°C)に加熱
し、または低温(例えば−50°C)に冷却する。つい
で、図示しないXYZ移動機構により、検査ステージ4
をXまたはY方向に移動して所定のLSIチップ2を開
口部3a の位置に停止し、さらにZ上昇して各パッド端
子2a を対応した探針3c に接触させて検査が行われ
る。2. Description of the Related Art In FIG. 3A, a large number of LSI chips 2 are formed on the surface of a wafer 1, and an electronic circuit pattern 2b of each LSI chip 2 is connected to a pad terminal 2a for external wiring. Each LSI chip is divided one by one,
An LSI device is manufactured by connecting the pad terminal 2a to the lead frame. Before the LSI chip 2 is divided,
The characteristics are inspected by the probe card when it is formed on the wafer. FIG. 3 (b) shows an example of a probe card used for inspection. The probe card 3 has an opening 3a at the center of a circular substrate 3 and a pad terminal 2a around the opening 3a.
Is formed by arranging probe pins 3b corresponding to. Each probe pin 3b has elasticity, and a probe 3c is implanted at its tip. FIG. 3C shows an inspection method of the LSI chip 2. The wafer 1 is placed on the inspection stage 4, and the outer periphery of the probe card 3 is fixed to the lower surface of the test head 5. First, the wafer 1 is heated to a high temperature (for example + 60 ° C.) or cooled to a low temperature (for example −50 ° C.). Then, the inspection stage 4 is moved by an XYZ moving mechanism (not shown).
Is moved in the X or Y direction to stop the predetermined LSI chip 2 at the position of the opening 3a, and further raised Z to bring each pad terminal 2a into contact with the corresponding probe 3c for inspection.
【0003】[0003]
【発明が解決しようとする課題】上記の検査において、
ウエハ1が高温または低温に維持されると、その温度に
影響されてプローブカード3も高温、または低温となっ
てストレスが生ずる。しかし、プローブカード3は外周
がテストヘッド5に固定されているため、低温ではスト
レスは内在するのみであるが、高温の場合はプローブカ
ード自体が伸長して開口部3a の周辺に反りが発生し、
パッド端子2a と探針3c の接触不良の原因となる。図
4はプローブカード3に反りが発生した状態を示し、実
線はプローブカード3が下方に反った場合で、中心部の
探針(イ) はパッド端子2a に接触しているが、中心部よ
り外側の探針(ロ),(ハ) は反り分だけ上昇するとともに外
側に傾斜し、対応するパッド端子2a に接触しない。一
方、点線で示すように、プローブカード3が上方に反っ
た場合は、探針(ロ),(ハ) は内側に傾斜して隣接のパッド
端子2a に接触する恐れがあり、また探針(イ) は上昇す
るために接触しない。上記の反りにより生ずる接触不良
は、プローブピン3b の弾性によりある程度吸収されて
いる。しかし、最近においては集積度がさらに向上した
超LSIにおいては、パッド端子2a の個数が増加した
ため、プローブカードは従来に比較してより大きい直
径、例えば200〜250mmのものが使用されてい
る。このような直径では、発生する反りは数10μmm
に達する。これに対して反りの許容限界は10μmm以
下とされており、プローブピンの弾性によりこの反りは
吸収できない。この発明は以上に鑑みてなされたもの
で、検査温度の上昇によりプローブカード3に生じた反
りを補正する機構を提供することを目的とする。In the above inspection,
When the wafer 1 is maintained at a high temperature or a low temperature, the temperature of the wafer 1 influences the probe card 3 to a high temperature or a low temperature, causing stress. However, since the outer periphery of the probe card 3 is fixed to the test head 5, stress is only inherent at low temperatures, but at high temperatures, the probe card itself expands and warps occur around the openings 3a. ,
This may cause poor contact between the pad terminal 2a and the probe 3c. FIG. 4 shows a state in which the probe card 3 is warped. The solid line shows the case where the probe card 3 is warped downward, and the probe (a) at the center is in contact with the pad terminal 2a. The outer probes (b) and (c) ascend by the amount of warp and incline outward and do not contact the corresponding pad terminals 2a. On the other hand, as indicated by the dotted line, when the probe card 3 is warped upward, the probes (b) and (c) may incline inward and come into contact with the adjacent pad terminals 2a. B) does not touch because it rises. The poor contact caused by the warp is absorbed to some extent by the elasticity of the probe pin 3b. However, recently, in a VLSI having a higher degree of integration, since the number of pad terminals 2a has increased, a probe card having a diameter larger than that of the conventional one, for example, 200 to 250 mm is used. With such a diameter, the generated warp is several tens of μmm.
Reach On the other hand, the allowable limit of the warp is set to 10 μmm or less, and the warp cannot be absorbed due to the elasticity of the probe pin. The present invention has been made in view of the above, and it is an object of the present invention to provide a mechanism for correcting a warp generated in the probe card 3 due to an increase in inspection temperature.
【0004】[0004]
【課題を解決するための手段】この発明はプローブカー
ドの反り補正機構であって、前記のプローブカードの表
面に対して、検査温度の上昇によりプローブカードに生
ずる反りを検出する反り検出圧電素子と、この反りに対
して逆方向の力を与えて補正する反り補正圧電素子とを
並列に接着する。さらに、反り検出圧電素子が検出した
検出電圧を入力し、この検出電圧と逆位相の補正電圧を
発生して反り補正圧電素子に供給する補正電圧発生回路
を設けて構成される。SUMMARY OF THE INVENTION The present invention relates to a warp correction mechanism for a probe card, which includes a warp detection piezoelectric element for detecting a warp generated on the surface of the probe card due to a rise in inspection temperature. A warp correction piezoelectric element that applies a force in the opposite direction to the warp and corrects the warp is bonded in parallel. Further, a correction voltage generating circuit is provided which receives a detection voltage detected by the warp detection piezoelectric element, generates a correction voltage having a phase opposite to the detection voltage and supplies the correction voltage to the warp correction piezoelectric element.
【0005】[0005]
【作用】一般に圧電素子は、加わった外力によりの歪み
(反り)を生じ、これに相当する電圧を発生する。この
反対に電圧を加圧すると反りを生ずる。電圧を基準に考
えると、電圧を発生する反りの方向と、加圧された電圧
による反りの方向は同一である。よって反りにより発生
した電圧に対して、その反対の反りを生ずる電圧、すな
わち逆位相の電圧を与えることにより反りを補正するこ
とができる筈である。この原理により、上記の反り補正
機構においては、検査温度の上昇により生じたプローブ
カードの反りを反り検出圧電素子が検出し、反りに応じ
た検出電圧を出力する。検出電圧は補正電圧発生回路に
入力し、これと逆位相の補正電圧が発生して反り補正圧
電素子に供給され、プローブカードの反りに対して逆方
向の力が与えられる。両圧電素子はプローブカードの表
面に並列に配設されているので、プローブカードに対し
て等量の作用をなして反りが零またはこれの近くに補正
され、各プローブピンの探針が対応したパッド端子に良
好に接触する。In general, a piezoelectric element is distorted (warped) by an applied external force, and a voltage corresponding to this is generated. On the contrary, when a voltage is applied, warpage occurs. Considering the voltage as a reference, the direction of the warp that generates the voltage and the direction of the warp due to the applied voltage are the same. Therefore, with respect to the voltage generated by the warp, the warp should be able to be corrected by giving a voltage that causes the opposite warp, that is, a voltage having an opposite phase. According to this principle, in the above-mentioned warp correction mechanism, the warp detection piezoelectric element detects the warp of the probe card caused by the rise of the inspection temperature, and outputs the detected voltage according to the warp. The detection voltage is input to the correction voltage generation circuit, a correction voltage having a phase opposite to the detection voltage is generated and supplied to the warp correction piezoelectric element, and a force in the opposite direction is applied to the warp of the probe card. Since both piezoelectric elements are arranged in parallel on the surface of the probe card, the same amount of action is applied to the probe card and the warp is corrected to zero or near this, and the probe pin of each probe pin corresponds. Good contact with pad terminals.
【0006】[0006]
【実施例】図1はこの発明の一実施例を示す。被検査の
ウエハ1を検査ステージ4に載置し、図示しないXYZ
移動機構によりXまたはY方向に移動し、Z方向に昇降
する。ウエハ1の上方に、ヘッド5a と固定リング5b
よりなるテストヘッド5を設け、取り付けボルト5c を
用いて、プローブカード3の周辺を固定リング5bに固
定する。プローブカード3の開口部3a の両側に、反り
検出圧電素子(A)61, 同(B)63 と、反り補正圧電
素子(A)62, 同(B)64 を対称的に配設し、反りを
確実に検出または補正できるように、各圧電素子をプロ
ーブカード3の表面に接着させる。各圧電素子を補正電
圧発生回路7に接続する。なお、開口部3a の両側に各
圧電素子を対称的に配設する理由は、反りは両側でかな
らずしもバランスしないので、これを確実に補正するた
めである。図2は補正電圧発生回路7の概略の構成を示
し、反り検出圧電素子(A)61,(B)63の検出電圧の
位相を反転する位相反転器71,73 と、それぞれの出力電
圧を適当なレベルに調整するアンプ72,74 とにより構成
され、各アンプの出力は補正電圧として反り補正圧電素
子(A)62,(B)64にそれぞれ供給される。1 shows an embodiment of the present invention. The wafer 1 to be inspected is placed on the inspection stage 4, and the XYZ (not shown)
The moving mechanism moves in the X or Y direction and moves up and down in the Z direction. Above the wafer 1, a head 5a and a fixing ring 5b are provided.
The test head 5 is provided, and the mounting bolt 5c is used to fix the periphery of the probe card 3 to the fixing ring 5b. The warp detection piezoelectric elements (A) 61 and (B) 63 and the warp correction piezoelectric elements (A) 62 and (B) 64 are symmetrically arranged on both sides of the opening 3a of the probe card 3 to prevent warpage. Each piezoelectric element is bonded to the surface of the probe card 3 so that the above can be detected or corrected reliably. Each piezoelectric element is connected to the correction voltage generation circuit 7. The reason why the piezoelectric elements are symmetrically arranged on both sides of the opening 3a is that the warp is not always balanced on both sides, so that the warp is surely corrected. FIG. 2 shows a schematic configuration of the correction voltage generating circuit 7, which includes phase inverters 71 and 73 for inverting the phases of the detection voltages of the warp detection piezoelectric elements (A) 61 and (B) 63, and the respective output voltages. The amplifiers 72 and 74 are adjusted to various levels, and the output of each amplifier is supplied as a correction voltage to the warp correction piezoelectric elements (A) 62 and (B) 64, respectively.
【0007】図1と図2により、プローブカード3の反
り補正と、LSIチップ2の検査方法を説明する。XY
Z移動機構によりウエハ1はXまたはY方向に移動し、
目的のLSIチップ2を開口部3a の位置に停止し、つ
いでZ上昇して各パッド端子2a を対応した探針3c に
接触させる。ウエハ1に対する加熱の影響により、プロ
ーブカード3に発生した反りは、反り検出圧電素子
(A)61,(B)63によりそれぞれ検出される。各検出
電圧は補正電圧発生回路7に入力し、検出電圧と逆位相
で適当なレベルの補正電圧が出力され、反り補正圧電素
子(A)62,(B)64にそれぞれ入力して反りが零また
はこれに近くに補正される。この補正により、各探針3
c が対応したパッド端子2a に確実に接触し、LSIチ
ップ2に対して信頼性のある検査がなされる。A warp correction of the probe card 3 and a method of inspecting the LSI chip 2 will be described with reference to FIGS. 1 and 2. XY
The wafer 1 is moved in the X or Y direction by the Z moving mechanism,
The target LSI chip 2 is stopped at the position of the opening 3a, and then Z-lifted to bring each pad terminal 2a into contact with the corresponding probe 3c. The warp generated in the probe card 3 due to the effect of heating the wafer 1 is detected by the warp detection piezoelectric elements (A) 61 and (B) 63, respectively. Each detection voltage is input to the correction voltage generation circuit 7, a correction voltage of an appropriate level is output in a phase opposite to the detection voltage, and the correction voltages are input to the warp correction piezoelectric elements (A) 62 and (B) 64, respectively, and the warp is zero. Or it will be corrected near this. By this correction, each probe 3
The pad terminal 2a corresponding to c is surely brought into contact with the pad terminal 2a, and the LSI chip 2 is inspected with reliability.
【0008】[0008]
【発明の効果】以上の説明のとおり、この発明によるプ
ローブカードの反り補正機構においては、検査温度の上
昇によりプローブカードに生じた反りを、反り検出圧電
素子により検出し、補正電圧発生回路により検出電圧と
逆位相の補正電圧を発生して反り補正圧電素子に供給
し、プローブカードの反りを補正し、各プローブピンの
探針をLSIチップの対応するパッド端子に確実に接触
させるもので、信頼性のあるLSIチップ検査に寄与す
るところには大きいものがある。As described above, in the warp correction mechanism of the probe card according to the present invention, the warp generated in the probe card due to the rise in the inspection temperature is detected by the warp detection piezoelectric element and detected by the correction voltage generation circuit. Generates a correction voltage in the opposite phase to the voltage and supplies it to the warpage correction piezoelectric element to correct the warpage of the probe card and ensure that the probe pin of each probe pin contacts the corresponding pad terminal of the LSI chip. There is a big part that contributes to a proper LSI chip inspection.
【図1】 この発明の一実施例を示す。FIG. 1 shows an embodiment of the present invention.
【図2】 図1における補正電圧発生回路の概略の構成
を示す。FIG. 2 shows a schematic configuration of a correction voltage generation circuit in FIG.
【図3】 (a) はウエハに形成されLSIチップの説明
図、(b) はLSI検査用のプローブカードの一例を示す
図、(c) はプローブカードによるLSIチップの検査方
法の説明図である。3A is an explanatory diagram of an LSI chip formed on a wafer, FIG. 3B is a diagram showing an example of a probe card for LSI inspection, and FIG. 3C is an explanatory diagram of an LSI chip inspection method by the probe card. is there.
【図4】 プローブカードの反りによる接触不良の説明
図である。FIG. 4 is an explanatory diagram of contact failure due to warpage of the probe card.
1…ウエハ、2…LSIチップ、2a …パッド端子、2
b …電子回路パターン、3…プローブカード、3a …開
口部、3b …プローブピン、3c …探針、4…検査ステ
ージ、5…テストヘッド、5a …ヘッド、5b …固定リ
ング、5c …取り付けボルト61…反り検出圧電素子
(A)、63…反り検出圧電素子(B)、62…反り補正圧
電素子(A)、64…反り補正圧電素子(B)、7…補正
電圧発生回路、71,73 …位相反転器、72,74 …アンプ。1 ... Wafer, 2 ... LSI chip, 2a ... Pad terminal, 2
b ... Electronic circuit pattern, 3 ... probe card, 3a ... opening, 3b ... probe pin, 3c ... probe, 4 ... inspection stage, 5 ... test head, 5a ... head, 5b ... fixing ring, 5c ... mounting bolt 61 Warp detection piezoelectric element (A), 63 ... Warp detection piezoelectric element (B), 62 ... Warp correction piezoelectric element (A), 64 ... Warp correction piezoelectric element (B), 7 ... Correction voltage generating circuit, 71, 73 ... Phase inverter, 72,74… Amplifier.
Claims (1)
ド端子に対して、プローブカードのプローブピンを接触
させて行う、該LSIチップの検査において、該プロー
ブカードの表面に対して、検査温度の上昇により該プロ
ーブカードに生ずる反りを検出する反り検出圧電素子
と、該反りに対して逆方向の力を与えて補正する反り補
正圧電素子とを並列に接着し、かつ、該反り検出圧電素
子の検出電圧を入力し、該検出電圧と逆位相の補正電圧
を発生し、前記反り補正圧電素子に供給する補正電圧発
生回路を設けて構成されたことを特徴とする、プローブ
カードの反り補正機構。1. In the inspection of an LSI chip, which is performed by bringing a probe pin of a probe card into contact with a pad terminal of an LSI chip formed on a wafer, an increase in inspection temperature with respect to the surface of the probe card. A warp detection piezoelectric element that detects a warp that occurs in the probe card and a warp correction piezoelectric element that corrects by applying a force in the opposite direction to the warp are bonded in parallel, and the warp detection piezoelectric element is detected. A warp correction mechanism for a probe card, comprising a correction voltage generation circuit that receives a voltage, generates a correction voltage having a phase opposite to the detection voltage, and supplies the correction voltage to the warp correction piezoelectric element.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4090255A JP2802849B2 (en) | 1992-03-16 | 1992-03-16 | Probe card warpage correction mechanism |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4090255A JP2802849B2 (en) | 1992-03-16 | 1992-03-16 | Probe card warpage correction mechanism |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH05264590A true JPH05264590A (en) | 1993-10-12 |
JP2802849B2 JP2802849B2 (en) | 1998-09-24 |
Family
ID=13993390
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP4090255A Expired - Lifetime JP2802849B2 (en) | 1992-03-16 | 1992-03-16 | Probe card warpage correction mechanism |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2802849B2 (en) |
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JP2005164600A (en) * | 2000-03-17 | 2005-06-23 | Formfactor Inc | Method and apparatus for planarizing semiconductor contactor |
JP2005338061A (en) * | 2004-05-28 | 2005-12-08 | Feinmetall Gmbh | Inspection device for electric test for inspection article |
US7002363B2 (en) | 2001-11-02 | 2006-02-21 | Formfactor, Inc. | Method and system for compensating thermally induced motion of probe cards |
US7262611B2 (en) | 2000-03-17 | 2007-08-28 | Formfactor, Inc. | Apparatuses and methods for planarizing a semiconductor contactor |
US7285968B2 (en) | 2005-04-19 | 2007-10-23 | Formfactor, Inc. | Apparatus and method for managing thermally induced motion of a probe card assembly |
WO2009066852A1 (en) * | 2007-11-22 | 2009-05-28 | Semics Inc. | Method and apparatus for controlling position of z-axis for wafer prober |
-
1992
- 1992-03-16 JP JP4090255A patent/JP2802849B2/en not_active Expired - Lifetime
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US7262611B2 (en) | 2000-03-17 | 2007-08-28 | Formfactor, Inc. | Apparatuses and methods for planarizing a semiconductor contactor |
JP2005164600A (en) * | 2000-03-17 | 2005-06-23 | Formfactor Inc | Method and apparatus for planarizing semiconductor contactor |
JP2005164601A (en) * | 2000-03-17 | 2005-06-23 | Formfactor Inc | Method and apparatus for planarizing semiconductor contactor |
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WO2003014755A1 (en) * | 2001-08-06 | 2003-02-20 | Tokyo Electron Limited | Device for measuring characteristics of probe cards and probing method |
JP2003050271A (en) * | 2001-08-06 | 2003-02-21 | Tokyo Electron Ltd | Probe card characteristic measuring device, probe device and probe method |
US6809536B2 (en) | 2001-08-06 | 2004-10-26 | Tokyo Electron Limited | Apparatus for measuring properties of probe card and probing method |
US7119564B2 (en) | 2001-11-02 | 2006-10-10 | Formfactor, Inc. | Method and system for compensating thermally induced motion of probe cards |
US7002363B2 (en) | 2001-11-02 | 2006-02-21 | Formfactor, Inc. | Method and system for compensating thermally induced motion of probe cards |
US7071714B2 (en) | 2001-11-02 | 2006-07-04 | Formfactor, Inc. | Method and system for compensating for thermally induced motion of probe cards |
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JP2005338061A (en) * | 2004-05-28 | 2005-12-08 | Feinmetall Gmbh | Inspection device for electric test for inspection article |
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US7592821B2 (en) | 2005-04-19 | 2009-09-22 | Formfactor, Inc. | Apparatus and method for managing thermally induced motion of a probe card assembly |
WO2009066852A1 (en) * | 2007-11-22 | 2009-05-28 | Semics Inc. | Method and apparatus for controlling position of z-axis for wafer prober |
US8368414B2 (en) | 2007-11-22 | 2013-02-05 | Semics Inc. | Method and apparatus for controlling position of Z-axis for wafer prober |
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JP2802849B2 (en) | 1998-09-24 |
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