JPH05250270A - Data memory write control circuit - Google Patents

Abstract

PURPOSE:To prevent data from being written in a wrong address at the data memory write control circuit. CONSTITUTION:This circuit is provided with a first state monitor circuit 1 to monitor the mutual states of address decode, address coincidence, read/write signal and data output enable fed back from a second state monitor circuit 2, differentiation circuit 3 to generate the write enable of a data memory by differentiating the data output enable and second state monitor circuit 2 to monitor the mutual states of output enable and the write enable from the differentiation circuit 3. Thus, data can be prevented from being written in the wrong address.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data memory write control circuit for preventing erroneous setting of data memory writing.

[0002]

2. Description of the Related Art FIG. 4 is a diagram showing a read / write control of a data memory, and FIG. 5 is a diagram showing a circuit of a write controller of a conventional example. In the following, according to FIG. 4, writing (writing) and reading (reading) of the data memory
The write operation of the conventional example will be described with reference to FIGS.

FIG. 6 is a timing chart showing the normal operation timing of the conventional one embodiment circuit, and FIG. 7 is a chart showing the abnormal operation timing of the conventional one embodiment circuit. Both read / write timing operations will be described below.

In FIGS. 4 to 7, reference numeral 11 denotes an N-ary counter which is initialized to, for example, a value'M 'at a constant period of the first system clock (a) and counts up at the second system clock (b). Then, the N-ary counter 11 outputs the clock 1 (b), the clock 2 (c), the clock 3 (d), and the read address (e) of the data memory 10.

An address decoder 12 outputs an address decode (g) obtained by decoding the read address (e). 13 is a data memory to be set by a microprocessor (not shown) via the microprocessor bus 15.
An address match detection circuit that detects the match between the address value obtained by subtracting the write address from the register 16 storing the 10 write addresses and the value of the read address (e) and outputs the address match (f). is there.

Reference numeral 14 is a clock 1 from the N-ary counter 11.
(b), clock 2 (c), clock 3 (d) and address decoder 1
Address decode from 2 and address match detection circuit 1
Input the address match (f) from 3 and the read / write signal from the register 16, and set the output enable (j) to set the read stop period of the data memory 10 and the data to set the write period of the data memory 10. The write control unit outputs each signal of output enable (k) and write enable (l) of writing execution of the data memory 10, and the address select for switching the read address (e) and the write address at the time of read / write.

Reference numeral 16 is a register for storing the write address of the data memory 10, and 17 is a register for storing the write data. Further, 18 is a selector for selecting either the read address (e) from the N-ary counter 11 or the write address from the register 16 by write select from the write control unit 14, and 10 is a data memory for exchanging data. Is.

The operation of the write controller will be described in detail below with reference to FIGS. In FIG. 5, 14a is a state monitoring circuit, and 14b and 14c are differentiating circuits. Condition monitoring circuit 14a
Is the read / write signal from the register 16, the address match (f) from the address match detection circuit 13, the address decode (g) from the address decoder 12, and the clock 3 (d).
Is input, and the output enable (j) and the address select of the inverse logic of the output enable (j) are output.

Differentiating circuit 14b is output enable
Input (j) and clock 2 (c) and output data output enable (k). The differentiating circuit 14c inputs the data output enable (k) and the clock 1 (b) and outputs the write enable (l).

Signals (a) to signals shown in FIGS. 4 to 5 will be described below.
(l) will be described with reference to FIGS. 6 and 7. (a) is the first system clock input to the N-ary counter 11,
The read address (e) of the binary counter 11 is set to a predetermined value M, for example.
Initialize to.

(B) is the second system clock input to the N-ary counter 11 and the clock 1 (b) output from the N-ary counter 11, which is the basic clock of this circuit. (c) is the clock 2 output from the N-ary counter 11, is the second system clock (b) divided by 1/2, and (d) is the clock 3 output from the N-ary counter 11. , The second system clock (b) divided by 1/4.

(E) is the read address of the data memory 10 output from the N-ary counter 11, and in this example, the clock 3
It is set to the same cycle as (d). (f) is an address match output from the address match detection circuit, for example, an address value (M
-1) and the address value (M-1) of the read address (e). This address match (f) becomes'H 'at the rising timing of the clock 3 (d) corresponding to the address value (M-1) and becomes'L' at the next falling timing of the clock 3 (d). It is a rolling signal.

(G) is an address decode made by decoding the fourth clock 1 (b), which is obtained from the logical product of the clock 2 (c) and the clock 3 (d). For example, it is a signal that becomes'H 'between timings and.

(H) and (i) are intermediate signals for explaining the operation of the write controller 14, and the signal (h) is obtained from the logical product of the positive components of the signal (f) and the signal (g), Also, the signal (i) is the signal
It is obtained from the logical product of the negative component of (f) and the positive component of signal (g).

(J) is an output enable output from the state monitoring circuit 14a for setting the read stop period of the data memory 10, and is "H" of the signal (h) at the falling timing of the clock 3 (d). Is read and becomes "H", and "H" of the signal (i) is read and becomes "L" at the next falling timing of the clock 3 (d).

(K) is a data output enable for setting the writing period of the data memory 10 output from the differentiating circuit 14b, and reads "H" of the signal (j) at the rising timing of the clock 2 (c). This signal becomes L'and becomes'H 'at the next rising timing of the clock 2 (c).

(L) is a write enable (l) for writing execution of the data memory 10 output from the differentiating circuit 14c, which is a signal at the falling timing of the clock 1 (b).
Read'L 'of (k) and become'L', clock 1
It is a signal which becomes'H 'at the next falling timing of (b).

As shown in FIG. 6, during normal operation of the write control unit 14, the microprocessor attempts to write to the value M of the read address (e) of the data memory 10 in the register.
When the data M is written to 16 and any data is written to the register 17, the address match detection circuit 13 detects and outputs the address match (f) when the value of the read address (e) is M-1, and outputs the output. The read of the data memory 10 is stopped by setting the enable (j) to'H 'and the write address from the register 16 is sent to the selector 18 by using the address selection of the inverse logic of'H' of the output enable (j). Is output to the data memory 10, and the bidirectional buffer 19 is turned on by setting the data output enable (k) obtained by rising and differentiating the output enable (j) to'L 'to turn on the data from the register 17. The period of write enable (l) obtained by differentiating the data output enable (k) by falling to the data memory 10, that is, clock 1
The data from register 17 is stored in the data memory between the falling timing and the falling timing in (b).
Write to 10.

However, in the area A shown in FIG.
When an abnormality occurs in the system clock (b), the N-ary counter 11 does not count up normally, the phases of the clock 2 (c) and the clock 3 (d) change, and an address value other than the address value M Address value M with (M + 1)
The data corresponding to will be written.

[0020]

Therefore, in the conventional circuit, the phases of clock 1, clock 2, and clock 3 for generating write enable, output enable, address select, and data output enable are changed due to internal factors. In that case, there is a problem that data is written to the data memory at different addresses.

According to the present invention, after the write enable is output, the data output enable is controlled in the write enable output state and the output enable output is controlled in the data output enable output state to prevent the writing of data to different addresses. The purpose is to

[0022]

In order to achieve the above object, according to the present invention, address decoding, address matching, and read / write signals are used in reading / writing data memory at system timing having a fixed cycle. And a first state monitoring circuit 1 for monitoring the mutual states of the data output enable fed back from the second state monitoring circuit 2 and outputting the output enable of the monitoring result and the address select of the inverse logic to the output enable.
And a differentiating circuit 3 for differentiating the data output enable to generate a write enable of a data memory, and monitoring the mutual states of the output enable and the write enable from the differentiating circuit 3, and the data output enable of the monitoring result. And a second state monitoring circuit 2 for outputting the above, and by mutually monitoring the states of the first state monitoring circuit 1 and the second state monitoring circuit 2 until the write enable of the data memory is completed. , Configure to prevent writing to different addresses.

[0023]

As shown in FIGS. 1 to 3, according to the present invention, in the first state monitoring circuit 1, the address decode signal is'H ', the address match signal is'H', and the read / write signal is'H '.
At this time, the output enable is set to "H" to stop the reading of the data memory, and the address select is set to "L" to switch the address of the data memory to the writing.

Furthermore, the condition for setting the output enable to "L" is "L" if the rising edge of the clock 3 is input during the period when the address match is "L" and the address decode is "H". If the data output enable which is the output of the second state monitoring circuit 2 is'L 'when the rising edge is input, the output enable is'H' until the next falling edge of the clock 3 is input. Try to hold it.

Therefore, in the differentiating circuit 3, the data output enable output "L" from the second state monitoring circuit 2 is given.
To generate a write enable, and the write enable is returned to the second state monitoring circuit 2 as a monitoring input, whereby the write enable is monitored with respect to different addresses until the writing is completed in the data memory. Writing can be prevented.

[0026]

Embodiments of the present invention will be described in detail below with reference to FIGS. FIG. 2 is a diagram showing the circuit configuration of an embodiment of the present invention, and FIG. 3 is a diagram showing the timing of abnormal operation of the circuit of an embodiment of the present invention.

2 to 3, the same components as those shown in FIGS. 4 to 7 are represented by the same symbols, and the initial value of the output enable (j) is'L '(level' 0 '), The initial values of the address select, data output enable (k) and write enable (l) are'H '(level' 1 ').

Reference numeral 1 denotes AND gates 1a and 1b for input AND operation.
Is a first state monitoring circuit having an inverter 1c for inverting the input and output and a J-KFF 1d for JK flip-flop operation. In the first state monitoring circuit 1, the read / write signal'H '(during writing) indicating the read / write state and the address decode (g)' H 'output indicating the value “M” of one address in the data memory are output. AND output of'H 'of address match (f) which indicates the address of the data memory to be written
When input to 1a, AND gate 1a outputs'H 'output J-
Input to J of KFF1d.

The "H" output of the address match (f) is input to the inverter 1c, the "L" output of the inverter 1c is input to the AND gate 1b, and the "L" output from the AND gate 1b is J. -Input to K of KFF1d.

When the rising edge of the clock 3 (d) is input to the J-KFF1d during the'H 'period of the address match (f), the J-KFF1d receives the J input by the rising edge of the clock 3 (d). "H" and "L" of K input are read and "H" of output enable (j) and address select "L" are output from J-KFF1d.

Reference numeral 2 denotes AND gates 2a and 2c for input AND operation.
And a second J-KFF 2b, 2d for JK flip-flop operation and a NAND gate 2e for two-input NAND operation
It is a state monitoring circuit.

"H" of the output enable (j)
When the output is input to the AND gate 2a and the'H 'output of the AND gate 2a is input to the J of the J-KFF 2b, J-K
The FF2b reads the J input'H 'and the K input'L' at the rising edge of the clock 2 (c), and the J-KFF
The output “H” is input from 2b to the NAND gate 2e and the AND gate 2c. Then, the output'L 'of the NAND gate 2e is input to the FF 3a of the differentiating circuit 3.

When the next rising edge of the clock 2 (c) is input, the AND gates 2a, J-KFF2b and J-KF are input.
If the input of F2d is'L ', that is, the write enable (l) which is the output of the OR gate 3c is'L', the output of the NAND gate 2e, that is, the data output enable (k) is'L '.
Hold the output.

On the other hand, if the write enable (l) which is the output of the OR gate 3c is "H", the output of the NAND gate 2e, that is, the data output enable (k) becomes "H". In the figure, 3 is a differentiating circuit having flip-flop FFs 3a and 3b and an OR gate 3c.

The output'L 'of the NAND gate 2e is FF3a.
Input to, FF3a reads the output'L 'of NAND gate 2e at the rising edge of clock 1 (b),
When the output of the OR gate 3c is input to the OR gate 3c and FF3b, that is, the write enable (k) becomes'L ', and the rising edge of the next clock 1 (b) is input, F
F3b reads "L" at the rising edge and is output to the OR gate 3c, and the output of the OR gate 3c, that is, the write enable (l) becomes "H".

That is, the data output enable (k) which is the output of the NAND gate 2e is returned to the first state monitoring circuit 1, the write enable (l) which is the output of the OR gate 3c is returned to the second state monitoring circuit 2, and the clock 1 Abnormality of each signal (d) to signal (k) is monitored based on the abnormality of (b), clock 2 (c), clock 3 (d), and if there is an abnormality, the reading suspension period of the data memory 10 Extend the time width of output enable (j) for setting for an abnormal period (extended to M + 1 in Fig. 3)
In this way, writing to different addresses in the area A is prevented.

[0037]

As is apparent from the above description, according to the present invention, even if there is an abnormality in the system clock during the read / write operation of the address of the data memory set by the microprocessor, the data By monitoring the output enable, data output enable, and write enable for the memory until the writing to the data memory is completed, writing to different addresses can be prevented, and there is an effect that it greatly contributes to improving the performance of the data memory. ..

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of a write control unit of the present invention.

FIG. 2 is a diagram showing a circuit configuration of an embodiment of the present invention.

FIG. 3 is a diagram showing timing of abnormal operation of the circuit according to the embodiment of the present invention.

FIG. 4 is a diagram showing read / write control of a data memory.

FIG. 5 is a diagram illustrating a circuit of a write control unit according to a conventional example.

FIG. 6 is a diagram showing a timing of a normal operation of a conventional example circuit.

FIG. 7 is a diagram showing a timing of an abnormal operation of a conventional example circuit.

[Explanation of symbols]

 1 is a first state monitoring circuit 2 is a second state monitoring circuit 3 is a differentiating circuit

Claims (1)

[Claims] 1. In data read / write of a data memory at a system timing having a fixed cycle, address decoding, address coincidence, read / write signal, and data output fed back from a second state monitoring circuit (2) A first state monitoring circuit (1) which monitors mutual states of enable and outputs an output enable of a monitoring result and an address selection of an inverse logic to the output enable
And a differentiating circuit (3) for differentiating the data output enable to generate a write enable of the data memory, and monitoring and monitoring the mutual states of the output enable and the write enable from the differentiating circuit (3). Second state monitoring circuit (2) for outputting the result data output enable
Until the write enable of the data memory is completed, the states of the first state monitoring circuit (1) and the second state monitoring circuit (2) are mutually monitored to write to different addresses. A data memory write control circuit characterized by being prevented.