JPH05151090A - Access control circuit - Google Patents

Abstract

PURPOSE:To obtain the access control circuit which prevents the contents of a memory block in a computer system from being destroyed owing to a bug, a runaway, etc., of a program. CONSTITUTION:The coincidence signal 11 of a coincidence detecting circuit 2 which compares the select signal 10 from a 1st address decoder circuit 1 connected to an address bus 30, the signal of a data bus 31, and the signal of a data generating circuit 3 is applied to the data generating circuit 3 to allow access only for a constant time set by a timer circuit 20; even when the program runs away thereafter, the access is automatically disallowed to prevent the memory block from being destroyed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an access control circuit for a memory, I / O, etc. in a computer system.

[0002]

2. Description of the Related Art In recent years, with the remarkable spread of computers, there has been a demand for highly reliable design of access control circuits such as memories and I / O in computer systems.

A conventional access control circuit will be described below with reference to the drawings. As shown in FIGS. 6 and 7, the conventional access control circuit includes a coincidence detection circuit 100, a set / reset circuit (hereinafter abbreviated as RS circuit) 101,
The second address decoder circuit 4, an AND gate 5, a memory block 6, an address bus 30 including an address signal and a control signal for accessing each element, and a data bus 31 including a data signal.

With respect to the access control circuit including the above components, the relationship and operation of each component will be described below.

First, the second address decoder circuit 4
The signal for selecting the memory block 6 is the address bus 30.
When shown above, the selection signal 14 is set to the HIGH level (hereinafter referred to as H). However, the selection signal 14 is A
Since the ND gate 5 performs a logical product with the permission signal 112, the operation of the memory block 6 is limited so that it is active only when the permission signal 112 is H and the selection signal 14 is H.

Next, as shown in FIG. 7, the coincidence detection circuit 1
00 and the RS circuit 101 configure the coincidence detection circuit 100 with the 4-input NAND gate 121 and the negative-input AND gates 122 and 123, respectively, and the RS circuit 101 with the 2-input NOR gates 124 and 125. ,
The detailed operation will be described below. The coincidence detection circuit 10
0 is a logical product of four address signals A12 to A15 in the address bus 30 by the NAND gate 121, and the result is I / O write signal I
The signal 110 is obtained by performing a logical product with OW (negative logic in the figure). On the other hand, the signal 111 is obtained by taking the logical product of the output of the NAND gate 121 and IOR (negative logic in the figure) which is a read signal of I / O. In this case, when the signals from A12 to A15 are address signals indicated by H,
When I / O is written, the output of the NAND gate 121 becomes LOW level (hereinafter referred to as L) and IOW becomes active L, so that the signal 110 becomes H, the signal 111 becomes L, and the output of the NOR gate 124 becomes L. , While NO
The output of the R gate 125 becomes H, and the output signal 112 becomes H. In addition, the signal 112 returns to IOW and the signal 11
Even if 0 becomes L, if both signals 111 are L, they remain H. As a result, the AND gate 5 is opened, and the memory block 6 is activated by the selection signal 14.

On the contrary, when the signals from A12 to A15 are address signals indicated by H, when the I / O is read out, the output of the NAND gate 121 becomes L, the IOR becomes active, and L 110 is L, signal 11
1 becomes H and the output of the NOR gate 125 becomes L, while the output of the NOR gate 124 becomes H, so that the signal 1
12 is L. Further, this signal 112 is maintained at L as long as both signals 111 are at L even if IOR returns to H and the signal 110 becomes L.

As a result, even if the AND gate 5 is closed and the selection signal 14 is activated, the memory block 6 is not activated and its access is restricted.

[0009]

However, in the above-mentioned conventional configuration, the access to the memory block 6 is restricted only by reading or writing the address at which the signal 110 or the signal 111 becomes active. Since it can be turned on and off, it is easy to decipher even if a user places a restriction on access to the memory block 6 in a computer system and keeps the usage secret. In addition, there is a problem that it is difficult to prevent the contents of the memory block 6 from being destroyed by a program bug or runaway.

The present invention solves the above-mentioned problems of the prior art. The access to the memory block 6 or the like is configured to be permitted only if a plurality of fixed procedures are used, and the procedure is fixed for the user of the computer system. If is kept secret, it is difficult to understand and decipher because the contents are not simple. Also, similarly, since the contents are not simple, it is possible to prevent the memory block from being destroyed by a program bug or runaway. Furthermore, since access is permitted only for a fixed time set by the timer circuit, even if the program runs out of control after the access is permitted by the above procedure, the access is automatically disallowed after a certain period of time. An object of the present invention is to provide an access control circuit capable of preventing the contents of a block from being destroyed by a program runaway.

[0011]

In order to achieve this object, an access control circuit of the present invention comprises a first address decoder circuit connected to an address bus composed of an address signal and a control signal, and a data composed of a data signal. A match detection circuit that uses the bus signal as the first comparison signal, a data generation circuit that generates the second comparison signal of the match detection circuit, and a timer circuit that detects the elapse of a fixed time, and A match signal indicating that the select signal output from the first address decoder circuit by writing and the first and second comparison signals output from the match detection circuit match is input to the data generation circuit. , The data generation circuit has the same first address as the second comparison signal for the specific address.
Each time the second comparison signal is written, the second comparison signal is changed, and after performing it N times (N is an integer of 2 or more), the other circuits are operated only during the time set by the timer circuit. Are configured to output a signal that allows them to select.

Further, when the data different from the second comparison signal is written to the specific address, the data generating circuit returns to the initial state.

[0013]

According to the present invention, in the above-mentioned configuration, access to a memory block or the like is not permitted unless a plurality of fixed procedures are used, and when the fixed procedure is kept secret to the user of the computer system, It is difficult to understand and decipher because the content is not simple. Similarly, since the contents are not simple, it is possible to prevent the memory block from being destroyed due to a program bug, runaway, or the like. Furthermore, since access is permitted only for a fixed time set by the timer circuit, even if the program runs out of control after the access is permitted by the above procedure, the access is automatically disallowed after a certain period of time. The contents of the block can be prevented from being destroyed by the program runaway.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

As shown in FIG. 1, the access control circuit of the present invention comprises a first address decoder circuit 1, a match detection circuit 2, a data generation circuit 3, a timer circuit 20, an address bus 30 composed of an address signal and a control signal, The data bus 31 is composed of data signals.

Regarding the access control circuit composed of the above components, the relationship and operation of each component will be described below. The first address decoder circuit 1 includes an address bus 3
When a data write signal for a specific address appears at 0, the selection signal 10 is activated. On the other hand, the data to be written is input from the data bus 31 to the coincidence detection circuit 2 as the first comparison signal 16 and compared with the second comparison signal 13 from the data generation circuit 3. If the first comparison signal 16 and the second comparison signal 13 match, the match detection circuit 2 outputs a match signal 11. Data generation circuit 3
Changes the content of the second comparison signal 13 when both the selection signal 10 and the coincidence signal 11 are activated.
After repeating the above contents N times (N is an integer of 2 or more),
The data generation circuit 3 activates the first access permission signal 12 and activates the timer circuit 20. The second access permission signal 21 is output from the timer circuit 20,
During the time set in the timer circuit 20, access to the circuits connected to the timer circuit 20 is permitted.

Next, FIG. 2 shows a configuration example of the memory block 6 as an example of access control. In the figure,
A second address decoder circuit 4, an AND gate 5,
Although it is composed of a memory block 6, the same components as those in FIG. 1 are designated by the same reference numerals, and the operation of the memory block 6 shown in FIG. 2 will be described.

When the address assigned to the memory block 6 is output to the address bus 30, the second address decoder circuit 4 activates the selection signal 14. At this time, if the second access permission signal 21 is active,
The AND gate 5 is opened, the selection signal 15 becomes active, and the memory block 6 becomes accessible. At this time, if the second access permission signal 21 is not active, the AND gate 5 is closed, the selection signal 15 is always inactive regardless of the state of the selection signal 14, and the memory block 6 is not in the access state.

Here, the memory block 6 means a read-only memory (ROM), a read / writeable memory (RAM), or a combination thereof.

Next, FIG. 3 shows a specific embodiment of the access control circuit of FIG. In FIG. 3, the NAND gate 40 and the inverter 41 constitute the first address decoder circuit 1, and the comparator 42 for comparing the magnitudes represented by ICs such as 74LS85 constitutes the coincidence detection circuit 2 and 74LS163. A synchronous counter 43 typified by an IC such as the above and an AND gate 44 form a data generation circuit 3, and a one-shot timer circuit 45 typified by an IC such as the 74LS221, a resistor R for determining the time. , The capacitor C is used to form the timer circuit 20. 3, the same components as those in FIG. 1 are designated by the same reference numerals, and the operation of the access control circuit will be described. Of the signals of the address bus 30, IOW which is a write signal for I / O is input to the inverter 41.
This signal has a negative logic and becomes L when active. Further, the output of the inverter 41 is input to the NAND gate 40, and when the I / O is written according to the above contents, H is output. The signal from the address bus 30 is connected to the other input of the NAND gate 40. Therefore, in the case of the present embodiment, when all the address signals from A9 to A15 are H and writing to the I / O is performed, the selection signal 10 becomes active. However, the selection signal 10 has a negative logic as shown in the drawing, and the fact that it is active indicates L.

From the data bus 31 to D0, D1, D2, one input of a comparator 42 constituting the coincidence detection circuit 2 is connected.
The 4-bit signal D3 is input, and the second comparison signal 13 from the data generation circuit 3 is input to the other one. Here, if the signals D0 to D3 and the second comparison signal 13 are equal, the comparator 42 outputs H as the coincidence signal 11 because both inputs coincide. If they do not match, the match signal 11 becomes L.

In the data generation circuit 3, the selection signal 10 is input to the clock signal input of the synchronous counter 43.
Further, the coincidence signal 11 is input to the clear (CL) terminal of the synchronous counter 43. The operation of the synchronous counter 43 is performed when the signal input to the clock signal input terminal changes from L to H. Therefore, when the selection signal 10 changes from L to H, that is, when the selection signal 10 changes from active to non-active, the coincidence signal 11 input to the clear terminal of the synchronous counter 43 is H (from D0 of the data bus 31). If the signal of D3 and the second comparison signal 13 match), the synchronous counter 43 is incremented. On the contrary, if the coincidence signal 11 is L (the signals D0 to D3 of the data bus 31 do not coincide with the second comparison signal 13), the synchronous counter 43 is cleared.

In this embodiment, the output of the synchronous counter 43 is
Power Q_A, Q_BIs used as the second comparison signal 13, and Q_ATo
In B2 of the comparator 42, Q_BIs connected to B1. Well
In addition, the first access permission signal 12 causes the AND gate 44 to
Use, Q of the synchronous counter 43 _A, Q_BBoth outputs are H
In the case of, it becomes active (H). You
That is, from the state where the synchronous counter 43 is cleared
When incremented three times, the first access permission signal
12 are active.

The activated first access permission signal 12 activates the one-shot timer circuit 45,
The second access permission signal 2 only for the time determined by R and C
1 is output.

Next, the operation of the address signal, the data signal, and the synchronous counter 43 will be described with reference to FIG. The hatched portion of the address signal in FIG. 4 indicates that the first address decoder circuit 1 is an active address signal. At the same time, when data is written, that is, when the IOW becomes active (L), the selection signal 10 also becomes active (L). The address signal shown in FIG. 4 indicates that writing is performed three times. On the other hand, in the synchronous counter 43, each of Q _A and Q _B is L, that is, it starts from the clear state.

The first write data is D0 to D
Since all 3 are L, and the data matches the second comparison signal 13, the comparator 42 outputs H as the match signal 11 (indicated by 11 in FIG. 4). Therefore, the selection signal 1
At the trailing edge (a) of 0, the synchronous counter 43 increments.

In the second write, since Q _A of the synchronous counter 43 is H, that is, B2 of the comparator 42 is H, only D2 of the signals from D0 to D3 is set to H, and Since the data matches the comparison signal 13, the comparator 42 outputs H as the match signal 11. Therefore, the synchronous counter 43 increments at the trailing edge (b) of the selection signal 10.

Similarly, in the third writing, only D1 of the signals from D0 to D3 is set to H, and the synchronous counter 43 is incremented at the trailing edge (c) of the selection signal 10. Here, Q _A and Q _B of the synchronous counter 43
Since both outputs become H, the first access permission signal 1
2 is active (H) (12 in FIG. 4) ((d part) in FIG. 4).

Next, FIG. 5 shows an example in which write data is wrong, unlike FIG. In FIG. 5, since D0 is also set to H in the second write, the second comparison signal 13 does not match, and the synchronous counter 43 is cleared in FIG. 5B.

As described above, according to this embodiment, the access permission signal can be activated by writing the predetermined data three times to the specific address.
After that, it becomes possible to access the memory block 6 and the like. If the write data is erroneous during the above-mentioned three times of writing, it is cleared when the data generating circuit 3 writes the erroneous data, and the access permission signal remains inactive.

[0031]

As is apparent from the above embodiments, the present invention has a configuration in which access to a memory block or the like is not permitted unless a plurality of fixed procedures are used, and it is fixed to the user of the computer system. If the procedure is kept secret, it is difficult to understand because the content is not simple. Also, because its content is not simple,
It is possible to prevent the memory block from being destroyed by a program bug or runaway. Furthermore, since access is permitted only for a certain period of time determined by the timer circuit, even if the program runs out of control after the access is permitted by the above procedure, access will automatically be denied after a certain period of time elapses. It is possible to realize an excellent access control circuit, which can prevent the contents of a memory block from being destroyed by a program runaway.

[Brief description of drawings]

FIG. 1 is a block diagram of an access control circuit according to an embodiment of the present invention.

[Figure 2] Circuit diagram of the same memory block

FIG. 3 is a partial circuit diagram of the access control circuit.

FIG. 4 is an operation timing chart in the access control circuit.

FIG. 5 is an operation timing chart in the access control circuit.

FIG. 6 is a block diagram of a conventional access control circuit.

FIG. 7 is a partial circuit diagram of the access control circuit.

[Explanation of symbols]

 1 First Address Decoder Circuit 2 Match Detection Circuit 3 Data Generation Circuit 20 Timer Circuit 30 Address Bus 31 Data Bus

Claims (2)

[Claims] 1. A first address decoder circuit connected to the address bus, comprising an address bus composed of an address signal and a control signal and a data bus composed of a data signal as constituent elements, and a signal of the data bus being a first circuit. Of the coincidence detection circuit for generating the second comparison signal of the coincidence detection circuit, and a timer circuit for detecting the passage of a fixed time, and writing to a specific address. A select signal output from the first address decoder circuit and a match signal indicating that the first and second comparison signals output from the match detection circuit match each other are input to the data generation circuit, and The data generation circuit changes the second comparison signal every time the first comparison signal that is the same as the second comparison signal is written to the specific address, and changes the second comparison signal to N (N is an integer of 2 or more)
An access control circuit arranged to output a signal permitting the system to select another circuit only after a time set by the timer circuit after execution. 2. The access control circuit according to claim 1, wherein the data generation circuit is arranged so as to return to an initial state when data different from the second comparison signal is written to the specific address.