JPH04102147A - Access control circuit - Google Patents

Abstract

PURPOSE:To make decoding hard and to prevent a memory block from being destroyed by the bugging or running-away of a program by permitting the access of the memory block or the like only when plural decided procedures are used. CONSTITUTION:When the write signal of a data to a specified address is outputted to an address bus 30, an address decoder circuit 1 makes a select signal 10 active and the data to be written is inputted from a data bus 31 to a coincidence detection circuit 2 as a first comparing data and compared with a second comparing data 13 from a data generation circuit 3. When the first and second comparing data are coincident, the coincidence detection circuit 2 outputs a coincidence detection signal 11. When both the select signal 10 and the coincidence detection signal 11 are made active, the data generation circuit 3 changes the contents of the second comparing signal 13 and after repeating these contents, the data generation circuit 3 makes an access permitting signal 12 active so as to permit the access of connected circuits. Thus, decoding is made difficult and the memory block can be prevented from being destroyed by the bugging and running away of the program.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a memory in a computer system.
This relates to access control circuits such as O.

2. Description of the Related Art Access control of memory, Ilo, etc. in a conventional computer system will be described below.

FIGS. 6 and 7 are circuit configuration diagrams illustrating a conventional access control system and a circuit showing a specific example of its essential parts. In FIG. 6, 100 is a match detection circuit, 101
is an R3 circuit controlled by the coincidence detection circuit 100, 4 is an address decoder circuit, 5 is an AND gate that takes the logical product of the output of the R8 circuit 101 and the output of the address decoder circuit 4,
Reference numeral 6 denotes a memory block which becomes active by the output of the AND gate 5. 30 is an address bus consisting of address signals and control signals for accessing each element, 31 is a data bus consisting of data signals, and the coincidence detection circuit 100
, AD of address decoder circuit 4 and memory block 6
The D end is connected to the address bus 30 and the memory block 6
The DATA end of is connected to the data bus 31.

Here, when the signal for selecting the memory block 6 is shown on the address bus 30, the address decoder circuit 4
The selection signal 14 is set to high level (hereinafter referred to as H). However, the selection signal 14 is
The memory block 6 is activated by the selection signal 15 output from the AND gate 5 only when the permission signal 112 is H and the selection signal 14 is H. Its operation is restricted.

Next, - loading and unloading circuit fi100, R8 circuit 101, signal 1
10, 111, and 112 will be explained using the specific circuit example shown in FIG. In Figure 7, 121 is 4
Manual NAND gate, 122 and 123 are negative input A
The coincidence detection circuit 100 is constituted by the ND gate as described above. Also, 124 and 125 are N for two people.

In the R gate, R3 times N101 is configured as described above.

The operation will be explained below. Coincidence detection circuit 100
As shown in FIG. 7, A1 of the address bus 3G
The four address signals from 2 to A15 are ANDed by the N'AND gate 121, and the result is ANDed with the Ilo write signal l0W (negative logic in the figure) to obtain the signal 110. ing. On the other hand, a signal 111 is obtained by logically multiplying the output of the NAND gate 121 and I0R (negative logic in the figure), which is the readout signal of Ilo. In this case, when Ilo is written to the address where the signals A12 to A15 are H, N
The output of the AND gate 121 becomes low level (hereinafter referred to as "IOW"), IOW becomes active, so the signal 110 becomes H1, the signal 111 becomes L, and the NOR gate) 12
On the other hand, the output of NOR gate 125 becomes H, so the permission signal 112 becomes H.

Also, this signal permission 112 means that IOW returns to H and signal 1
Even if 1G becomes L, if signal 111 remains together,
H's! Resolutely maintained up to l. As a result, AND gate 5
is opened, and the memory block 6 is activated by the selection signal 14.

Conversely, when Ilo is read from an address where signals A12 to A15 are H, NA
The output of the ND gate 121 becomes high, the IOR becomes active, the signal 11G becomes high, the signal 111 becomes H, and the output of the NOR gate 125 becomes Ll, while the NOR
The output of the gate 124 becomes H, so the enable signal 112
yelled L. Further, even if the IOR returns to H and the signal 111 becomes L, the signal permission 112 remains at L if the signal 11G is also set. This results in AN
Even if the D gate 5 is closed and the selection signal 14 becomes active, the selection signal 15 does not become active, so the memory block 6 does not become active and its access is restricted.

Problems to be Solved by the Invention However, in the above configuration, access to the memory block 6 cannot be restricted or removed simply by reading or writing to an address where the signal 110 or the signal 111 becomes active. Therefore, in a computer system, etc., restrictions are placed on access to the memory block 6 by the user.
Moreover, even if the usage method is kept secret, it is easy to be decoded, and it is also difficult to prevent the contents of the memory block 6 from being destroyed by program bugs, runaways, etc.

In view of the above problems, the present invention has a configuration in which access to a memory block, etc. is not permitted unless a plurality of predetermined procedures are used, and the predetermined procedures are kept secret from the user of the computer system. In this case, since the contents are not simple, it is difficult to understand << and difficult to decode, and similarly, because the contents are not simple, it is necessary to prevent the memory program from being destroyed by program bugs, runaways, etc. The purpose of the present invention is to provide an access control circuit that enables the following.

Means for Solving the Problems In order to solve the above problems, the access control circuit of the present invention has an address decoder circuit connected to an address bus consisting of address signals and control signals, and an address decoder circuit connected to a data bus consisting of data signals. A coincidence detection circuit that uses the signal of the lever data bus as first comparison data, and a data generation circuit that generates second comparison data for the minus number output circuit, and writes to a specific address. inputting a selection signal outputted from the address decoder circuit and a signal outputted from the minus number decoding circuit indicating that the first and second comparison data match to the data generation circuit; The data generation circuit changes the second comparison data every time the first comparison data that is the same as the second comparison data is written to the specific address, and changes the second comparison data N times (N is 2 or more). (integer)) is configured to output a signal that allows the system to select another circuit.

Furthermore, when data different from the second comparison data is written to the specific address, the data generating circuit is returned to the initial state.

Effect: With this configuration, users are required to follow multiple predetermined procedures to access memory programs, etc., and if the predetermined procedures are kept secret from the users of the computer system, , since its contents are not simple, it is difficult to understand<<, and it is difficult to decode, and similarly, because its contents are not simple, it is possible to prevent the memory block from being destroyed by program bugs, runaways, etc. .

EXAMPLE An example of the present invention will be described below with reference to the drawings.

FIG. 1 is a circuit diagram showing an access control circuit according to an embodiment of the present invention. In FIG. 1, 1 is an address decoder circuit, 2 is a coincidence detection circuit, and 3 is a data generation circuit. It is controlled by a coincidence detection signal 11 and outputs an access permission signal 12 and comparison data 13. 3G is an address bus consisting of address signals and control signals, and 31 is a data bus consisting of data signals. The address bus 30 is connected to the address decoder circuit 1, and the data bus 31 is connected to the coincidence detection circuit 2.

The operation will be explained below. Address decoder times R
1 makes the selection signal 10 active when a data write signal for a specific address is output to the address bus 30. On the other hand, the data to be written is input to the coincidence detection circuit 2 from the data bus 31 as first comparison data, and is compared with the second comparison data 13 from the data generation port 83. If the first and second comparison data match, the minus number generating circuit 2 outputs a match detection signal 11. The data generation circuit 3 changes the content of the second comparison signal 13 when both the selection signal 10 and the coincidence detection signal 11 become active. After repeating this content N times (N is an integer of 2 or more), the data generation circuit 3 activates the access permission signal 12 and activates 1. and allow access to the circuits connected to it.

FIG. 2 shows an example of a configuration diagram when a memory block is adopted as an example of the object to be access controlled.
In the figure, 4 is an address decoder circuit, 5 is an AND gate, 6 is a memory block, and 14 and 15 are selection signals. Here, the same numbers as in FIG. 1 indicate the same contents as in FIG. 1.

The operation of the memory block shown in FIG. 2 will be explained below. When the address allocated to the memory block 6 is output to the address bus 30, the address decoder circuit 4
makes the selection signal 14 active. At this time, if the permission signal 12 is active, the AND gate 5 is opened, the selection signal 15 is also active, and the memory block 6 becomes accessible. In this case, permission signal 12
is not active, AND gate 5 is closed;
The selection signal 15 is always inactive regardless of the state of the selection signal 14, and the memory block 6 is not in an access state. Here, the memory block 6 refers to read-only memory (ROM) or read/write memory. (RAM) or a complex thereof.

FIG. 3 is a circuit diagram showing a specific embodiment of the access control circuit shown in FIG. 1. In Figure 3, 40 is NAND
The gate 41 is an inverter, and these constitute the address decoder circuit 1.

42 is a magnitude comparator typified by an IC such as 74LS85, which constitutes the coincidence detection circuit 2.

43 is a synchronous counter represented by an IC such as 74L S 163, and 44 is an AND gate, which constitute the data generation circuit 3. In FIG. 3, the same number as the first UjA indicates the same content.

Next, the operation of the access control circuit shown in FIG. 3 will be explained. Of the signals on the address bus 30, the inverter 41
IOW, which is a write signal to o, is input. This signal has negative logic and becomes L when active. Further, the output of the inverter 41 is an input to the AND gate 40, and when the above content is written to Ilo, H is output. A9 to A1 of AND gate 40
The other inputs up to 5 are connected to signals from the address bus 30. Therefore, in the case of this embodiment, from A9 to A
When all address signals up to 15 are at H and writing to Ilo is performed, selection signal 10 becomes active. However, this selection signal 10 has a negative logic as shown in the figure, and being active indicates L.

One input of the comparator 42 constituting the coincidence detection circuit 2 receives the 4-bit signals DO, DI, D2 and D3 from the data bus 31, and the other input receives the data generation port N.
A comparison signal 13 from No. 3 is input. Here, if the signal from DO to D3 and the comparison signal 13 are equal, both inputs of the comparator 42 match, so the match detection signal 11
Outputs H as . If they do not match, the match detection signal 11 goes low.

In the data generation circuit 3, the selection signal 1o is input to the tarock input of the synchronous counter 43. Further, the -number output signal 11 is input to the clear terminal of the synchronous counter 43. The synchronous counter 43 operates when the signal input to the clock input changes from L to H.

Therefore, when the selection signal 1° changes from L to H,
That is, when the selection signal 1° changes from active to non-active, the coincidence detection signal 11 input to the clear terminal of the synchronous counter 43 becomes H (signals from DO to D3 of the data bus 31 match the comparison signal 13). If so, the synchronous counter 43 is incremented. 3!1, -
If the several-sheet output signal 11 is L (signals from Do to D3 of the data bus 31 and the comparison signal 13 do not match), the synchronous counter 43 is cleared.

In this embodiment, the output QA of the synchronous counter 43.

Using QB as comparison data 13, Q
A is connected to 82 of the comparator 42, and QB is connected to 81.

Furthermore, the access permission signal 12 is set to be active (H) by an AND gate 44 when both the QA and QB ratio outputs of the synchronous counter 43 are H, that is, the synchronous counter 43 is in a cleared state. When the number is incremented three times, the permission signal 12 becomes active.

Next, the operations of the address signal, data signal, synchronous counter 43, etc. will be explained using FIG. The hatched part of the address signal in Fig. 4 is the address decoder circuit 1.
This indicates that the address signal is active. At the same time, when data is written, that is, when IOW becomes active (L),
The selection signal 10 also becomes active (L), and in FIG. 4, it shows that writing has been performed three times.
On the other hand, in the synchronous counter 43, QA and QB are each at L, indicating that the process has started from a clear state.

The first write data is all L from Do to D3i, and since the data matches the comparison signal 13 and is 5, the comparator 42 outputs H as the coincidence detection signal 11 as shown in FIG. . Therefore, the trailing edge a of the selection signal 10
Then, the synchronous counter 43 is incremented.

In the second write, QA or B5 of the synchronous counter 43, that is, B2 of the comparator 42, is 1 (so, if only B2 of the signals from DO to B3 is set to H, the comparison signal 13 and the data Since they match, the comparator 42 outputs H as the match detection signal 11 as shown in FIG. 4. Therefore, the synchronous counter 43 increments at the trailing edge of the selection signal 10.

Similarly, in the third write, only Dl of the signals from DO to B3 is set to H, and at the trailing edge C of the match signal 1o,
The synchronous counter 43 is incrementing. Here, QA of the synchronous counter 43.

Since both QB outputs become H, access permission signal 12
is active (H) at point d as shown in FIG.

Next, FIG. 5 shows the case where the write data is incorrect. In FIG. As shown in the figure, the synchronous counter 43 has already been cleared at the trailing edge of the selection signal 10.

As described above, according to this practical example, by writing certain data to a specific address three times, the access permission signal 12 can be activated, and access to the memory block 6 etc. can be made thereafter. Become. Also, write data w4-) in the middle of the above three writes.
In such a case, the access permission signal 12 is cleared when the data generation circuit 3 writes erroneous data, and the access permission signal 12 becomes inactive.

Furthermore, the access permission signal 12 that has become active can be cleared by writing erroneous data to the specific address.

Effects of the Invention As described above, according to the present invention, access to a memory block, etc. is not permitted unless a plurality of predetermined procedures are used, and the predetermined procedures are kept secret from users of the computer system. If so, the content may be difficult to understand because it is not simple. Furthermore, since the contents are not simple, it is possible to realize an access control circuit that can prevent the memory block from being destroyed due to program bugs, runaways, or the like.

[Brief explanation of drawings]

15i1 is a circuit configuration diagram showing one embodiment of the access control circuit of the present invention, FIG. 2 is a circuit configuration diagram for a memory block whose access is restricted, and FIG. 3 is a specific implementation of the access control circuit. Circuit configuration diagram showing an example, No. 45!
1 and 5 are timing diagrams showing the operation of the access control circuit, and FIGS. 6 and 7 are circuit configuration diagrams showing the conventional access control circuit and a specific example of its essential parts. It is a diagram. 1.4...Address decoder circuit, 2...-number configuration circuit, 3...Data generation circuit, 30...Address bus, 31...Data bus, 5, 44.122, 1
23...AND gate, 6...memory block, 4
0.121...NAND gate, 41...Inverter, 42...Comparator, 43...Synchronous counter, 1
24, 125-N OR gate, 10--selection signal, 11--several output signal, 12--permission signal, 13
...Comparison data, 14.15...Selection signal. Agent Yoshihiro Morimoto 3rd 41 - NAND'r"-to 4/ -4nha'-ta 42-Hichoma 43- Synchronous type kakunda 44 4yv game L

Claims (1)

[Claims] 1. An address bus consisting of address signals and control signals;
In a system having a data bus consisting of data signals as a component, an address decoder circuit connected to the address bus, and a coincidence detection circuit connected to the data bus and using the data bus signal as first comparison data. , a data generation circuit that generates second comparison data for the coincidence detection circuit, and a selection signal output from the address decoder circuit by writing to a specific address, and a data generation circuit output from the coincidence detection circuit. and inputs a signal indicating that the first and second comparison data match to the data generation circuit, and the data generation circuit generates the same first comparison data as the second comparison data for the specific address. A signal that changes the second comparison data every time the second comparison data is written, and after performing this N times (N is an integer of 2 or more), allows the system to select another circuit. An access control circuit configured to output. 2. The access control circuit according to claim 1, wherein when data different from the second comparison data is written to the specific address, the data generation circuit returns to an initial state.