JPH0736271B2 - Address signal noise detection circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a noise detection circuit for an address signal, and more particularly, even when noise is input to a semiconductor device, it is notified that noise is input to a control unit of the semiconductor device. , A circuit enabling control of internal operation due to noise.

[Prior Art] Since the conventional semiconductor device is not provided with a circuit for detecting noise, it is not possible to distinguish whether the address has changed normally or has changed due to noise, and therefore, in response to the noise. The output was changing. Usually, since the output circuit of the semiconductor device is composed of a transistor having a large current driving capability, a large transient current flows. As a result, the power supply voltage or the ground voltage changes, and this also supplies noise to other devices or itself, causing a phenomenon that the operation of the system becomes unstable.

In order to solve the above problems, for example, JP-A-58
No. 270712 discloses a noise countermeasure circuit. Sixth
FIG. 1 is a circuit diagram showing a conventional noise countermeasure circuit shown in this publication. As shown in the figure, the conventional noise suppression circuit includes a delay circuit 1, a NOR gate 2, a NAND gate 3,
It is composed of two N-channel transistors 4 and 5 and inverters 6 and 7.

FIG. 7 is a waveform chart of the signals of the respective parts shown in FIG. 7 (a) to 7 (e) are signals a to e shown in FIG.
Respectively correspond to. The operation of the conventional circuit shown in FIG. 6 will be described below with reference to FIG. First, as shown in FIG. 7A, it is assumed that high-level noise is mixed in the low-level portion of the input address signal a and low-level noise is mixed in the high-level portion. The input address signal a is delayed by the delay circuit 1 to become an address signal as shown in FIG. 7 (b). The input address signal a and the delayed address signal b are given to the NOR gate 2 and the NAND gate 3. Therefore, the output c of the NOR gate 2 is as shown in FIG. 7 (c), and the output d of the NAND gate 3 is as shown in FIG. 7 (d). That is, NOR gate 2
High-level noise is removed by the NAND gate 3
Removes low level noise. Further, the logics of these signals c and d are converted into the transistors 4 and 5,
By properly combining the circuits of the inverters 6 and 7, the output signal e as shown in FIG. 7 (e) is finally obtained. As shown in the figure, in the output signal e, both high level noise and low level noise are removed.

[Problems to be Solved by the Invention] As described above, the conventional circuit shown in FIG.
And a plurality of logic gates are appropriately combined to absorb noise equivalent to the delay of the delay circuit 1. However, as is apparent from the time chart of FIG. 7, the output address signal e is a signal delayed by the delay of the delay circuit 1 with respect to the input address signal a. Therefore, when the circuit as shown in FIG. 6 is used, the operation speed (access speed) is delayed by the delay of the delay circuit 1. That is, in the conventional circuit shown in FIG. 6, noise is suppressed at the expense of operating speed. However, the recent technological trend regarding semiconductor devices is directed to how to improve the operation speed, and the conventional circuit shown in FIG. 6 runs counter to such technological trend. Therefore, although the conventional circuit shown in FIG. 6 is shown as an example of the noise countermeasure circuit, it is the fact that it is rarely used in reality.

The present invention has been made to solve the above-mentioned problems, and noise detection of an address signal which can take measures against noise mixed in the address signal without causing a reduction in operating speed. The purpose is to provide a circuit.

[Means for Solving the Problems] A noise detecting circuit for an address signal according to the present invention includes a pulse generating means for generating a pulse having a constant polarity in response to a change in the level of the input address signal, and an input address signal. By combining the logic of the delay means for delaying and the logic of the address signal delayed by the delay means and the original input address signal, the normal level change of the input address signal is caused by the noise of the pulse of the first logic value. An input address signal from a binary signal generating means for generating a binary signal indicating a change with a pulse having a second logical value, and a binary signal generated by the binary signal generating means based on the pulse generated by the pulse generating means. And a means for extracting only a portion of the pulse corresponding to the noise of.

[Operation] In the present invention, the noise pulse included in the input address signal is extracted to create the detection signal. Therefore, if countermeasures against noise are taken based on the detection signal, the operation speed of the semiconductor device is lowered. It is possible to prevent the adverse effect of noise.

[Embodiment] FIG. 1 is a circuit diagram showing an embodiment of the present invention. In the figure, an input address signal a is given to an address change detection circuit (hereinafter referred to as an ATD circuit) 8. The ATD circuit 8 generates a pulse of a constant polarity (high level in this embodiment) in response to a change in the level of the input address signal a, and is used in, for example, an internal synchronous SRAM or the like. ing. The output g of the ATD circuit 8 is the NAND gate A2
It is given to one input terminal. Also, the input address signal a
Is applied to one input terminal of each of the NAND gate A1 and the NOR gate N1 and is also applied to the delay circuit D1. The output b of the delay circuit D1 is applied to the other input ends of the NAND gate A1 and the NOR gate N1. The output of the NAND gate A1 is given to the inverter I1. The output c of this inverter I1 is NOR
It is applied to one input terminal of the gate N2. Also, NOR gate N
The output d of 1 is given to the other input terminal of the NOR gate N2. NO
The output e of the R gate N2 is given to the inverter I2. The output f of the inverter I2 is given to the other input end of the NAND gate A2. The output of the NAND gate A2 is given to the inverter I6. The noise detection signal h is obtained from the inverter I6.

Here, the ATD circuit 8 is composed of a delay circuit D2, three inverters I3 to I5, and two transfer gates T1 and T2. Transfer gates T1 and T2 are
Each is a CMOS switch composed of an N-channel transistor and a P-channel transistor. The input address signal a is given to the delay circuit D2. The output of the delay circuit D2 is applied to one gate electrode of each of the transfer gates T1 and T2. The output of the delay circuit D2 is the inverter I4.
To the other gate electrodes of the transfer gates T1 and T2. The input address signal a is given to the inverter I5 via the transfer gate T1 and is given to the inverter I5 via the inverter I3 and the transfer gate T2. AT from inverter I5
The output signal g of the D circuit 8 is obtained.

2A and 2B are diagrams showing the waveforms of the internal signals in the embodiment shown in FIG. Note that FIG. 2A is a waveform diagram when the input address signal a shows a normal change, and FIG. 2B is a waveform diagram when noise is mixed in the input address signal b. In addition, FIG. 2A (a) to (h)
2B and 2B correspond to the signals a to h shown in FIG. 1, respectively. The operation of the embodiment shown in FIG. 1 will be described below with reference to FIGS. 2A and 2B.

First, the operation of the ATD circuit 8 will be described. In this ATD circuit 8, the inverters I3 to I5 and the transfer gates T1 and T2 form an exclusive OR circuit, and the input address signal a and the address signal delayed by the delay circuit D2 are formed by this exclusive OR circuit. An output signal g as shown in FIG. 2A (g) or FIG. 2B (g) is obtained by taking the exclusive OR of and. Next, the detailed operation of the ATD circuit 8 will be described. When the input address signal a changes from high level to low level, and when the input address signal a
The operation will be described separately for the case where changes from low level to high level.

When the input address signal a changes from high level to low level Immediately after the input address signal a falls from high level to low level, the output of the delay circuit D2 is at high level and the output of the inverter I4 is at low level. is there. Therefore, at this time, the transfer gate T1 is turned on, and the output signal g of the inverter I5 changes opposite to the input address signal a. That is, the output signal g changes from low level to high level. The output of the delay circuit D2 falls from the high level to the low level with a delay of a predetermined delay time from the fall of the input address signal a. In response to this, the inverter I4
Output rises from low level to high level. As a result, the transfer gate T1 is turned off and the transfer gate T2 is turned on. On the other hand, the output of the inverter I3 rises from the low level to the high level earlier than the output of the delay circuit D2 falls from the high level to the low level. Therefore, when the output of the delay circuit D2 changes, the inverter I3 outputs the output signal g.
A low level signal appears which is the inverted high level output of. That is, when the input address signal a changes from high level to low level, a pulse wave of low level → high level → low level appears in the output signal g.

When the input address signal a changes from low level to high level Immediately after the input address signal a rises from low level to high level, the output of the delay circuit D2 is still low level and the output of the inverter I4 is high. It is a level.
Therefore, at this time, the transfer gate T2 is turned on, and the output signal g rises from low level to high level at the same time when the output of the inverter I3 is inverted from high level to low level. On the other hand, the output of the delay circuit D2 falls from the high level to the low level with a delay of a predetermined delay time from the rise of the input address signal a, and in response thereto, the output of the inverter I4 rises from the low level to the high level.
As a result, the transfer gate T2 is turned off and the transfer gate T1 is turned on. Therefore, a low-level signal that is the inversion of the input address signal a appears in the output signal g. That is, when the input address signal a changes from low level to high level, a pulse wave of low level → high level → low level appears in the output signal g.

Summarizing the above cases, even if the input address signal a changes from the high level to the low level or from the low level to the high level, the output signal g has the low level → the high level → the low level. A pulse wave appears, and its pulse width is determined by the delay time of the delay circuit D2.

Next, the overall operation of the embodiment shown in FIG. 1 will be described. First, the operation when the level of the input address signal a changes normally will be described with reference to FIG. 2A. When the input address signal a normally changes from the high level to the low level or from the low level to the high level, the delay circuit D1
Output b has a waveform delayed from the input address signal a by the delay time of the delay circuit D1 (see FIG. 2A (b)). Since the output c of the inverter I1 is the logical product of the original input address signal a and the address signal b delayed by the delay circuit D1, it has a waveform as shown in FIG. 2A (c). The output d of the NOR gate N1 is the original input address signal a.
And the address signal b delayed by the delay circuit D1
Since it is R, the waveform becomes as shown in FIG. 2A (d).
Since the signal e is the NOR of the signals c and d, it becomes a pulse indicating the phase difference between the input address signal a and the delayed address signal b (see FIG. 2A (e). The signal f is shown in FIG. 2A (f). ) Is a reverse phase wave of the signal e. On the other hand, since the signal g is an ATD pulse which has undergone a normal change of the input address signal a, it has a waveform as shown in FIG. 2A (g). Then, comparing the waveforms of (f) and (g) in FIG. 2A, there is no portion where both signals are at the high level at the same time, so the detection signal h which is an AND of the signals f and g. Are all “L” (low level) and no detection pulse is output.

Next, the operation when noise is mixed in the input address signal a will be described with reference to FIG. 2B. When noise as shown in FIG. 2B (a) is mixed in the input address signal a, the output b of the delay circuit D1 has a waveform in which the noise component is delayed as it is as shown in FIG. 2B (b). Therefore, the signals c and d which are the AND of the address signals a and b and NOR
Have waveforms as shown in FIGS. 2B (c) and 2 (d), respectively. Here, the signal c is a signal in which a low-level noise pulse of the input address signal a is represented by a high-level pulse, and the signal d is a high-level noise pulse of the input address signal a represented by a high-level pulse. It has become a signal. Since the signal e is the NOR of the signals c and d, its waveform is as shown in FIG. 2B (e). The signal f is a reverse phase wave of the signal e (see FIG. 2B (f)).
Here, comparing the signal f with the input address signal a, the signal f is a signal in which both the low level noise pulse and the high level noise pulse included in the input address signal a are expressed as high level pulses. Has become. On the other hand, the ATD circuit 8 outputs a pulse having the same waveform as the pulse shown in FIG. 2A (g) for a normal change of the input address signal a (the middle pulse of the waveform shown in FIG. 2B (g)). ). On the other hand, the ATD circuit 8 uses the input address signal a
When responding to the noise mixed in the noise, the ATD pulse has a longer pulse width (depending on the width of the noise pulse) than the normal address change because the noise changes twice in a short time. Although it is different, the maximum pulse width is double. Therefore, when the ATD circuit 8 responds to noise, its output signal g is shown in FIG. 2B (g).
Output a pulse as shown on the left or right side of. NA of the AND of the ATD pulse g and the signal f
The output h of the ND gate A2 and the inverter I6 is
The waveform is as shown in Fig. 2B (h). This Figure 2B (h)
When the waveform shown in FIG. 4 is compared with the waveform of the input address signal a, the output signal h is a signal showing a noise pulse of the input address signal a. Therefore, this output signal h can be used as a noise pulse detection signal.

FIG. 3 shows an example of a circuit for controlling the output of the semiconductor device by using the noise detection signal obtained from the circuit of FIG. By the way, the noise detection circuit shown in FIG. 1 is provided for each bit of the address data composed of a plurality of bits, and the output control can be performed even if noise is mixed into any bit of the address data. , The detection signals h _{1 to} hn of all addresses are given to the NOR gate N3.
Further, an output enable signal inside the semiconductor chip (hereinafter referred to as a signal ▲ ▼) is also input to the NOR gate N3. As a result, each detection signal h _{1 to} hn is
▼ Can be used in place of signals. NOR gate N
The output of 3 is given to one input end of the NAND gate A3 and also given to one input end of the NOR gate N4 via the inverter 17. These NAND gate A3 and NOR gate N4
The data read from the memory (not shown) is applied to the other input terminal of each via the read data bus RD. NAND
The output of the gate A3 is given to the gate terminal of the P-channel type MOS transistor P1. The output of the NOR gate N4 is given to the gate terminal of the N-channel type MOS transistor R1. These transistors P1 and R1 are connected in series between the power supply and the ground, and form a so-called output buffer. Output data DO from the connection point between transistors P1 and R1.
Is taken out.

In the output control circuit of FIG. 3, the transistor P1 and
The output buffer configured with R1 is generally "H" read (P
It has three states: 1: ON, R1: OFF), "L" read (P1: OFF, R1: ON), and output disable (P1: OFF, R1: OFF). That is, either the transistor P1 or R1 turns on in the read state, and the transistors P1 and R1
Both will be turned off. Then, in the output control circuit of FIG. 3, in the read state in which the transistor P1 or R1 is turned on, when noise is mixed in the input address signal, the output is temporarily prohibited to prevent the output from being inverted. Is configured to. Specifically, transistors P1 and R1 operate as follows.

Note that, in the above, noise is generated in the part of →. In this way, as a result of the output inversion being prohibited in the noise portion, a large transient current does not flow in the noise portion, and the influence of noise can be prevented from being transmitted to other devices. Further, in the embodiment shown in FIGS. 1 and 3, since no processing is applied to the address itself given to the memory (not shown), the address signal of the conventional circuit as shown in FIG. The operation speed is not delayed due to the delay.

FIG. 4 is a circuit diagram showing another noise countermeasure circuit using the noise detection signal obtained from the circuit of FIG. In addition,
In FIG. 4, the parts denoted by the same reference numerals as those in FIG. 3 have the same configuration, and the description thereof will be omitted. In the embodiment of FIG. 4, turning on / off of the transistors P1 and R1 forming the output buffer is controlled only by the signal. The noise detection signals h _{1 to} hn are given to the NOR gate N3. The output of the NOR gate N3 is given to one input terminal of the NAND gate A5. At the other input end of this NAND gate A5,
The output signal of the ATD circuit 8 as shown in FIG. 1 is given. The output of the NAND gate A5 is given to the gate terminal of the gate transistor T3 via the inverter I8. The gate transistor T3 is a transistor that controls opening / closing between the read data bus RD and the latch circuit 9. The latch circuit 9 is composed of inverters I9 to I11, and temporarily holds read data from a memory (not shown) provided via the read data bus RD. Usually, in SRAM, in order to save power consumption,
An automatic power-off circuit is provided so that the power is automatically turned off after a lapse of a certain time after reading the data from the memory. Therefore, the latch circuit 9 for temporarily holding the read data is required. By the way, when the above-mentioned noise is mixed in the input address signal, the address data changes, and thereby the data held in the latch circuit 9 is rewritten. However, since the pulse width of a normal noise pulse is extremely narrow, the latched data of the latch circuit 9 may not be rewritten even after the noise ends, and erroneous data may be retained as it is. In this case, the system malfunctions. In order to solve such a problem, noise detection signals h _{1 to} hn of each bit of address data are
When noise is mixed in any bit by the output of, the gate transistor T3 is turned off so that the data held in the latch circuit 9 cannot be rewritten. As a result, the latch circuit 9 always holds the regular data. Therefore, malfunction of the semiconductor device can be prevented.

FIG. 5 is a circuit diagram showing another example of the output control circuit shown in FIG. In this embodiment, in addition to the output transistors P1 and R1 whose output is prohibited by the noise detection signal, another pair of output transistors P2 and R2 whose ON / OFF is controlled only by the signal ▼ are provided. Further, an inverter I12, a NAND gate A4, and a NOR gate N5 are provided corresponding to the inverter I7, the NAND gate A3 and the NOR gate N4. In such a configuration, the current drivability of the output transistors P1 and R1 is selected to be considerably larger than the current drivability of the output transistors P2 and R2. Normally, the stray capacitance of the output data bus to which the output data DO is sent is quite large, so even if either of the output transistors P2 and R2 is turned on at the time of a noise pulse, the level change of the output data DO is small, It is possible to prevent the influence of noise on other devices. In the embodiment shown in FIG. 5, the output data DO does not enter the floating state even when the noise pulse is generated. Therefore, it is suitable for an application in which output data is in a floating state, which is inconvenient.

As described above, the gist of the present invention is to obtain a noise detection signal in which a noise portion is extracted from an input address signal by a circuit as shown in FIG. 1, for example. If such a noise detection signal is used, various noise countermeasures can be taken by the circuits shown in FIGS. 3 to 5, for example. That is, in the present invention, the point is that the noise pulse is not directly removed from the address signal as in the conventional circuit shown in FIG. 6, but the noise countermeasure is indirectly performed based on the signal in which the noise is detected. is there.

[Effects of the Invention] As described above, according to the present invention, it is possible to effectively detect both the noise pulse of the first polarity and the noise pulse of the second polarity included in the input address signal. If a noise countermeasure is taken using this detection signal, it is possible to prevent the adverse effect of noise without causing a delay in the operating speed as in the conventional circuit.

[Brief description of drawings]

FIG. 1 is a diagram showing a noise detection circuit according to an embodiment of the present invention. 2A and 2B are waveform diagrams of signals at various parts of the noise detection circuit shown in FIG. FIG. 3 is a diagram showing an example of a circuit for taking measures against noise by using a noise detection signal obtained from the circuit shown in FIG. FIG. 4 is a diagram showing another example of a circuit for taking measures against noise by using a noise detection signal obtained from the circuit shown in FIG. FIG. 5 is a diagram showing still another example of a circuit that takes measures against noise by using a noise detection signal obtained from the circuit shown in FIG. FIG. 6 is a diagram showing a conventional noise countermeasure circuit. FIG. 7 is a waveform diagram of signals at various parts of the circuit of FIG. In the figure, 8 is an ATD circuit, D1 and D2 are delay circuits, and I1.
~ I12 is an inverter, T1 and T2 are transfer gates, T3 is a gate transistor, A1 to A4 are NAND gates, N1
~ N5 is a NOR gate, and P1, P2, R1 and R2 are transistors forming an output buffer.

Claims (1)

[Claims] 1. A pulse generating means for generating a pulse having a constant polarity in response to a change in the level of an input address signal, a delay means for delaying the input address signal, and an address signal delayed by the delay means. By combining the logic with the original input address signal, a binary signal indicating a normal level change of the input address signal with a pulse of a first logic value and a level change due to noise with a pulse of a second logic value. Based on the pulse generated by the pulse generating means, a pulse of a portion corresponding to the noise of the input address signal from the binary signal generated by the binary signal generating means is generated. A noise detection circuit for address signals, which is provided with a means for extracting.