JPH05243147A - Formation of low-dislocation density region on compound semiconductor layer formed on silicon substrate - Google Patents

Abstract

PURPOSE:To provide a method of forming a low-dislocation density region on a GaAs layer grown on a silicon substrate. CONSTITUTION:A GaAs layer is grown on a silicon substrate 11 to a thickness of 3mum by an MOCVD method. Then, this sample is taken out from an MOCVD device and an SiO2 film is formed on the layer 13 to a thickness of 300nm by a CVD method. Then, this SiO2 film is patterned into a prescribed form by a photolithography method and a wet etching method and an SiO2 film 15a is partially made to remain on the layer 13. Then, a heat cycle, in which the state at the time when the substrate temperature is made to rise to 900 deg.C in an atmosphere of hydrogen and AsH3 is held for three minutes and thereafter, a heating device is turned on and when the substrate temperature is made to drop to 600 deg.C, the heating device is again driven and the sample temperature is made to rise to 900 deg.C, is executed three cycles.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a low dislocation density region in a compound semiconductor layer formed on a silicon substrate.

[0002]

2. Description of the Related Art If a compound semiconductor layer can be grown on a silicon substrate, not only a large-area compound semiconductor substrate which has never been obtained can be obtained, but also the characteristics of silicon and the characteristics of the compound semiconductor are utilized. Realization of useful semiconductor devices can be expected.

However, on a silicon substrate, for example, GaAs
When the layer is grown, since silicon and GaAs have different thermal expansion coefficients, when the sample is returned from the growth temperature to room temperature, a strong tensile stress is applied to the GaAs growth layer. Therefore, if the GaAs growth layer is made too thick (3
When the thickness is about 4 μm or more) cracks occur in the growth layer.

The above-mentioned tensile stress is obtained from the literature 1 (Japanese Journal of Applied Physics (Ja
panese Journal of Applied
Physics), Vol. 27, No. 10 (198
According to 8.10)), dislocations in the growth layer do not move and new dislocations do not occur in the growth layer during the cooling process of the sample after the growth of the GaAs layer, regardless of the growth temperature of the GaAs layer. It is said to occur due to the difference in the coefficient of thermal expansion of silicon-GaAs between the temperature around 350 ° C. and room temperature. At temperatures above about 350 ° C., dislocations move or new dislocations are generated in the growth layer in order to relieve stress.

Therefore, no matter how dislocations are reduced in the growth layer at the growth temperature, the dislocations are generated as described above in the subsequent cooling process, so that the quality of the growth layer is deteriorated.

Therefore, as a method for reducing the dislocation density in the GaAs layer, the following methods (I) and (II) are conventionally used.
The above method and a method combining these methods have been disclosed.

(I) A method of repeating annealing of a grown layer at a temperature of about 900 ° C. (for example, Reference 2: Applied
Physics Letters (Appl.Phys.Let
t), 51, p. 130 (1987)).

(II) InGaAs on a silicon substrate
After growing a strained superlattice using / GaAs or the like, a GaAs layer is grown on the strained superlattice (for example, Document 3; App.
l. Phys. Lett. ), 46, p. 294 (19
85).

[0009]

However, in any of the conventional growth methods, the dislocation density of the GaAs growth layer is 10 or less.
^Since it is very difficult to reduce the dislocation density to ⁶ / cm ² or less, a method for growing a GaAs layer that can further reduce the dislocation density has been desired. On the other hand, GaAs grown on a silicon substrate
When a semiconductor element is formed in the growth layer, it is preferable that the dislocation density has a desired value in the entire region of this GaAs growth layer, but even if a low dislocation density region is partially formed, its utility value is high. Is considered to be sufficient.

The present invention has been made in view of the above points, and therefore an object of the present invention is to provide a method capable of forming a low dislocation density region in a partial region of a compound semiconductor layer formed on a silicon substrate. Especially.

[0011]

In order to achieve this object, a method for forming a low dislocation density region of a compound semiconductor layer formed on a silicon substrate according to the present invention (hereinafter abbreviated as "low dislocation density region forming method"). According to the above method, a step of partially forming another substance having a thermal expansion coefficient different from that of the compound semiconductor layer on the compound semiconductor layer formed on the silicon substrate, and the above-mentioned other substance. And a step of subjecting the silicon substrate on which the compound semiconductor layer has been formed to a thermal cycle treatment at two or more temperatures including at least a temperature at which dislocation migration may occur in the compound semiconductor layer.

Here, the temperature of the heat cycle treatment and the number of heat cycle treatments may be set to appropriate values according to the material of the compound semiconductor layer, the film thickness and area of the layer, and the like.

The substance formed on the compound semiconductor layer may be basically any substance as long as it has a thermal expansion coefficient different from that of the compound semiconductor layer. However, a substance that is chemically stable with respect to the compound semiconductor layer and is easily patterned into an arbitrary shape is preferable.

Further, the method of arranging the material having a different thermal expansion coefficient from that of the compound semiconductor layer partially on the compound semiconductor layer may be determined according to the design. In the following examples, SiO ₂ is formed on the GaAs layer and the cross-cut is S
An example in which it is formed to be an iO ₂ film and an example in which the line portion of the cross-cut is a SiO ₂ film are shown.

[0015]

According to the structure of the present invention, since another substance having a different thermal expansion coefficient from the layer is partially formed on the compound semiconductor layer, this sample is subjected to the thermal cycle treatment according to the present invention. Then, excessive stress acts on the boundary portion between the portion where the other substance is formed and the portion where the other substance is not formed in the compound semiconductor layer. Further, in this thermal cycle treatment, dislocations move in the compound semiconductor layer in order to relax the stress in the compound semiconductor layer, but the dislocations do not move uniformly in the compound semiconductor layer, but move to the boundary portion. Move to focus. As a result, a region having a low dislocation density is formed in a portion of the compound semiconductor layer.

[0016]

Embodiments of the method for forming a low dislocation density region of the present invention will be described below with reference to the drawings. The materials used and numerical conditions such as time, temperature, and film thickness described in the following description are only suitable examples within the scope of the present invention.
Therefore, it should be understood that the present invention is not limited to only these conditions. In the following examples, the compound semiconductor layer is a GaAs layer, and another substance partially formed on the GaAs layer and having a thermal expansion coefficient different from that of the GaAs layer is SiO _2. Is.

1 (A) to 1 (C) are process diagrams for explaining this embodiment. In all of the figures, the sample is shown by a cross-sectional view taken along the thickness direction of the silicon substrate 11. Further, FIG. 2 is a plan view showing the sample shown in FIG. 1C as viewed from above. However, in each of the drawings, the dimensions, shapes, and arrangement relationships of the respective constituent components are schematically shown so that the present invention can be understood.

First, the GaAs layer 1 is formed on the silicon substrate 11.
3 is grown (FIG. 1 (A)). In the method of forming a low dislocation density region of the present invention, the method of forming the compound semiconductor layer is not specified, so that GaAs can be grown by various conventionally known methods. In this example, the GaAs layer 13 was grown by the so-called two-step growth method as described below.

First, the diameter is 2 inches (1 inch is about 2.5).
4 cm. ) The silicon substrate 11 (hereinafter, may be simply referred to as the substrate 11) is placed in the reaction tube of the MOCVD apparatus.

Next, in order to clean the silicon substrate 11, AsH ₃ (arsine: 100
%) At a flow rate of 20 SCCM while heating the silicon substrate at a temperature of 950 ° C. for 5 minutes. Next, the output of the heating device is set to zero and the substrate is naturally cooled until the temperature of the substrate reaches 400 ° C.

Next, while raising the substrate temperature to 700 ° C. and maintaining this temperature, AsH ₃ and TMG are placed in the reaction tube.
(Trimethylgallium) and AsH ₃ flow rate of 20S
The CCM and TMG are supplied for a predetermined time under the condition that the flow rate is 3.2 SCCM. As a result, the non-doped GaAs layer 13 having a thickness of 3 μm is formed on the substrate 11 (see FIG. 1).
(A)). The temperature of the TMG cylinder at this time is -4.
It is maintained at 4 ° C.

If necessary, a buffer layer (not shown) may be first grown on the substrate 11 and then the GaAs layer 13 may be grown on this buffer layer. When forming the buffer layer, after the above-mentioned cleaning of the substrate 11, while maintaining the substrate temperature at 400 ° C., AsH ₃ and TMG are introduced into the reaction tube, and the flow rate of AsH ₃ is changed to 20 SCC.
The flow rate of M and TMG may be set to 3.2 SCCM for 2 minutes.

Next, in this embodiment, the state where the substrate temperature was 900 ° C. was maintained for 3 minutes while hydrogen and AsH ₃ were introduced into the reaction tube, and then the heating device was turned off to bring the substrate temperature to 6 ° C.
When the temperature reaches 00 ° C., the heating device is driven again to bring the sample temperature to 900 ° C., and three thermal cycles (hereinafter, referred to as “growth layer independent thermal cycle treatment”) are performed. This is to reduce the dislocation density in this layer to some extent even in the state of only the GaAs layer 13. The effects of the present invention can of course be obtained without performing the thermal cycle treatment for the growth layer alone.

Next, after cooling the sample, the sample on which the GaAs layer 13 is formed is taken out from the reaction tube. And this GaA
In order to partially form the SiO ₂ film on the s layer 13, the SiO ₂ film 15 is first formed on the entire surface of the GaAs layer 13 (FIG. 1B). The method of forming this SiO ₂ film is not particularly limited, and various conventionally known methods may be used. In this embodiment, the CVD method is used. The thickness of the SiO ₂ film is about 300 nm in this embodiment.

Next, by a well-known photolithography to form a resist pattern (not shown) such as a resist remains on the eye portion of the cross-cut on the SiO ₂ film 15. After that, using this resist pattern as a mask, HF
The SiO ₂ film 15 is selectively etched with an aqueous solution of (hydrofluoric acid) to form a substantially square SiO film 1 on the GaAs layer 13.
Many 5a are left in a matrix (FIG. 1C, FIG. 2). In this embodiment, one side a (see FIG. 2) of the SiO ₂ film 15a is 40 μm, and the exposed width b (see FIG. 2) of the GaAs layer 13 is 20 μm.

Next, in this way, the SiO ₂ film 15 is partially
The sample in which a is left is subjected to thermal cycle treatment at two or more temperatures including at least one temperature at which dislocation movement and / or new dislocation generation may occur in the GaAs layer 13. In this example, this thermal cycle is
The sample is put in the reaction tube of the MOCVD apparatus, and the same thermal cycle treatment as for the growth layer is performed under the same conditions.

In this thermal cycle treatment, dislocations in the GaAs layer 13 move due to the stress in the GaAs layer 13, but stress is applied to the boundary between the portion of the GaAs layer 13 where the SiO ₂ film 15a is provided and the portion where it is not provided. Therefore, the dislocations move so as to concentrate on the boundary portion so as to relieve the stress at the boundary portion. As a result,
A region having a low dislocation density can be formed in the portion of the GaAs layer 13 where the SiO ₂ film 15a is not provided. Note that SiO ₂
The film 15a may be removed or may remain depending on how the GaAs layer 13 is used thereafter.

Next, in this embodiment, in order to confirm that a low dislocation density region is formed, the GaAs layer 13 of the sample which has been subjected to the series of treatments as described above is etched by a predetermined amount with molten KOH and etched. A pit was made to appear and the surface of this sample was observed with an optical microscope. Note that SiO ₂
The film 15a is removed during etching of the GaAs layer 13 with molten KOH.

FIG. 3 is a copy of a photograph of a part of the surface of the sample under observation with an optical microscope. The photographed area of the sample is the portion indicated by P in FIG. The etch pits 21 correspond to dislocations. As is clear from FIG. 3, dislocations are concentrated at the boundary between the portion 13x of the GaAs layer 13 where the SiO ₂ film 15a is provided and the portion 13y where it is not provided (the portion indicated by the one-dot chain line in FIG. 3). It can be seen that the dislocation density is low in the GaAs layer portion 13y where the SiO ₂ film is not provided.

Separately from the example, the same experiment as the above example was performed except that when the SiO ₂ film was left on the GaAs layer 13, the arrangement of the SiO ₂ film was reversed from that shown in FIG. Was done. That is, in FIG. 2, the squares of the grid are made of SiO ₂ film, while the lines of the grid are made of Si.
An experiment similar to that of the example was performed with the O ₂ film left. Also in this case, dislocations are caused in the GaAs layer 1 as in the above embodiment.
No. 3 SiO ₂ film 15a is provided at the boundary between the part where the SiO ₂ film is provided and the part where the SiO ₂ film is not provided, and dislocations occur in the GaAs layer part where the SiO ₂ film is not provided (in this case, each square area) It was found that the density was low.

Although the embodiment of the method for forming a low dislocation density region of the present invention has been described above, the present invention is not limited to the above-described embodiment but can be modified as described below.

For example, in the above-mentioned embodiment, the other material partially formed on the GaAs layer is the SiO ₂ film, but this material may be another suitable material as long as it has a different GaAs thermal expansion coefficient. For example, a silicon nitride film or the like may be used.

Further, in the above-mentioned embodiment, the example of forming the low dislocation density region in the GaAs layer formed on the silicon substrate has been described. However, the present invention forms the low dislocation density region in the compound semiconductor layer other than the GaAs layer. It can also be applied when forming.

[0034]

As is apparent from the above description, according to the method of forming a low dislocation density region of the present invention, dislocations are concentrated in a specific portion of the compound semiconductor layer, and thus the region of low dislocation density is formed in other portions. Can be formed. For this reason, for example, G having a region where the dislocation density is low at a practical level on a silicon substrate.
An aAs layer can be formed.

[Brief description of drawings]

FIG. 1A to FIG. 1C are process drawings provided for explaining an example.

FIG. 2 Si on a GaAs layer formed on a silicon substrate
FIG. 6 is a plan view showing a state where an O ₂ film is partially formed.

FIG. 3 is a copy of a photograph obtained by etching a sample with molten KOH and observing a part thereof with an optical microscope.

[Explanation of symbols]

11: Silicon substrate 13: GaAs layer 13x: part had been provided an SiO ₂ film of the GaAs layer 13y: portion not provided with the SiO ₂ film of the GaAs layer 15: SiO ₂ film 15a: partially provided on the GaAs layer SiO ₂ film 21: Etch pit

Claims (1)

[Claims] 1. A step of partially forming, on a compound semiconductor layer formed on a silicon substrate, another substance having a coefficient of thermal expansion different from that of the compound semiconductor layer, and forming the other substance and the compound semiconductor layer. A step of performing a thermal cycle treatment on the completed silicon substrate at two or more temperatures including at least a temperature at which dislocation migration may occur in the compound semiconductor layer. Method for forming low dislocation density region of compound semiconductor layer.