JPH07263454A - Forming method of wafer having low dislocation - Google Patents

Abstract

PURPOSE:To provide a method for forming a GaAs layer having low dislocation on an Si wafer. CONSTITUTION:After a GaAs layer 12 is formed on a wafer 10, an insulating film 14 whose thermal expansion coefficient is smaller than that of the GaAs layer is formed on the Gage layer. The insulating film is partly etched and eliminated, and a mask layer is formed by forming holes 15 in the insulating film. This formed structure body is annealed by at least one time heat cycle treatment in the temperature range, D from 400 deg.C to 950 deg.C. After that, at least a new second GaAs layer is formed on a semiconductor layer.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a wafer having low dislocations, and more particularly to a method for forming a wafer on a silicon (Si) wafer.
The present invention relates to a method for forming a wafer having low dislocations, in which IV group semiconductor layers are stacked.

[0002]

2. Description of the Related Art In recent years, a new functional device in which a high quality III-V group semiconductor layer (for example, GaAs layer) is grown on a silicon (Si) wafer has attracted attention. This functional device can be constructed by taking advantage of the characteristics of silicon and GaAs. However, reference I (“The Influence of Growth”
h Temperature and Thermal
Annealing on the Stress i
n GaAs Layers Grownon Si
Substates ", T.W. Ueda, at a
l, Japanese Journal of Appl
ied Physics, Vol. 27, No. 10,
(1988), PP. 1815-1818), since silicon and GaAs materials have different thermal expansion coefficients, GaA on a silicon wafer is
When the s layer is formed, many dislocations occur at the interface between GaAs and silicon or in the GaAs layer. This dislocation is
It occurs when a GaAs layer is epitaxially grown on a silicon wafer at a predetermined temperature and then cooled to room temperature. For example, in the case of growing a GaAs layer on a silicon wafer, the dislocation density generated in the GaAs layer at the growth temperature was on the order of 1 × 10 ⁴ (cm ⁻² ), but was 1 during the cooling process. It is disclosed in Document II that the number increases to the order of × 10 ⁶ (cm ⁻² ) (see Document II: “Dislocation gen”).
association of GaAs on Si in
"the cooling stage", Appl, Ph
ys, Lett, 56, (22), P2225, (19
90)).

Therefore, GaAs / Si is used as a functional device.
When a wafer is used, a method of reducing the dislocation density in the GaAs layer is inevitably necessary. Therefore, conventionally, methods such as those disclosed in Documents III and IV have been proposed (Document III: "Defect str").
structures at the GaAs / Si in
interface after annealing ”,
Appl, Phys, Lett, 51, No. 2, P1
30, (1987), Reference IV: "Defect re.
reduction in GaAs epitaxy
layering a GaAsP-InGaP
trained layer superlatti
ce ”, Appl, Phys, Lett, Vol. Four
6, No. 3, P294, (1985)).

First, in Document III, a method of repeating annealing at a heating temperature of about 900 ° C. for a GaAs layer grown on a Si substrate is proposed, and in Document IV, GaAsP / InGaP or the like on a Si substrate is proposed. Has been proposed, and then a GaAs layer is grown on this strained superlattice.

[0005]

However, in any of the methods disclosed in the above-mentioned conventional literatures III and IV, the GaA formed on the Si wafer is used.
It was difficult to set the dislocation density in the s layer to 1 × 10 ⁶ (cm ⁻² ) or less. GaAs formed on Si wafer
If a large number of dislocations are generated therein and the dislocation density increases, the device characteristics (for example, output) will be adversely affected.

Therefore, a method for forming a III-IV group semiconductor layer having a low dislocation on a silicon wafer has been desired.

[0007]

Therefore, according to the present invention, after the III-IV group semiconductor layer is formed on the Si wafer, the thermal expansion coefficient of the semiconductor layer is higher than that of the semiconductor layer on the semiconductor layer. An insulating film having a small expansion coefficient is formed. afterwards,
The insulating film is partially removed by etching, a hole is formed in the insulating film, and a mask layer is formed.

Subsequently, a structure having a mask layer is formed into 400
A thermal cycle treatment is performed at least once in the temperature range of 950 ° C. to 950 ° C., annealing is performed, and then at least one III-V group second semiconductor layer is formed on the semiconductor layer.

[0009]

The present invention described above has III-
After forming the V-group semiconductor layer, an insulating film having a thermal expansion coefficient smaller than that of the semiconductor layer is formed on the semiconductor layer. Therefore, the tensile stress between the Si wafer and the semiconductor layer is adjusted due to the difference in thermal expansion coefficient between the insulating film and the semiconductor layer. Then, the insulating film is partially removed by etching to form a mask layer, and then the above-described structure is annealed by performing a predetermined number of thermal cycles in the temperature range of 400 ° C. to 950 ° C. At this time, 400
From the temperature of ° C, dislocations become easy to move and silicon (S
i) Due to the interaction of the tensile stress between the wafer, the semiconductor layer, and the mask layer, dislocations in the semiconductor layer are concentrated on the end face and the side peripheral portion of the mask layer in contact with the semiconductor layer. Further, the upper limit value of 950 ° C. is set because workability (reduction of time) during manufacturing is good. At this time, dislocations in the semiconductor layer not covered with the mask layer are reduced (details will be described later).

Then, at least one new second semiconductor layer is formed on the semiconductor layer in which dislocations are less likely to occur. This second semiconductor layer uses a material having a thermal expansion coefficient substantially the same as that of the semiconductor layer. A second semiconductor layer with less strain can be formed on the semiconductor layer. Therefore, a semiconductor layer having a low dislocation and a second semiconductor layer can be formed on the Si wafer.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A method for forming a wafer having low dislocations according to the present invention will be described below with reference to the drawings. In addition, each figure is, to the extent that the present invention can be understood, the shape of each component,
The size and arrangement are only shown schematically. The embodiments described below are merely preferred examples, and the present invention is not limited to these embodiments.

1A to 1C, 2 and 3,
6A to 6C are process diagrams and heat treatment explanatory diagrams for explaining a forming method according to an embodiment of the present invention. In the explanatory view of the heat treatment in FIG. 3, the horizontal axis represents time and the vertical axis represents temperature.

First, in order to remove the oxide film and impurities on the upper surface of the silicon (Si) wafer, the Si wafer is preliminarily heat-treated at about 900 ° C. (period (I) in FIG. 3). After that, the III-V group semiconductor layer 12 is formed on the Si wafer. As the semiconductor layer 12, for example, Ga
An As layer is used. At this time, as a method for forming the GaAs layer 12, MOCVD (Metal Organic) is used.
-Chemical Vapor Deposition
n) method, arsenic trichloride (AsCl ₃ ) and gallium (Ga) are supplied into the furnace to form the GaAs layer 12 on the Si wafer at a heating temperature of, for example, 650 ° C. (FIG. 1).
(A) and period (II) of FIG. 3). At this time, GaA
The thickness of the s layer 12 is preferably about 3 μm.

Next, the GaAs layer 12 is formed on the Si wafer 10.
After naturally cooling or forcibly cooling the structure formed by forming the structure, the structure is transferred to another furnace and an insulating film 14 having a thermal expansion coefficient smaller than that of the GaAs layer 12 is formed on the GaAs layer 12. ((B) of FIG. 1). This insulating film 1
4, a silicon oxide (SiO ₂ ) film is used in this embodiment. As a method of forming the SiO ₂ film 14, for example, the CVD method is used to form the SiO ₂ film 14 on the GaAs layer 12 under the following preferable conditions.

Conditions for forming SiO ₂ film Gas composition: monosilane (SiH ₄ ) + oxygen (O ₂ ) Gas pressure of low pressure CVD: 2-3 Torr Furnace temperature: about 300 ° C. At this time, film thickness of SiO ₂ film 14 To about 3000Å. The thermal expansion coefficient of the SiO ₂ film 14 formed at this time is 5 × 10 ⁻⁷ , whereas the GaAs layer 12 is
Has a thermal expansion coefficient of 6.86 × 10 ⁻⁶ .

Next, using the photolithography method,
After forming a resist pattern on the SiO ₂ film 14 (not shown), the sample is dipped in a hydrogen fluoride (HF) solution to form Si.
The O ₂ film 14 is etched. After that, the resist pattern is removed using an acetone solution to make a hole in the SiO ₂ film to form a mask layer ((C) of FIG. 1). This Figure 1
(C) of (i) is a plan view, and (ii) is a sectional view taken along line ii of (i). At this time, the shape of the SiO ₂ film 14 may be formed such that a plurality of holes 15 are partially provided ((C) of FIG. 1), or as shown in (A) and (B) of FIG. Alternatively, a stralip-shaped hole 13 may be provided. In addition, in FIG. 1C, a schematic plan view is shown in the upper part, and a main part cross-sectional view taken along a horizontal line with respect to the center of the window 15 is shown in the lower part. In addition, FIGS. 4A and 4B show stripe-shaped SiO ₂ on the GaAs layer 12.
An example in which the film 14 is formed is shown. At this time, any of the SiO _{2 of} FIG. 1 (C) and FIG. 4 (A) and (B)
Also present in the SiO ₂ film 14 into the shape of the membrane area and the SiO ₂
Regions where no film is present are formed. As a material for the mask layer, a silicon nitride film may be used instead of the SiO ₂ film.

Next, the structure of FIG.
Using a heating furnace similar to that used in method D, annealing is performed by performing thermal cycle treatment at least once in the temperature range of 400 ° C to 950 ° C. In this example, the thermal cycle processing temperature was as follows. That is, 90
Set to 0 ° C and set low temperature to 600 ° C. Then, a mixed gas of hydrogen (H ₂ ) gas and arsine (AsH ₃ ) gas is supplied into the furnace to increase the heating temperature from 900 ° C. to 60 ° C.
The heat cycle treatment at 0 ° C. was repeated 3 times. At this time, the holding time at 900 ° C. is preferably about 3 minutes (period (III) in FIG. 3). At this time, GaAs
The dislocations in the layer 12 start to move from the temperature of 400 ° C., and the stress due to the tensile stress between the SiO ₂ film and the GaAs layer is adjusted as the temperature rises. At this time, the stress can be almost adjusted by treating the structure at a heating temperature of 900 ° C. for 3 minutes. In this example, by performing the thermal cycle treatment three times, the dislocations could be completely concentrated on the side edge surface of the SiO ₂ film 14 in contact with the GaAs layer 12.

Further, by performing this thermal cycle treatment, as described above, the GaAs layer 12 and the SiO ₂ film 14 are formed.
For thermal expansion coefficients are different, the boundary region 1 between nonexistent part of the portion and the SiO ₂ film 14 in the presence of SiO ₂ film 14
Large stress is concentrated on 7. Then, due to this stress, dislocations generated or moved in the GaAs layer 12 are concentrated in the boundary region 17. This is shown in FIGS. 5A to 5C. In addition, for the observation of the etch pit of FIG.
The results of observing the etch pits with an optical microscope after etching the sample with a potassium hydroxide (KOH) solution are shown in FIG. 5 (C). In addition, FIG.
In (C), hatching showing a cross section is partially removed to facilitate understanding of the drawing.

In FIG. 5A, Ga is formed on the Si wafer 10.
The generation state of dislocations 18 at the stage of forming the As layer 12 is shown. Here, the SiO ₂ film 14 will be described by taking the striped pattern shown in FIG. 4 as an example.

As can be understood from FIG. 5A, many dislocations 18 are generated along the upper surface of the GaAs layer 12 from the interface direction between the Si wafer 10 and the GaAs layer 12.

Next, FIGS. 5B and 5C show the state of dislocations when the thermal cycle process is performed after the SiO ₂ film 14 is formed on the GaAs layer 12.

As can be understood from FIGS. 5B and 5C, the dislocations 20 after the thermal cycle are GaAs.
It is concentrated on the boundary region 17 of the stripe-shaped SiO ₂ film 14 that is joined to the layer 12. Also, FIG. 5 (C)
As it can be understood from the plan view of, in the region a where the SiO ₂ film is not present, almost the etch pit 22, while not occur in a region b where the SiO ₂ film is present, the etch pits 22 are SiO ₂ A large number of etch pits 22 are formed in the region b where the SiO ₂ film 14 is present, which are generated in large numbers along the side edge surface of the film 14. The reason for this is considered as follows.

By performing the thermal cycle treatment, Ga
Since the As layer 12 and the SiO ₂ film 14 have different thermal expansion coefficients, stress is applied to the boundary region 17 of the SiO ₂ film 14 in contact with the GaAs layer 12, and this stress causes dislocations in the GaAs layer 12. It is presumed that dislocations are concentrated in the boundary region 17 of the SiO ₂ film 14 which is in contact with the GaAs layer 12 because it is generated or moved. Also,
Since the SiO ₂ film 14 is provided on the GaAs layer 12, the tensile stress between the Si wafer 10 and the GaAs layer 12 having different thermal expansion coefficients is adjusted and relaxed. Therefore, SiO
_Since the tensile stress of the GaAs layer 12 in the region a where the ₂ film 14 does not exist is reduced, GaA where the SiO ₂ film 14 does not exist.
It is presumed that dislocations do not occur in the s layer 12.

For the above-mentioned reason, the dislocation density of the region a where the SiO ₂ film does not exist is measured by a microscope (for example, an optical microscope).
And the dislocation density was measured, the dislocation density was found to be 10
It was found to be about ⁵ (cm ^-2 ).

Next, using the MOCVD method again, trimethylgallium (TMG) and arsine (AsH) are placed in the furnace.
The mixed gas of ₃ ) is introduced together with hydrogen, and any suitable heat treatment is performed to form a new III-V group second semiconductor layer 16 on the SiO ₂ film 14 (FIG. 2). At this time,
The second semiconductor layer 16 formed on the SiO ₂ film 14 is a second GaAs layer. The thickness of the second GaAs layer 16 is S
The thickness may be about 3000Å, which is the same as that of the iO ₂ film, or may be an arbitrary film thickness according to the design value. At this time, on the SiO ₂ film 14 is not deposited a second GaAs layer 16, only a nonexistent region a of the SiO ₂ film 14, the second GaAs layer 16 is formed, a so-called selective growth occurs. Therefore, Ga having a dislocation density of about 10 ⁵ cm ^-2
The second GaAs layer 16 formed on the region of the As layer 12 (region without the SiO ₂ film) can obtain the second GaAs layer 16 having a smaller dislocation density.

By forming a device element on the wafer having low dislocations formed in the above-described embodiment and then dicing and using it, a functional device having excellent electric characteristics can be formed.

Further, in the embodiment of the present invention, the film thickness of the SiO ₂ film 14 is set to about 3000 Å, but it is not limited to this value at all, and the pattern shape of the SiO ₂ film 14 or the GaAs layer 12 is not limited. It may be arbitrarily changed depending on the film thickness.

Further, in this embodiment, the semiconductor layer 12 has a G
Although an example in which a compound material of GaAs is used for the aAs and the second semiconductor layer 16 has been described, the material is not limited to this material, and for example, a combination of a semiconductor and a second semiconductor layer may be GaP / GaP, GaSb. / Ga
It may be Sb, InP / InP, or the like.

[0029]

As is apparent from the above description, according to the method for forming a wafer having low dislocations according to the present invention, the boundary portion of the side edge surface or the edge surface of the hole of the mask layer contacting the semiconductor layer. Since dislocations can be concentrated and formed in the semiconductor layer, the dislocation density in the semiconductor layer where the mask layer does not exist becomes small. Therefore, the dislocation density of the second semiconductor layer can be further reduced by forming a new second semiconductor layer in the portion of the semiconductor layer having few dislocations. Therefore, by using a wafer with low dislocations,
A device having excellent electrical characteristics can be formed.

[Brief description of drawings]

1 (A) to 1 (C) are process drawings provided for explaining an embodiment of the present invention.

FIG. 2 is a process chart provided for explaining a post process of FIG.

FIG. 3 is an explanatory diagram provided for explaining a heat treatment of the present invention.

4A and 4B are a schematic plan view and a cross-sectional view provided for explaining dislocations generated in a boundary region of a stripe-shaped SiO ₂ film.

5A to 5C are a cross-sectional view and a plan view for explaining a dislocation generation state at each manufacturing process step.

[Explanation of symbols]

10: Si wafer 12: GaAs layer 14: SiO ₂ film 13, 15: Hole 16: Second GaAs layer 17: Boundary region 18, 20: Dislocation 22: Etch pit

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Taka Aotake 1-7-12 Toranomon, Minato-ku, Tokyo Oki Electric Industry Co., Ltd.

Claims (4)

[Claims] 1. When forming a III-V group semiconductor layer on a Si wafer and then performing an annealing treatment to form a wafer having low dislocations, (a) on the semiconductor layer,
Forming an insulating film having a coefficient of thermal expansion smaller than that of the semiconductor layer; and (b) partially removing the insulating film by etching to form a hole in the insulating film to form a mask layer. And (c) a step of annealing the structure formed in the step (b) at least once in a temperature range of 400 ° C. to 950 ° C. for annealing, and (d) on the semiconductor layer, And a step of forming at least one new III-V group second semiconductor layer. 2. The method for forming a wafer having low dislocations according to claim 1, wherein the material of the semiconductor layer is gallium arsenide (GaAs), gallium phosphide (GaP), gallium antimony (GaS).
b) and a method of forming a wafer having low dislocations, which is one kind of compound selected from the group of indium phosphide (InP). 3. The method for forming a wafer having low dislocations according to claim 1, wherein the material of the second semiconductor layer is gallium arsenide (GaA).
s), gallium phosphide (GaP), gallium antimony (GaSb), and one kind of compound selected from the group of indium phosphide (InP), and a method for forming a wafer having low dislocations. 4. The method for forming a wafer having low dislocations according to claim 1, wherein the material of the insulating film is silicon oxide (SiO ₂ ) or silicon nitride (SiN _x ). Method of forming a wafer having dislocations.