JP3089732B2 - Method for epitaxial growth of compound semiconductor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for selectively epitaxially growing a group III-V compound semiconductor as a heterogeneous material on a silicon substrate. As a compound semiconductor grown on a silicon substrate, for example, GaAs, Ga
Binary III-V compound semiconductors such as P and InP, Al
GaAs, AlGaP, InAlAs, InAlP, G
A ternary group III-V compound semiconductor such as aAsP or GaInP, or a mixture of these compound semiconductors can be used.

[0002]

2. Description of the Related Art Conventionally, a technique for growing a compound semiconductor such as GaAs on a silicon substrate (hereinafter referred to as a heteroepitaxial growth technique) includes a method of thermally cleaning a silicon substrate at a high temperature of about 1000.degree.
A low-temperature GaAs buffer layer of about several tens of nm is grown at a low temperature of about ℃, and the growth temperature is raised again to a normal GaAs growth temperature (600 to 800 ° C.) to epitaxially grow the GaAs layer. This method is generally called a two-stage growth method. There has also been proposed a method of epitaxially growing a GaAs layer on a silicon substrate via a superlattice buffer layer. However, both growth methods
At present, a fundamental technical solution to the generation of crystal defects based on a lattice mismatch and a large difference in thermal expansion coefficients, which are fundamental problems of a GaAs growth technique on a silicon substrate, has not yet been obtained.

Recently, Japanese Unexamined Patent Publication No. 63-182811, and American
Vacuum Society 1988 "J.Vac.Sci.Technol.B6
(2), Mar / Apr 1988 "and the like have proposed a technique in which ap ⁺ type silicon substrate is anodized to make it porous, and then heteroepitaxially grown thereon. A micro hole having a diameter of about several nm is formed in a part of the silicon substrate surface having a thickness of several μm, and GaAs is grown so as to bridge the micro hole. % Difference).

FIGS. 2 and 3 are cross-sectional views of a GaAs layer formed on a porous silicon substrate by a conventional heteroepitaxial growth method. Specifically, a p ⁺ type silicon substrate is immersed in an etchant composed of hydrofluoric acid / ethanol / water, and the surface layer of the silicon substrate is deepened by constant current electrolysis using the silicon substrate as an anode and the platinum electrode as a cathode. About 10μm
Until porous. The substrate is put into an MBE furnace or an OMVPE furnace to grow GaAs epitaxially (FIG. 2). In some cases, after a thin (about 50 nm) silicon epitaxial layer is formed on the porous layer, the GaAs layer is epitaxially grown. However, even with this heteroepitaxial growth technique, crystal defects have not yet been completely eliminated, and a phenomenon in which a GaAs layer enters into the micropores of the porous layer has been observed, and crystal defects called micro twins and stacking faults have been observed. The problem is that a large number of problems occur.

[0005]

SUMMARY OF THE INVENTION Accordingly, the present invention has been made to solve the above-mentioned problems and has substantially reduced the occurrence of crystal defects due to lattice mismatch between silicon and III-V compound semiconductors.
An object of the present invention is to provide a heteroepitaxial growth method capable of obtaining an IV compound semiconductor epitaxial layer.

[0006]

[SUMMARY Ki for the present invention, there is provided a method of epitaxially growing a group III-V compound semiconductor layer on a silicon substrate, on p ⁺ -type silicon substrate n ^- is grown -type silicon epitaxial layer, the n ^- A Si ₃ N ₄ film is deposited on the silicon epitaxial layer, and the Si ₃ N ₄ film and the n ⁻
The p ⁺ -type silicon substrate including the patterned n ⁻ -type silicon epitaxial layer is subjected to anodization treatment to make a part of the p ⁺ -type silicon substrate porous, and then subjected to thermal oxidation treatment. To transform the porous layer into a SiO ₂ layer, and to form Si ₃ on the patterned n ⁻ -type silicon epitaxial layer.
This is a compound semiconductor epitaxial growth method characterized by removing the N ₄ film with hot phosphoric acid and thereafter epitaxially growing a group III-V compound semiconductor layer on the patterned n ⁻ -type silicon epitaxial layer.

[0007]

FIG. 1 is an explanatory view showing each step of selectively growing a GaAs epitaxial layer on a silicon substrate by the epitaxial growth method of the present invention.
(A) is a diagram in which an n ⁻ -type silicon epitaxial layer is grown to about 100 nm after performing an organic cleaning and a hydrofluoric acid etching process on a p ⁺ -type silicon substrate. This n ⁻ -type silicon epitaxial layer may have a thickness of about several hundred nm, and may be formed by MBE (molecular beam epitaxy) or VPE.
It grows by the method (gas phase epitaxial growth method). In addition,
The thickness of the n ^- type silicon epitaxial layer is 100 nm
The range of from to several hundred nm is preferable. If it is too thin, dislocations are likely to occur when the porous layer is oxidized, and if it is too thick, it will not meet the purpose of the silicon epitaxial layer of the present invention.
(B) shows that after depositing a Si ₃ N ₄ film of about 200 nm on the n ⁻ -type silicon epitaxial layer by thermal CVD (CVD: chemical vapor deposition) or plasma CVD,
FIG. 3 is a view in which a resist is applied on an i ₃ N ₄ film and a stripe pattern is formed on an n ⁻ -type silicon epitaxial layer through a photolithography process. Note that Si ₃ N
The thickness of the _four films is preferably in the range of 150 to 200 nm.
If the thickness is too small, the silicon epitaxial layer is adversely affected in the etching process.

(C) Anodizing the surface of the silicon substrate by constant current electrolysis using a silicon substrate as an anode and a platinum electrode as a cathode in an electrolytic etching solution composed of hydrofluoric acid-ethanol-water to form a p ⁺ type FIG. 3 is a diagram in which a porous layer is formed on a surface of a silicon substrate. At this time, the n ⁻ -type silicon epitaxial layer is not anodized, but retains its shape, but becomes porous from the surface of the p ⁺ -type silicon substrate that comes into contact with the etching solution, and extends not only in the depth direction but also in the lateral direction. Porosity progresses, and a porous layer is formed leaving an n ⁻ -type silicon epitaxial layer as shown in the figure. (D) is a view in which the silicon substrate is put into a thermal oxidation furnace, and only the porous surface layer is oxidized to form porous SiO ₂ . Since the oxidation rate of porous silicon is 100 times or more faster than that of bulk silicon, only the porous layer is made of SiO 2.
Transformed to ₂ . (E) is the Si ₃ N ₄ film is etched in hot phosphoric acid, n patterned on SiO ₂ made porous ^- diagrams exposed type silicon epitaxial layer. (F) Using this substrate, GaAs is selectively formed on the n ⁺ -type silicon epitaxial layer in a low-pressure OMVPE furnace.
It is the figure which made the s layer grow epitaxially.

By adopting the present invention as described above,
In heteroepitaxial growth of a III-V compound semiconductor layer such as GaAs on a silicon substrate, selective growth of a high-quality epitaxial layer with few crystal defects has been enabled.
In the conventional GaAs heteroepitaxial growth method on a silicon substrate, the thickness of the GaAs layer is several μm at most and 1/100 or less of the thickness of the silicon substrate of several hundred μm, so that only crystal defects based on lattice mismatch are generated. Instead, lattice distortion was caused due to the difference in thermal expansion coefficient, and many crystal defects called micro twins and stacking faults were generated.

In the present invention, since the porous layer formed on the surface of the substrate is denatured into SiO ₂ , a cushioning effect works to reduce lattice distortion caused by a difference in thermal expansion coefficient between the silicon substrate and the GaAs layer. Can be eliminated, and Ga
Since the portion where As grows has a thin silicon epitaxial layer of about several hundred nm, the GaAs layer is about 100 times thicker in thickness than the above case. Lattice strain can be absorbed not on the GaAs layer side but on the silicon epitaxial layer side. As a result, generation of crystal defects can be effectively suppressed in the GaAs epitaxial layer. As described above, the epitaxial growth of the GaAs layer has been described as an example, but a high-quality epitaxial layer can be similarly grown for other group III-V compound semiconductors.

[0011]

The present invention will be described in more detail with reference to the following examples. (1) A p ⁺ silicon substrate having a specific resistance of 0.01 Ωcm or less was subjected to organic cleaning and hydrofluoric acid etching. (2) An n ⁻ -type silicon epitaxial layer was grown to a thickness of about 900 nm by a silicon MBE method. The growth temperature was 800 ° C. (3) Next, the substrate having the n ⁻ -type silicon epitaxial layer was subjected to hydrofluoric acid cleaning and organic cleaning to remove surface oxides and surface contamination. (4) The substrate was placed in a thermal CVD furnace, and a mixed gas of SiH ₄ (silane) and NH ₃ (ammonia) gas was introduced into the furnace, it is thermally decomposed at a temperature of about 650 ° C., n ^-
About 200 nm of Si on the silicon epitaxial layer
_{A 3} N ₄ (silicon nitride) polycrystalline film was deposited. (5) After cooling to room temperature, organic washing is performed, and after applying a photoresist, pre-baking, photographic exposure, development,
A stripe pattern having a width of several μm was formed by a usual photolithography method including post-baking. The direction of the stripe pattern was the {110} direction. (6) In the striped window from which the resist has escaped, Si ₃
N ₄ film appeared, buffered hydrofluoric acid (liquid composition: HF:
(NH ₄ F: H ₂ O = 1: 10: 100) to remove the Si ₃ N ₄ film. (7) The remaining resist (formed in a stripe shape) was washed and removed by ultrasonic waves in an acetone solution. (8) Next, immerse in KOH (potassium hydroxide) aqueous solution,
The portion where the n ⁻ -type silicon epitaxial layer was directly exposed was selectively removed to expose the p ⁺ silicon substrate in a stripe shape. (9) Through the above steps, the shape shown in FIG. 1B was obtained.

(10) Next, using a silicon substrate prepared in a hydrofluoric acid-ethanol-water electrolytic etching solution as an anode and a platinum electrode as a cathode, the anode is applied to the surface of the silicon substrate by constant current electrolysis of about 150 mA. A chemical conversion treatment was performed. At this time, the n ⁻ -type silicon epitaxial layer is not anodized and keeps its shape, but the surface of the p ⁺ silicon substrate exposed to the etching solution is made porous by anodization (FIG. 1C). The thickness of the porous layer was about 30 μm. (11) This silicon substrate is put into a thermal oxidation furnace and oxidized at a temperature of 700 to 900 ° C. in an oxygen atmosphere,
The porous surface layer is oxidized and porous SiO
₂ was formed (FIG. 1 (d)). (12) Thereafter, when the Si ₃ N ₄ film was etched in hot phosphoric acid, the patterned n ⁻ -type silicon epitaxial layer on the porous SiO ₂ was exposed (FIG. 1).
(E)).

(13) Decompression OMVP using this substrate
In an E furnace, a growth temperature of 650 ° C., a growth pressure of 10 Torr, a total gas flow rate of 500 cc / min, and a flow rate of 10 cc / min using trimethylgallium (TMG) as a group III raw material
GaAs was grown at a flow rate of 300 cc / min using 10% arsine diluted with hydrogen as a Group V material, and the GaAs layer was selectively epitaxially grown only on the n ⁻ -type silicon epitaxial layer. (FIG. 1 (f)). The TMG raw material was placed in a thermostat at 0 ° C., and introduced into the growth reactor by bubbling hydrogen das. Purified hydrogen was added to the shortage of the total gas flow. (14) The GaAs layer has n ⁻ formed in a stripe shape.
Selectively grown on the silicon epitaxial layer. Then, evaluation of low-temperature photoluminescence and the like confirmed that the crystal was a high-quality crystal. (15) Regarding crystal defects, the cross section of the epitaxial layer was observed with a transmission electron microscope. Compared to a GaAs layer heteroepitaxially grown on a normal silicon substrate, it was found that the crystal defect density was reduced by one to two digits.

[0014]

According to the present invention, by employing the above-described structure, the present invention is very effective in greatly reducing crystal defects due to lattice mismatch between silicon of the substrate and the group III-V compound semiconductor.

[Brief description of the drawings]

FIG. 1 is an explanatory view showing each step of selectively growing a GaAs epitaxial layer on a silicon substrate by the epitaxial growth method of the present invention.

FIG. 2 is a cross-sectional view of a GaAs layer heteroepitaxially grown on a conventional porous silicon substrate.

FIG. 3 is a cross-sectional view of a GaAs layer heteroepitaxially grown on a conventional porous silicon substrate via a thin silicon epitaxial layer.

──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Yasuhiro Shiraki 3-36-9 Hirayama, Hino-shi, Tokyo (72) Inventor Koichi Komon 1-1-1, Koyokita-Kita, Itami-shi, Hyogo Sumitomo Electric Industries, Ltd. Inside the Itami Works (72) Inventor Mitsuru Shimazu 1-1-1, Koyo Kita, Itami City, Hyogo Prefecture Inside Sumitomo Electric Industries, Ltd. Itami Works (72) Inventor Hiroya Kimura 1-1-1, Koyo Kita Kita, Itami City, Hyogo Prefecture Sumitomo Electric Industries, Ltd. Itami Works (72) Inventor Shirakawa 2-1-1-1, Kunyokita, Itami-shi, Hyogo Prefecture Sumitomo Electric Industries, Ltd. Itami Works (56) References JP-A-63-182811 (JP) (A) JP-A-3-42818 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 21/20 H01L 21/205

Claims (1)

(57) [Claims] 1. A method of epitaxially growing a group III-V compound semiconductor layer on a silicon substrate, p ⁺ -type silicon substrate on the n ^- -type silicon epitaxial layer is grown, the n ^- Si on the -type silicon epitaxial layer ₃ N ₄
Depositing a film, patterning the Si ₃ N ₄ film and the n ⁻ -type silicon epitaxial layer by a photolithography method, and subjecting the p ⁺ -type silicon substrate including the patterned n ⁻ -type silicon epitaxial layer to anodizing treatment; P ⁺
A portion of the silicon substrate is made porous, and then subjected to thermal oxidation to transform the porous layer into a SiO ₂ layer. The Si ₃ N ₄ film on the patterned n ⁻ silicon epitaxial layer is heated with hot phosphoric acid. A method for epitaxially growing a compound semiconductor, comprising: removing a III-V compound semiconductor layer on the patterned n ⁻ -type silicon epitaxial layer.