JP2000012467A - Method for forming gaas layer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To more easily obtain the GaAs layer of high quality on a Si substrate by forming a GaAs intermediate layer containing the holes of Ga, which extin guish dislocation and convert the progress direction of dislocation, and forming the GaAs layer on the surface of the GaAs intermediate layer. SOLUTION: An n+-GaAs buffer layer 13 is epitaxially grown on the (100) face of a Si substrate 11, an ohmic contact layer 15 is formed on the n+-GaAs buffer layer 13 and a back surface field layer 17 is formed. Then, a GaAs intermediate layer 19 containing much holes of Ga, which extinguish dislocation or convert the progress direction of dislocation, is formed on the Si substrate 11. Consequently, a V/III ratio ([As]/[Ga]ratio) in supplied raw material gas is made higher than regular 19, to be 97, for example. Then, a GaAs layer 21 is grown by using a heat cycle method adding a heat-treatment process in the middle of the growth of crystal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a gallium arsenide (hereinafter referred to as GaAs) layer, and more particularly to a method for forming a GaAs epilayer used as a base for fabricating various optical devices and electronic devices. It is about.

[0002]

2. Description of the Related Art A GaAs layer is used as a base for manufacturing a compound semiconductor device. This foundation is
It is formed by forming a GaAs epilayer on a silicon (Si) substrate.

[0003] Single domain GaAs on a Si substrate
A GaAs-on-Si growth technique for growing an epi layer can increase the substrate area and reduce the cost. For this reason, the development of an epitaxial growth technique that can obtain a GaAs layer with higher quality has been promoted. Note that a GaAs layer having excellent quality here refers to a GaAs crystal having a low density of dislocations and lattice defects.

[0004] Many dislocations are generated at the interface between the GaAs layer and the Si substrate due to the difference in lattice constant and thermal expansion coefficient between Si and GaAs. In order to reduce the dislocation, a method of performing thermal cycle annealing or the like, or, for example, Reference 1 (Reference 1: SFFang et al.)
al., Journal of Applied Physics, Vol. 68, R31 (199
0), "Gallium arsenide and other compound semicondu
ctors on sillicon ") and Reference 2 (Reference 2: T. Soga et a
l., Journal of Crystal Growth, Vol. 107, 479 (199
1), "Very low dislocation density GaAs on Si using
As described in "Superlattices grown by MOCVD"), a method of inserting a buffer layer such as a superlattice layer between a Si substrate and a GaAs layer has been attempted. It serves to eliminate dislocations extending on the surface of the layer and to change the direction in which the dislocations extend, and in particular, to use a strained superlattice layer using a lattice-mismatched material as a buffer layer. In the case, due to the internal stress of each layer constituting the strained superlattice layer,
Lattice mismatch is absorbed. As a result, dislocations can be prevented from reaching the surface of the GaAs layer.

[0005]

However, in order to obtain a high lattice mismatch absorption effect using a superlattice layer as a buffer layer, it is necessary to control the intensity of internal stress. For this control, the aluminum
Precise control of the composition of gallium arsenide (Al _x Ga _{1 -x} As) and indium gallium arsenide (In _x Ga _{1 -x} As) and the thickness and number of each layer constituting the superlattice layer were required. . And such precise control was very difficult.

[0006] For this reason, there has been a demand for a method for more easily obtaining a high-quality GaAs layer on a Si substrate.

[0007]

For this reason, the G of the present invention
According to the method of forming an aAs layer, a step of forming a GaAs intermediate layer containing Ga vacancies on a Si substrate to eliminate dislocations or change the direction of progress of dislocations, and to form a surface of the GaAs intermediate layer Forming a GaAs layer.

The GaAs intermediate layer formed above the Si substrate with another layer such as a buffer layer interposed therebetween contains Ga vacancies. For this reason, dislocations generated near the interface with another layer in contact with the Si substrate and reaching the GaAs intermediate layer can be eliminated by the vacancies. In addition, the Ga vacancies can change the traveling direction of the traveling dislocation to a direction different from the traveling direction. Therefore, the surface of the GaAs intermediate layer has GaAs
By forming a layer, a GaAs layer of good quality with reduced dislocations can be obtained.

GaAs containing a large number of such vacancies of Ga
The intermediate layer is formed under the condition that the value of the V / III ratio is higher than 19. However, supply V / III ratio
It is the molar ratio of Group V element to Group III element. Thereby, a large amount of Ga vacancies can be contained in the formed GaAs intermediate layer. Further, this GaAs intermediate layer is formed only by setting the V / III ratio to be at least higher than the normal V / III ratio value of 19 at the minimum, and there is no need to change the growth conditions such as temperature and film thickness. Therefore, it can be formed more easily. In addition, Ga vacancies capable of annihilating dislocations or changing the traveling direction of dislocations can be present in the GaAs intermediate layer. The GaAs layer can be obtained as a high-quality layer with reduced dislocations by growing the GaAs intermediate layer on the surface of the GaAs intermediate layer using a normal method. Therefore, in a simpler method than before,
A high-quality GaAs layer can be formed on a substrate.

Preferably, the value of the V / III ratio is 60
It is good to be above. From experiments performed in the embodiment of the present invention described later, if the value of the V / III ratio is about 60 or more, the number of Ga vacancies in the GaAs intermediate layer is such that the dislocations disappear or change direction. It is believed that holes can be present. Further, it is considered that the higher the value of the V / III ratio, the higher the effect can be obtained.

Preferably, the value of the V / III ratio is 80.
It is preferable to set the value to a value in the range above and 150 or less.

With a V / III ratio within this range, sufficient Ga vacancies can be present in the GaAs intermediate layer to eliminate dislocations or change the direction of the dislocations. In addition, when expensive AsH ₃ is used as a raw material for forming the GaAs intermediate layer, the value of the V / III ratio is preferably 150 or less in order to suppress the manufacturing cost.

Preferably, the method further includes a step of forming a GaAs buffer layer on the Si substrate before the step of forming the GaAs intermediate layer.

In order to further improve the crystallinity of the GaAs layer grown on the GaAs intermediate layer, a GaAs layer is grown on a Si substrate at a lower temperature than usual, and this is used as a buffer layer.

When a GaAs layer provided on the Si substrate is used as a base to form, for example, a solar cell or the like, n ⁺ − for making an ohmic contact with the substrate.
Preferably, a GaAs layer is provided on the GaAs buffer layer. Furthermore, in order to improve the conversion efficiency to the current from the light, preferably provided with n ⁺ -AlGaAs layer n ⁺ -GaAs layer. This n ⁺ -AlGaAs layer is used to prevent the holes for lowering the conversion efficiency from diffusing into the substrate.
It is an F (Back Surface field) layer.

The GaAs layer is formed by using a vapor growth method. Particularly, when the GaAs layer is formed by MOCVD, trimethylgallium ((CH
_{3) 3} Ga), and V arsine as a raw material for group (A
sH ₃ ). Therefore, G
The aAs intermediate layer is set so that the molar ratio of arsine to trimethylgallium contained in the source gas is greater than 19. The value of the molar ratio is preferably set to 60 or more. Further, the most suitable value of the molar ratio is a value in the range of 80 or more and 150 or less.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. It should be noted that the drawings merely schematically show the shapes, sizes, and arrangements of the components so that the present invention can be understood, and thus the present invention is not limited to the illustrated examples.

<First Embodiment> As a first embodiment of the present invention, referring to FIG. 1, a structure including a Si substrate and a GaAs layer serving as a base for manufacturing a solar cell will be described. The method for forming the will be described.

FIG. 1 shows a Si substrate of this embodiment and a Ga substrate.
It is the schematic which shows the structure of the structure containing an As layer, and is shown by the cut surface of the cross section.

In this embodiment, a GaAs layer is formed on a Si substrate by vapor phase epitaxy. Here, MOCVD (Metalorganic chemical v
apordeposition) method (organic metal chemical vapor deposition)
A GaAs layer is epitaxially grown on the upper side of the Si substrate.

G containing vacancies on a Si substrate to eliminate dislocations or change the direction of the dislocations
An A step for forming an aAs intermediate layer and a B step for forming a GaAs layer on the surface of the GaAs intermediate layer are included.

In this example, a GaAs buffer layer is first formed on a Si substrate before performing the step A.

The n ⁺ -Si substrate 11 is carried into a reactor,
The substrate is placed on a table for fixing the substrate. Thereafter, the oxide film on the surface of the Si substrate 11 is removed by heating the heater in the table to raise the substrate temperature to 950 ° C. Next, the substrate temperature is lowered to 430 ° C., and n ⁺ -GaAs
The buffer layer 13 is epitaxially grown on the (100) plane of the Si substrate 11 at a low temperature. In this example, GaAs
Are used, a trimethylgallium (TMG: Ga (CH ₃ ) ₃ ) gas is used as a Ga source gas, and an arsine (AsH ₃ ) gas is used as a As source material. Further, disilane (Si ₂ H) is used as an n-type dopant.
₆ ) is used. The atmospheric pressure in the reactor is 100
Torr, the flow rate of TMG gas is 1.6 sccm, and the flow rate of arsine gas is 30 sccm. At this time, the V / III ratio in the source gas, that is, the [As] (mol) / [Ga] (mol) ratio is set to 19. Here, n
⁺ −GaAs buffer layer 13 is, for example, 20 to 50 nm
Grow to about the thickness.

Next, the base formed in this embodiment is:
Used as a base for manufacturing solar cells. For this reason, a layer that makes an ohmic contact with the substrate 11 is formed. This ohmic contact layer 15 is formed by n ⁺ -Ga
It is formed on the As buffer layer 13. The ohmic contact layer 15 is an n ⁺ -GaAs layer 15 in this example, and is formed continuously in the same reaction furnace after the formation of the n ⁺ -GaAs buffer layer 13. The substrate temperature at this time is a normal GaAs layer growth temperature. Therefore, here, the substrate temperature is set to 720 ° C. Also, the n ⁺ -GaAs layer 15
Is, for example, 2 × 10 ¹⁷ (atoms) / cm ³ . n ⁺ -GaAs n ⁺ -GaA on the buffer layer 13
The s layer 15 is grown by 0.2 μm.

Further, in order to use the base to be formed as a base for manufacturing a solar cell, a BSF layer 17 for improving the conversion efficiency from light to current is formed. The BSF layer 17 can prevent holes that lower conversion efficiency from diffusing into the substrate. Here, the BSF layer 17 is formed of n ⁺ −
And AlGaAs layer, on n ⁺ -GaAs layer 15, n ⁺
-Formed continuously with the formation of the GaAs layer 15; In this example, the n ⁺ -AlGaAs layer 17 has an impurity concentration of, for example, 2 × 10 ¹⁸ (atoms) / cm ³ and is formed to a thickness of 0.3 μm. In addition, the substrate temperature is set to normal 720 ° C.

Next, the step A for forming a GaAs intermediate layer is performed.

In order to form a lot of Ga vacancies in the GaAs intermediate layer 19, V / III
The ratio ([As] / [Ga] ratio) is set higher than the normal value of 19. In this example, the value of the V / III ratio is 97. Also,
The substrate temperature is set to 720 ° C. as usual. This gives n ⁺
An n-GaAs intermediate layer 19 is grown on the AlGaAs layer 17 to a thickness of 0.5 μm.

Thereafter, a step B for forming a GaAs layer is performed.

In this example, the GaAs layer 21 is grown using a thermal cycle method in which a heat treatment step is performed during the crystal growth. First, an n ⁺ -GaAs buffer layer 13 on the n ⁺ -Si substrate 11, an n ⁺ -GaAs layer 15, n ⁺ -Al
An annealing process is performed on the structure including the GaAs layer 17 and the n-GaAs intermediate layer 19 in this order at 900 ° C. for 3 minutes. Thereafter, the temperature of the substrate is once lowered to 450 ° C. and then to 720 ° C. again. Then, the value of the V / III ratio is set to a normal value of 19, and a first n-GaAs film 21a is formed on the surface of the n-GaAs intermediate layer 19 (this is referred to as a first film).
Is formed to a thickness of 1 μm. The impurity concentration of the first film 21a is set to 2 × 10 ¹⁷ (atoms) / cm ³ .

After that, the second annealing is performed in the growth furnace without taking out the structure from the growth furnace. Here, after performing the annealing treatment at 900 ° C. for 3 minutes,
The substrate temperature is reduced to 450 ° C.

Next, at a substrate temperature of 720 ° C. and under the same growth conditions as the first film, a second n-GaAs film 21b (hereinafter referred to as a second film) is formed on the first film 21a by 1 μm. Formed to a thickness of

Thereafter, a third annealing is performed on the structure grown up to the second film 21b. Here, 9
After performing heat treatment at 00 ° C. for 3 minutes, the substrate temperature is increased to 450 ° C.
Down to

Thereafter, the first film 21a and the second film 21b
Similarly, the third n-GaAs film 21c (hereinafter, referred to as a third film) is formed with a thickness of 1 μm on the second film 21b.

Thus, the first film 21a and the second film 21b
N-GaAs having a thickness of 3 μm and a third film 21c
The s layer 21 is formed. Then, Ga is placed on the Si substrate 11.
As buffer layer 13 and ohmic contact layer 15
, A BSF layer 17, a GaAs intermediate layer 19, and GaAs.
The underlayer 10 for manufacturing a solar cell, in which the layers 21 and 21 are laminated in this order, is obtained (FIG. 1).

(Comparative Example 1) Next, as Comparative Example 1,
Almost in the same manner as in the first embodiment, Ga
As buffer layer, ohmic contact layer, BSF
A structure having a layer, a GaAs intermediate layer, and a GaAs layer in this order is formed. However, in this comparative example, GaA
When the s intermediate layer is formed, the value of the V / III ratio is set to 19, which is the same as when forming a normal GaAs layer.

Next, the GaAs formed in the first embodiment is used.
The crystallinity of the s layer and the crystallinity of the GaAs layer formed in Comparative Example 1 are compared.

Here, the crystallinity of the GaAs layer was evaluated by A
r ⁺ laser (wavelength λ = 514.5 nm) excitation,
Photoluminescence intensity at 7K (PL intensity)
This is done by measuring This is because, when a sample irradiated with light has a defect such as dislocation, the defect portion becomes a non-emission center, and the emission intensity is lower than that of a sample having no defect. The lower the emission intensity, the more dislocations are present in the GaAs layer. Here, in order to obtain not only the surface of the GaAs layer but also the crystallinity inside,
The PL intensity near the surface of the As layer and the PL intensity inside the As layer are measured. For this reason, a portion where the GaAs layer is etched to a depth of about 0.1 μm is a measurement point near the surface, and a portion where the GaAs layer is etched to a depth of about 1.3 μm is Ga.
This is a measurement point inside the As layer. The etching is 4
It is performed by a wet etching method using H ₂ O ₄ / H ₂ O ₂ / H ₂ O as an etchant. Further, in order to improve the measurement accuracy, measurement is performed at four different points in the same sample (GaAs layer), and the average and standard deviation are taken as the measurement result. The measured value of each sample is determined based on the emission intensity of the (100) plane of the n ⁺ -GaAs layer having high reproducibility and high intensity.

Table 1 shows the measurement results of the PL intensities of the GaAs layer of the first embodiment and the GaAs layer of the comparative example. In Table 1, the PL intensity shows the measurement results near the surface,
The internal measurement results are shown in PL intensity. Further, the ratio of PL intensity to PL intensity is shown as relative intensity /. This relative intensity indicates a state of attenuation of the intensity in the inward direction.

[0039]

[Table 1]

As a result, referring to Table 1, in the GaAs layer of the first embodiment, the PL intensity near the surface was 79.5 and the PL intensity inside was 51. Also,
The relative strength was 0.64.

In the GaAs layer of Comparative Example 1,
The PL intensity near the surface was 68 and the PL intensity inside was 33. This relative intensity was 0.49.

In the sample of the first embodiment,
The PL intensity near the surface is higher than the PL intensity near the surface of the sample of Comparative Example 1. This means that the dislocation density in the vicinity of the surface could be reduced as compared with the conventional case, suggesting that the crystallinity has been improved. In addition, the relative intensity of the PL intensity is comparative example 1
Is bigger than. This indicates that the rate of attenuation of the PL intensity in the inward direction is small. The internal direction is a direction toward the interface between the Si substrate where dislocation occurs and another layer. The fact that the attenuation of the PL intensity in the inward direction is small means that dislocations are reduced even in a portion of the GaAs layer near the interface.

Therefore, when epitaxially growing a GaAs layer on a Si substrate, a normal GaAs layer is formed on the Si substrate.
If a GaAs intermediate layer is formed with a value higher than the value of the V / III ratio, and a GaAs layer is grown on the GaAs intermediate layer, a GaAs layer with high crystallinity can be obtained. The GaAs intermediate layer is formed at an appropriate temperature at the same temperature as the other GaAs layers so that the dislocations can be eliminated or the direction of the dislocations can be changed. For this reason,
The GaAs intermediate layer can be easily formed only by controlling the V / III ratio. Also, GaAs is deposited on the GaAs intermediate layer.
The s layer may be formed as usual. Thereby, a GaAs layer having high crystallinity can be formed by a simple method.

<Second Embodiment> As a second embodiment of the present invention, the same as in the first embodiment,
On a substrate, a GaAs buffer layer, an ohmic contact layer, a BSF layer, and a GaAs intermediate layer are formed in this order by M.
It is formed using an OCVD method. In this embodiment, the heat treatment is performed three times after the GaAs layer is formed on the GaAs intermediate layer.

Hereinafter, differences from the first embodiment will be described with reference to FIG. 2, and detailed description of the same points as those in the first embodiment will be omitted.

FIG. 2 shows the Si substrate of the second embodiment and G
FIG. 2 is a schematic structural diagram of a structure including an aAs layer. FIG. 2 is shown by a cross-section.

As in the first embodiment, n ⁺ -S
An n ⁺ -GaAs buffer layer 13 of 20 to
It is grown at a low temperature (430 ° C.) to a thickness of 50 nm. Followed by forming a n ⁺ -GaAs layer as an ohmic contact layer 15 on the n ⁺ -GaAs buffer layer 13 to a thickness of 0.2 [mu] m. Further, an n ⁺ -AlGaAs layer having a thickness of 0.3 μm is formed on the n ⁺ -GaAs layer 15 as the BSF layer 17. Next, the 97 values of the V / III ratio as in the first embodiment, on the n ⁺ -AlGaAs layer 17, n
Forming the GaAs intermediate layer 19 to a thickness of 0.5 μm;
These n ⁺ -GaAs layer 15, n ⁺ -AlGaAs layer 17, and n-GaAs intermediate layer 19 have a substrate temperature of 72.
It is formed at 0 ° C.

Next, a GaAs layer 31 is formed.

In this example, at a substrate temperature of 720 ° C., V / II
The n-GaAs layer 31 is epitaxially grown to 3 .mu.m with the value of the I ratio set to 19 (FIG. 2). This n-GaAs layer 3
The impurity concentration of 1 is 2 × 10 ¹⁷ (atoms) / cm ³ .

After that, the structure on which the n-GaAs layer 31 is formed is subjected to first annealing at 900 ° C. for 3 minutes. Then, after lowering the substrate temperature to 450 ° C., a second annealing is performed at 900 ° C. for 3 minutes. Thereafter, similarly, after lowering the substrate temperature to 450 ° C., a third annealing is performed at 900 ° C. for 3 minutes. Thus, after the growth of the n-GaAs layer 31, the annealing process is performed three times continuously.

Thus, GaAs is formed on the Si substrate 11.
Buffer layer 13, ohmic contact layer 15, B
SF layer 17, GaAs intermediate layer 19, and GaAs layer 31
Are laminated in this order to obtain a base 20 for manufacturing a solar cell (FIG. 2).

Comparative Example 2 As Comparative Example 2, a GaAs buffer layer, an ohmic contact layer, a BSF layer and a GaAs buffer layer were formed on a Si substrate in almost the same manner as in the second embodiment.
A structure having a GaAs intermediate layer and a GaAs layer in this order is formed. However, in this comparative example, when the GaAs intermediate layer is formed, the value of the V / III ratio is changed to the normal GaAs.
9.7, which is lower than when the s layer is formed.

Comparative Example 3 As Comparative Example 3, a structure similar to that of Comparative Example 2 is formed. In this example, when the GaAs intermediate layer is formed, the value of the V / III ratio is set to 19, which is the same as when forming a normal GaAs layer.

Comparative Example 4 As Comparative Example 4, a structure similar to Comparative Examples 2 and 3 is formed. In this example,
When the GaAs intermediate layer is formed, the value of the V / III ratio is set higher than that of the normal GaAs layer and lower than that of the GaAs intermediate layer of the second embodiment.
Let it be 2.

Next, the GaAs formed in the second embodiment is used.
The crystallinities of the s layer and the GaAs layers formed in Comparative Examples 2 to 4 are compared.

[0056] Here, by Ar ⁺ laser excitation, 77
The photoluminescence intensity (PL intensity) at K is measured. In order to measure the PL intensity near the surface of the GaAs layer, the GaAs layer of each sample was etched to expose a 0.2 μm deep portion.
It is a measurement point near the surface. In order to measure the PL intensity inside the GaAs layer, the GaAs layer of each sample was etched to expose a 2.0 μm deep portion, and this portion was used as an internal measurement point. . The etching is performed by a wet etching method using 4H ₂ O ₄ / H ₂ O ₂ / H ₂ O as an etching solution. Also,
Same sample (GaAs layer) to improve measurement accuracy
The measurement is performed at four different points, and the average and standard deviation are taken as the measurement result. The measured value of each sample is determined based on the emission intensity of the (100) plane of the n ⁺ -GaAs layer having high reproducibility and high intensity.

Table 2 shows the measurement results of the PL intensities of the GaAs layer of the second embodiment and the GaAs layers of Comparative Examples 2 to 4. In Table 2, the PL intensity shows the measurement results near the surface, and the PL intensity shows the internal measurement results. Further, the ratio of PL intensity to PL intensity is shown as relative intensity /. This relative intensity indicates a state of attenuation of the intensity in the inward direction.

[0058]

[Table 2]

As a result, referring to Table 2, in the GaAs layer of the second embodiment, the PL intensity near the surface was 68.7 and the PL intensity inside was 43.6. Further, the relative strength was 0.64.

In the GaAs layer of Comparative Example 2,
The PL intensity near the surface is 17.9, and the PL intensity inside is 1
3.4. This relative strength was 0.75.

In the GaAs layer of Comparative Example 3,
The PL intensity near the surface was 45.5, and the PL intensity inside was 25.5.
5.8. This relative intensity was 0.57.

In the GaAs layer of Comparative Example 4,
The PL intensity near the surface is 40.4 and the PL intensity inside is 1
6.3. This relative intensity was 0.40.

FIG. 3 shows a change characteristic of the PL intensity with respect to the value of the V / III ratio. In FIG. 3, V / II is plotted on the horizontal axis.
The I ratio is shown, and the PL axis is shown on the vertical axis. this
The value of the V / III ratio was determined according to the second embodiment and Comparative Examples 2 to 3.
These values were set when the GaAs intermediate layer of the sample No. 4 was formed. The values of the V / III ratio were set to 9.7 (Comparative Example 2), 19 (Comparative Example 3), 52 (Comparative Example 4), and 97 (Second Embodiment), and G was formed.
The PL intensity near and inside the surface of the GaAs layer provided on the aAs intermediate layer is shown. The white circles indicate the PL intensity near the surface, and the black circles indicate the PL intensity from the surface.
The PL intensity inside the portion at a depth of μm is shown.
Also, the width of each measured value is shown in the direction of the vertical axis, which indicates the dispersion of the measured values measured at four different points of each sample at the time of measuring the PL intensity. Is the maximum value, and the lower end is the minimum value of the measured values. The values represented by white circles and black circles are the values shown in Table 2.

Referring to Table 2 and FIG. 3, Comparative Example 2
Although the relative intensity of PL intensity is small, the PL intensity is low near the surface and inside, and the dislocation density is high. In Comparative Example 3, which is a standard sample, the dislocation density near and inside the surface of the GaAs layer can be lower than in Comparative Example 2. In Comparative Example 4, no reduction in the dislocation density was observed near the surface or inside.
It is substantially the same as Comparative Example 3. In the GaAs layer of the second embodiment, the PL intensity near the surface and inside was significantly higher, and the dislocation density could be reduced. Further, in the GaAs layer of this embodiment, the relative intensity of the PL intensity is larger than that of the other comparative examples (except for Comparative Example 2). Therefore, it is considered that the number of dislocations in the entire GaAs layer could be reduced.

Therefore, when epitaxially growing a GaAs layer on a Si substrate, a normal GaAs layer is formed on the Si substrate.
A value higher than the value of the V / III ratio (19), preferably 60
If a GaAs intermediate layer is formed with a value of about the above, more preferably 80 or more, and a GaAs layer is grown on the GaAs intermediate layer, GaAs having high crystallinity can be obtained.
In addition, since arsine, which is a raw material of As, is an expensive material, the value of the V / III ratio is set to 150 in order to suppress the production cost.
It is preferable to set the following.

In the growth of the GaAs layer, the thermal anneal method of performing a heat treatment during the crystal growth may not be used, and the GaAs layer may be annealed after the growth as in this embodiment. GaAs with high crystallinity
An s layer is obtained. Therefore, GaAs provided with a GaAs layer
By controlling the value of V / III ratio when forming the intermediate layer,
A GaAs layer with high crystallinity can be more easily formed on a Si substrate.

In the first and second embodiments, the GaAs layer is grown by MOCVD. However, the present invention is not limited to this, and MBE (Molecular Beam Epitaxy) may be used. However, when the MBE method is used, GaA
The GaAs intermediate layer on which the s layer is provided contains Ga vacancies that annihilate dislocations or change the direction of the dislocations.

Instead of the GaAs intermediate layer, an Al _1-x Ga _x As layer containing Ga (where x is a mixed crystal ratio and a value satisfying 0 <x <1) is used as the intermediate layer. May be used. In this case, when forming the intermediate layer, the molar ratio of the sum of the As concentration, which is the group V element concentration in the source gas, and the group III element concentration, ie, the sum of the Ga concentration and the Al concentration ([As] /
[Ga] + [Al]) may be set to a value within the range of 80 to 150.

[0069]

As is apparent from the above description, according to the method of forming a GaAs layer of the present invention, Ga vacancies that dissipate dislocations or change the traveling direction of dislocations are formed on a Si substrate. And a step of forming a GaAs layer on the surface of the GaAs intermediate layer.

The GaAs intermediate layer formed on the upper side of the Si substrate contains Ga vacancies. For this reason, dislocations generated near the interface with the layer in contact with the Si substrate and reaching the GaAs intermediate layer can be eliminated by the vacancies. In addition, the Ga vacancies can change the traveling direction of the traveling dislocation to a direction different from the traveling direction. Therefore, if a GaAs layer is formed on the surface of the GaAs intermediate layer, a GaAs layer of good quality with reduced dislocations can be obtained.

GaAs containing a large number of such Ga vacancies
The intermediate layer is formed under the condition that the value of the V / III ratio is at least higher than 19. However, the V / III ratio is
The molar ratio of the Group V element to the Group III element to be supplied.
Thereby, a large amount of Ga vacancies can be contained in the formed GaAs intermediate layer. In addition, this GaAs
The intermediate layer has a V / III ratio of 1 which is a normal V / III ratio value.
Since it is not necessary to change the growth conditions such as the temperature and the film thickness just by forming the film at a height higher than 9, the film can be formed more easily. The GaAs layer can be obtained as a high-quality layer with reduced dislocations by growing the GaAs intermediate layer on the surface of the GaAs intermediate layer using a normal method. Therefore, GaAs of good quality can be deposited on a Si substrate by a simpler method than before.
Layers can be formed.

[Brief description of the drawings]

FIG. 1 is a schematic configuration diagram of a base for manufacturing a solar cell, for explanation of a first embodiment.

FIG. 2 is a schematic configuration diagram of a base for manufacturing a solar cell, for explanation of a second embodiment.

FIG. 3 is a graph showing a change characteristic of a PL intensity with respect to a value of a V / III ratio, which is used for describing a second embodiment.

[Explanation of symbols]

10, 20: Underlayer 11: Si substrate (n ⁺ -Si substrate, substrate) 13: n ⁺ -GaAs buffer layer (GaAs buffer layer) 15: n ⁺ -GaAs layer (ohmic contact layer) 17: n ⁺ -AlGaAs layer (BSF layer) 19: n-GaAs intermediate layer (GaAs intermediate layer) 21, 31: n-GaAs layer (GaAs layer) 21a: first n-GaAs film (first film) 21b: second n-GaAs film (second film) Film) 21c: 3rd n-GaAs film (3rd film)

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5F045 AA04 AB10 AB17 AC01 AC08 AD08 AD11 AE25 AF03 AF13 BB07 BB12 CA13 CB02 DA53 EE12 HA16 5F052 AA11 DA05 DB01 DB06 EA11 GC03 JA09 KA01

Claims (4)

[Claims] When forming a GaAs layer on a Si substrate by vapor phase growth, Ga vacancies on the Si substrate are used to eliminate dislocations or to change the direction of the dislocations. GaAs containing
A method for forming a GaAs layer, comprising: forming an s intermediate layer; and forming the GaAs layer on a surface of the GaAs intermediate layer. 2. The method for forming a GaAs layer according to claim 1, wherein the GaAs intermediate layer has a V / III ratio in a source gas (a molar ratio of a group V element to a group III element in a source gas supplied). Is formed under the condition that the value of is at least higher than 19. 3. The method of forming a GaAs layer according to claim 2, wherein the value of said V / III ratio is set to a value within a range of 80 or more and 150 or less. G
Method for forming aAs layer. 4. The method for forming a GaAs layer according to claim 1, wherein a GaAs buffer layer is formed on the Si substrate before the step of forming the GaAs intermediate layer. A method for forming a GaAs layer, comprising the steps of: