JPH05235173A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

PURPOSE:To reduce the photolithographic steps for the formation of multilayered wirings by a method wherein upper layer wirings are formed of the wider part and the narrower part in the line width thereof than a specific width so as to selfmatchingly form an interlayer connecting hole with the upper layer wirings. CONSTITUTION:Lower layer wirings 114 and upper layer wirings 121 are provided on the first insulating film 111. The upper layer wiring 121 is formed into the wider part and narrower part in line width than a specific width. Next, a throughhole is formed in self-aligned manner with the upper layer wiring 121 in the wider part. Through these procedures, both a through hole and the upper layer wirings 121 can be formed by only one photolithgraphic step enabling a semiconductor device having multilayer wirings to be manufactured by less numbers of step than those in the conventional method. Furthermore, the upper layer wirings 121 and the through hole can be selfmatchingly formed to eliminate any excessive alignment margin thereby enabling the fine wiring pitch to be adopted.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a semiconductor device having a multilayer wiring structure and a method for manufacturing the same.

[0002]

2. Description of the Related Art One example of a conventional semiconductor device having a multilayer wiring structure will be described with reference to FIG. FIG. 11 is a sectional view showing an example of a conventional semiconductor chip of this type. This is a first layer wiring 412 made of aluminum or the like on an insulating film 411 formed on a semiconductor substrate 410 made of silicon. And a second-layer wiring 415 is formed thereover with an interlayer insulating film 413 interposed therebetween. Then, the interlayer insulating film 413 is provided with an interlayer connection hole 414 for electrically connecting the first layer wiring 412 and the second layer wiring 415.

Next, another example of a conventional semiconductor device having a multilayer wiring structure and its manufacturing method will be described with reference to FIGS. 12 to 15 are sectional views in order of manufacturing steps for explaining another example of the conventional semiconductor chip and a manufacturing method thereof, which is one example of the conventional semiconductor chip. The pillars (pillars 516) for interlayer connection are replaced by using plating technology instead of the interlayer connection holes 414 shown in FIG.
3 step E)).

A method of manufacturing this semiconductor chip will be described.
First, as shown in step A of FIG. 12, titanium / tungsten and gold are sequentially laminated as a feeding film 512 for plating on an insulating film 511 formed on a semiconductor substrate 510 made of silicon. As the power supply film 512, titanium other than the above,
A combination of platinum, palladium, titanium nitride, etc. is also possible.

Next, as shown in step B of FIG. 12, a pattern of photoresist 513 for forming the first layer wiring is formed on portions other than this wiring forming portion, and then gold plating is performed as shown in step C of FIG. Then, the wiring 514 of the first layer is formed. Then, after removing the photoresist 513, as shown in FIG.
Pillars for pillar connection (pillar 516) as shown in 3 step D
The photoresist 51 is formed on the portion other than the portion where the (see next step E) is formed.
Form 5 patterns.

Next, as shown in step E of FIG. 13, gold plating is performed to form pillars (pillars 516) for interlayer connection, and then the photoresist 515 is removed (step F of FIG. 14). Subsequently, as shown in Step G of FIG. 14, the power supply film 512 is removed by etching using the wiring 514 of the first layer as a mask.
Known methods for removing the power supply film 512 include wet etching with aqua regia and dry etching with ion milling.

Next, as shown in step H of FIG. 14, an interlayer insulating film 517 is formed and etched back or the like,
A pillar (pillar 516) for interlayer connection is formed so as to be exposed on the surface of the interlayer insulating film 517. Then, FIG. 15 step I and step J
As shown in FIG.
Similarly to the formation of the wiring 514 of the first layer of D to D, after the power supply film 512 is laminated and the pattern of the photoresist 513 is formed except the wiring forming portion (step I), plating is performed using the photoresist 513 as a mask, The photoresist 513 is removed to form the second layer wiring 518 (step J). Then, by repeating the above steps, a semiconductor device having a multilayer wiring structure is manufactured.

[0008]

In the conventional semiconductor device having the above-mentioned multilayer wiring structure, it is necessary to alternately repeat the photoresist process for forming the wiring and the photoresist process for forming the interlayer connection hole. Therefore, for example, in the case of the four-layer wiring, there is a problem that a large number of photoresist processes of seven times are required. Further, a margin in consideration of misalignment is required between the lower layer wiring and the interlayer connection hole or between the lower layer wiring and the pillar, which has a drawback that it becomes an obstacle in miniaturization. ..

Therefore, it is an object of the present invention to provide a semiconductor device and a method for manufacturing the same which solve the above-mentioned problems and drawbacks of the prior art. More specifically, the present invention aims to provide a semiconductor device and a method of manufacturing the same that can significantly reduce the photolithography process for forming a multi-layer wiring, reduce an extra alignment margin, and enable miniaturization. And

[0010]

According to the present invention, in a semiconductor device having a multi-layer wiring structure, an upper layer wiring has a portion having a line width wider (wider) than a certain width and a portion thin (narrow). In this thick (wide) part, the interlayer connection hole (through hole) is self-aligned with the upper layer wiring.
The present invention provides a semiconductor device that achieves the above-mentioned object. Specifically, in the formation of upper layer wiring and the formation of interlayer connection holes (through holes), in the conventional method, Two photolithographic steps are required, but in the present invention, it is shortened to one.

That is, the present invention comprises two inventions of a semiconductor device and a manufacturing method thereof. Among them, the semiconductor device of the present invention is a semiconductor device having a "multilayer wiring structure, in which a line width of an upper layer wiring is thicker than a certain width. A semiconductor device characterized in that an opening for electrically connecting the lower layer wiring and the upper layer wiring is formed in a thick portion in a self-aligned manner with respect to the upper layer wiring ". It is a thing.

The method of manufacturing a semiconductor device of the present invention is
(1) a step of forming a lower layer wiring on a first insulating film provided on a semiconductor substrate, (2) a step of forming an interlayer insulating film,
(3) A step of forming a power supply film on the interlayer insulating film, (4) A mask pattern for plating made of a photoresist or a resin film in addition to the upper layer wiring forming portion consisting of a portion where the line width is thicker than a certain width and a thin portion And (5) forming a second insulating film on a side surface of the mask pattern and burying a portion where the line width is thinner than a certain width, (6) the line width being thicker than a certain width A step of forming a through hole by using a second insulating film and the photoresist as a mask at a portion, and (7) removing the second insulating film and then forming an upper wiring by a plating method using the photoresist as a mask A gist of the present invention is a method of manufacturing a semiconductor device having a multilayer wiring structure.

[0013]

Embodiments of the present invention will be described in detail below with reference to FIGS. (Embodiment 1) FIG. 1 is a sectional view of a semiconductor chip showing an embodiment of the present invention, and FIGS. 2 to 7 are sectional views showing a method of manufacturing the semiconductor chip in the order of steps.

As shown in FIG. 1, the semiconductor chip according to the first embodiment has a structure in which a lower layer wiring 114 and an upper layer wiring 121 are provided on a first insulating film 111, and moreover, the upper layer wiring 121. As a structure, a portion having a line width thicker than a certain width (see a in FIG. 1) and a thin portion are formed, and through holes are formed in the thick portion in a self-aligned manner with respect to the upper layer wiring 121. is there. In FIG. 1, 110
Is a silicon substrate, 112 is a first feeding film, 115 is a polyimide-based interlayer insulating film, and 116 is a second feeding film.

The method of manufacturing the semiconductor chip shown in FIG. 1 will be described with reference to FIGS. 2 to 7 showing the manufacturing steps of steps A to N. First, as shown in step A of FIG. 500-2000 angstroms of titanium / tungsten and 300 of gold or platinum on the first insulating film 111 provided in
.About.1000 angstroms are sequentially formed by the sputtering method to form the first power supply film 112.

The function of the power supply film is not only to (1) secure the adhesion to the base, (2) a current path for plating and (3) a material that can be plated, but also (4) heat resistance. It is necessary to have a function as a barrier film for ensuring the above. Above (1)
As the material having the functions of (4) to (4), combinations of titanium, platinum, palladium, titanium nitride and the like are well known in addition to the above-mentioned titanium / tungsten, gold or platinum, and as the first power supply film 112, These can also be used.

Next, as shown in step B of FIG. 2, after forming a pattern of the photoresist 113 in a portion other than the lower layer wiring forming portion, as shown in step C of FIG. 3, a lower layer wiring 114 is formed by a plating method. .. Subsequently, as shown in step D of FIG. 3, the photoresist 113 is removed, and further, as shown in step E of FIG. 3, the unnecessary first power supply film 112 is removed using the lower layer wiring 114 as a mask by an etching method. ..

Next, as shown in FIG. 4F, a polyimide-based interlayer insulating film 115 is formed. At this time, flattening may be performed by etching back or the like. After that, as shown in Step G of FIG. 4, the second power supply film 116 for forming the upper layer wiring is formed. As the second power feeding film 116, the first power feeding film 112 is used.
Similarly, a titanium / tungsten film of 500 to 2000 angstrom and a film of gold or platinum of 300 to 1000 angstrom are prepared.

Next, as shown in step H of FIG. 4, a pattern of a photoresist 117 is formed on a portion other than the through hole formation planned portion 118 and the wiring planned portion 119 which is the upper layer wiring formation planned portion. At this time, a space between the resist and the resist is widened at a place (a through-hole formation scheduled portion 118) where an interlayer connection hole (hereinafter referred to as a through hole) is to be formed in a later step than at other portions (a wiring planned portion 119). (See a in FIG. 1). For example, change the width of the normal planned wiring portion 119
If it is set to 0.5 μ, the width of the through-hole formation-scheduled portion 118 is made wider than this, and is set to 0.75 μ.

Next, as shown in step I of FIG. 5, an oxide film (second insulating film 120) is deposited on the entire surface by, eg, sputtering, and then reactive ion etching is performed as shown in step J of FIG. Etch back is performed using (RIE) or the like, and the oxide film (second insulating film 120) is left on the side surface of the photoresist 117. Thereafter, as shown in step K of FIG. 6, the second power supply film 116 and the interlayer insulating film 115 are sequentially opened using the photoresist 117 and the oxide film (second insulating film 120) as a mask.

Next, as shown in step L of FIG. 6, after the oxide film (second insulating film 120) is removed by etching, as shown in step M of FIG. Form 121. Subsequently, as shown in Step N of FIG. 7, the photoresist 117 and the second power supply film 116 are sequentially removed. Although the two-layer wiring is formed as described above, it is needless to say that the wiring can be further multilayered by repeating this.

(Embodiment 2) FIGS. 8 to 10 are sectional views in order of manufacturing steps showing another embodiment (Embodiment 2) of the present invention.
In the first embodiment, the upper layer wiring 121 is formed by using electroless plating in the process M of FIG. 7, but the second embodiment is different in that the electroplating is used.

First, as in the first embodiment, after the step K in FIG. 6 is completed, as shown in step A in FIG. 8, the third power supply film 122 is formed on the entire surface by the sputtering method. Next, as shown in FIG. 8B, the entire surface is sputter-etched so that the third power supply film 122 on the side surface of the oxide film (second insulating film 120) remains.

Then, the oxide film (second insulating film 120) is removed by etching (step C in FIG. 9), and electroplating is performed to form an upper wiring 121 (step D in FIG. 9). Next, the photoresist 117 and the second power supply film 116 are sequentially removed (step E in FIG. 10).

[0025]

As described in detail above, the present invention provides a semiconductor device having a multi-layer wiring structure, wherein the upper wiring is
The line width is thicker (wider) and thinner (narrower) than a certain width, and an interlayer connection hole (through hole) is formed in the thicker (wide) portion in a self-aligned manner with respect to the upper layer wiring. The feature is that the photolithography process for forming the multi-layered wiring can be significantly reduced, an extra alignment margin can be reduced, and miniaturization can be achieved.

That is, according to the present invention, since the through hole and the upper layer wiring are formed in one photolithographic process,
A semiconductor device having multi-layer wiring can be manufactured in a smaller number of steps than the conventional method. For example, in the case of wiring of four layers, the conventional method requires at least seven photolithography steps, but the method of the present invention has an effect of only four times. In addition, since the upper layer wiring and the through hole are self-aligned, no extra alignment margin is required, and a fine wiring pitch can be achieved.

[Brief description of drawings]

FIG. 1 is a sectional view of a semiconductor chip showing an embodiment of the present invention.

FIG. 2 is a cross-sectional view of steps A to B for explaining an example of a method for manufacturing a semiconductor chip of the present invention in the order of manufacturing steps thereof.

FIG. 3 is a sectional view of steps C to E following FIG.

FIG. 4 is a cross-sectional view of steps FH subsequent to FIG.

5 is a cross-sectional view of steps I to J following FIG.

6 is a cross-sectional view of steps KL subsequent to FIG.

FIG. 7 is a cross-sectional view of steps MN subsequent to FIG.

FIG. 8 is a sectional view of steps A to B for explaining another example of the method for manufacturing a semiconductor chip of the present invention in the order of manufacturing steps thereof.

FIG. 9 is a cross-sectional view of steps C to D following FIG.

FIG. 10 is a sectional view of a step E following FIG. 9;

FIG. 11 is a cross-sectional view showing an example of a conventional semiconductor chip.

FIG. 12 is a cross-sectional view of steps A to C for explaining another example of the conventional semiconductor chip and the manufacturing method thereof.

13 is a cross-sectional view of steps D to E following FIG.

FIG. 14 is a cross-sectional view of steps FH that follows FIG.

FIG. 15 is a cross-sectional view of steps IJ subsequent to FIG.

[Explanation of symbols]

 110 Silicon Substrate 111 First Insulating Film 112 First Feeding Film 113 Photoresist 114 Lower Wiring 115 Interlayer Insulating Film 116 Second Feeding Film 117 Photoresist 118 Through Hole Forming Part 119 Wiring Part 120 Second Insulating Film 121 Upper Layer Wiring 122 Third feeding film 410 Semiconductor substrate 411 Insulating film 412 First layer wiring 413 Interlayer insulating film 414 Interlayer connection hole 415 Second layer wiring 510 Semiconductor substrate 511 Insulating film 512 Power feeding film 513 Photoresist 514 First layer wiring 515 Photoresist 516 Pillar 517 Interlayer insulating film 518 Second layer wiring

Claims (2)

[Claims] 1. In a semiconductor device having a multilayer wiring structure, a line width of an upper layer wiring is composed of a portion thicker and a portion narrower than a certain width, and an opening for electrically connecting the lower layer wiring and the upper layer wiring is formed in the thick portion in the upper layer. A semiconductor device, which is formed in a self-aligned manner with respect to wiring. 2. A step of forming a lower layer wiring on a first insulating film provided on a semiconductor substrate, a step of forming an interlayer insulating film, and a step of forming an interlayer insulating film on the interlayer insulating film. A step of forming a power supply film, (4) a step of forming a masking pattern for plating made of a photoresist or a resin film in a portion other than an upper layer wiring forming part having a line width thicker and a thinner part than a certain width, (5) A step of forming a second insulating film on a side surface of the mask pattern and burying a portion where the line width is thinner than a certain width; (6) the second insulating film and the portion where the line width is thicker than the certain width. A step of forming through holes using a photoresist as a mask; (7) a step of forming an upper layer wiring by a plating method using the photoresist as a mask after removing the second insulating film; Method of manufacturing semiconductor device.