JP2884849B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device having a multilayer wiring structure.

[0002]

2. Description of the Related Art Conventionally, a multi-layer wiring structure of this kind has
Alternatively, it is formed as shown in FIGS.

That is, in FIG. 14, a first layer wiring 412 made of aluminum or the like is formed on an insulating film 411 formed on a semiconductor substrate 410 made of silicon, and an interlayer insulating film is formed thereon. A second layer wiring 415 is formed via 413. The interlayer insulating film 413 is provided with an interlayer connection hole 414 for electrically connecting the first layer wiring 412 and the second layer wiring 415.

Next, another conventional technique shown in FIGS. 15 to 24 will be described.

In this example, a pillar (pillar) for interlayer connection is used in place of the interlayer connection hole by using a plating technique.

First, as shown in FIG. 15, on a dielectric film 511 formed on a semiconductor substrate 510 made of silicon, titanium / tungsten and gold are sequentially laminated as a power supply film 512 for plating. As the power supply film, a combination of titanium, platinum, palladium, titanium nitride, and the like can be used.

Next, as shown in FIG. 16, a photoresist pattern 513 for forming a first layer wiring is formed in a portion other than the wiring forming portion.

Next, as shown in FIG. 17, gold plating is performed to form a first layer wiring 514.

Next, as shown in FIG. 18, after removing the photoresist, a photoresist pattern 515 is formed in portions other than the portions where pillars (pillars) for interlayer connection are to be formed.

Next, as shown in FIG. 19, gold plating is performed to form pillars 516 for interlayer connection.

Next, as shown in FIG. 20, the photoresist is removed.

[0012] Next, as shown in FIG.
Using the mask 14 as a mask, the power supply film 512 is removed by etching. As a method of removing the power supply film, wet etching using aqua regia and dry etching using ion milling or the like are known.

Next, as shown in FIG. 22, by forming an interlayer insulating film and performing etch-back or the like, pillars (pillars) for interlayer connection are formed so as to protrude from the surface of the interlayer insulating film .

Next, as shown in FIG. 23 and FIG.
A second layer wiring is formed in the same manner as the layer. In the case of multilayer wiring, the above is repeated.

[0015]

In this conventional multilayer wiring structure, it is necessary to alternately repeat a photoresist process for forming wiring and a photoresist process for interlayer connection. Therefore, for example, in the case of a four-layer wiring, seven photoresist steps are required. Also, a margin is required between the lower wiring and the interlayer connection hole or the pillar in consideration of misalignment, which has been an obstacle to miniaturization.

[0016]

[0017]

According to the present invention, there is provided a method of manufacturing a semiconductor device , comprising the steps of: forming a power supply film on a first insulating film provided on a semiconductor substrate; A step of forming a mask pattern for plating made of, for example, a photoresist or a resin film other than a lower layer wiring forming portion having a portion wider and a portion thinner than a width of the mask pattern, and forming a second insulating film on a side surface of the mask pattern. Embedding a portion where the line width is smaller than a predetermined width; and selectively embedding a first portion in an exposed portion of the power supply film surrounded by the second insulating film at a portion where the line width is larger than the predetermined width. Forming a base of pillars for electrically connecting the lower layer wiring and the upper layer wiring by applying the metal film of the above, a step of removing the second insulating film by etching, A second metal film is formed on the first metal film by plating. A step of forming, after removing the mask pattern made of the photoresist or resin film or the like, the second
Etching the power supply film using the metal film as a mask, forming an interlayer film below the height of the column made of the first and second metal films, and forming an upper wiring. It is characterized by having.

[0018]

Next, an embodiment of the present invention will be described with reference to the drawings.

First, as a first embodiment, as shown in FIG. 1, a 500-2000 angstrom thick titanium tungsten film and a 300-1000 angstrom thick film are formed on a first insulating film 111 provided on a silicon substrate 110. Power supply film 1 formed of gold or platinum sequentially by sputtering
12 is formed. The function of the power supply film is not only a material that can be adhered to the base, a current path for plating and a material that can be plated, but also a function as a barrier film for ensuring heat resistance may be necessary. . As the power supply film, a combination of titanium, platinum, palladium, titanium nitride, and the like can be used.

Next, as shown in FIG. 2, a photoresist pattern 113 is formed in a portion other than the portion where the lower layer wiring is formed. At this time, the width X of the portion 102 where the pillar is formed in a later step is made wider than the width Y of the other portions 101.
For example, if Y is 0.5 μm in the normal portion 101, the width X of the pillar forming portion 102 is increased to 0.75 μm.

Next, as shown in FIG. 3, after an oxide film is deposited by, for example, a sputtering method, a second layer of the oxide film is formed on the side surface of the photoresist by a reactive ion etch (RIE) method.
Etch back so that the insulating film 114 remains.

At this time, portions 101 other than the pillar formation portion are buried with an oxide film 114. Depending on the thickness of the oxide film,
The film thickness remaining on the side surface at the pillar formation portion 102 is also controlled. Assuming that the width X of the pillar forming portion 102 is 0.75 μm, the oxide film thickness X on the side surface portion is preferably about 0.25 to 0.3 μm.

Next, as shown in FIG. 4, a pillar base 115 is formed by plating. For example, it is formed to a thickness of about 2 μm by electroplating gold.

Next, as shown in FIG. 5, the oxide film 114 on the side surface is removed by etching.

Next, as shown in FIG. 6, the pillar forming portion 102 and the wiring portion 116 of the other portion 102 are formed again by the gold plating method. If the wiring portion is 1 μm thick, the pillar portion is completed at a height of 3 μm.

Next, as shown in FIG. 7, after the resist 113 is removed, the exposed portion of the power supply film 112 is removed by etching.

Next, as shown in FIG. 8, an interlayer insulating film 117 is formed.
Is formed to be equal to or less than the height of the pillar. That is, the head of the pillar is slightly projected from the surface of the interlayer insulating film. As the interlayer film, SiO 2 grown by plasma CVD was used.
₂ , a laminated structure of SiON, SiN, etc. and sgin-on-glass, or a polyimide-based insulating film or the like is formed, and flattened by performing etch back or the like.

FIG. 9 is a plan view, and FIG. 8 is a cross section taken along the line AA in FIG.

Next, as shown in FIG. 10, a power supply film 118 for plating for forming an upper wiring is formed in the same manner as the lower power supply film 112, and a photoresist pattern 119 is further formed.

Next, as shown in FIG. 11, the upper wiring 120 is formed by gold plating, the resist is removed, and the unnecessary unnecessary power supply film 118 is removed by etching.

As is clear from FIG.
The top of the pillar 130 slightly projecting from the upper layer 7 is connected to the upper layer wiring composed of the layer 120 and the underlying film 118, whereby a predetermined connection between the upper layer wiring and the lower wiring composed of the layer 116 and the underlying film 112 is made. It is.

Next, a second embodiment of the present invention will be described. Similar to the first embodiment, after forming up to the step of FIG. 3, when plating for the pillar base 215, less expensive plating of nickel or the like is performed. After that, as in the first embodiment, the pillar base 215 is used for the gold plating 116 in the subsequent process.
Is completely covered to form the pillar 140, so that even if an inexpensive material is used, problems such as corrosion and deterioration do not occur.
Even if a material having a high resistance is used, the conduction resistance does not increase so much. FIGS. 12 and 13 showing the second embodiment correspond to FIGS. 5 and 6, respectively, showing the first embodiment. The same functions as those in the first embodiment are denoted by the same reference numerals.

Next, a third embodiment of the present invention will be described.

Similar to the second embodiment, after the steps shown in FIG. 3 are formed, the pillar base is formed by the selective CVD method. For example, selective CVD tungsten is formed to a thickness of 2 μm. Subsequent steps are the same as in the first embodiment. The drawings are omitted.

[0035]

As described above, according to the present invention, a lower layer wiring and a pillar are formed in one photolithographic process, so that a semiconductor device having a multilayer wiring can be manufactured with a smaller number of steps. For example, in the case of four layers,
In the case of the present invention, the number of photolithography steps required is four, which is only four.

Further, since the lower wiring and the pillar are self-aligned, a finer wiring pitch can be achieved.

Further, as in the second embodiment, there is no problem even if the pillar base is replaced with an inexpensive metal, so that the production cost can be reduced. Since the upper part of the pillar and the wiring can be formed by one plating, metal grains are continuously formed, and the reliability is improved.

[Brief description of the drawings]

FIG. 1 is a drawing showing a first embodiment of the present invention.

FIG. 2 is a diagram showing a first embodiment of the present invention.

FIG. 3 is a drawing showing a first embodiment of the present invention.

FIG. 4 is a drawing showing a first embodiment of the present invention.

FIG. 5 is a diagram showing a first embodiment of the present invention.

FIG. 6 is a drawing showing a first embodiment of the present invention.

FIG. 7 is a drawing showing a first embodiment of the present invention.

FIG. 8 is a diagram showing a first embodiment of the present invention.

FIG. 9 is a view showing a first embodiment of the present invention.

FIG. 10 is a diagram showing a first embodiment of the present invention.

FIG. 11 is a diagram showing a first embodiment of the present invention.

FIG. 12 is a view showing a second embodiment of the present invention.

FIG. 13 is a view showing a second embodiment of the present invention.

FIG. 14 is a view showing a conventional technique.

FIG. 15 is a view showing a conventional technique.

FIG. 16 is a view showing a conventional technique.

FIG. 17 is a view showing a conventional technique.

FIG. 18 is a view showing a conventional technique.

FIG. 19 is a view showing a conventional technique.

FIG. 20 is a view showing a conventional technique.

FIG. 21 is a view showing a conventional technique.

FIG. 22 is a view showing a conventional technique.

FIG. 23 is a view showing a conventional technique.

FIG. 24 is a view showing a conventional technique.

[Explanation of symbols]

 Reference Signs List 101 Wiring location not forming pillar 102 Wiring location forming pillar 110 Semiconductor substrate 111, 114 Insulating film 112, 118 Feeding line for plating 113 Photoresist pattern 115, 215 Pillar base 116 Lower wiring by gold plating 117 Interlayer insulating film 12 Gold plating Upper layer wiring 130, 140 pillar

Claims (1)

(57) [Claims] A step of forming a power supply film on a first insulating film provided on a semiconductor substrate; and a step of plating a portion other than a lower wiring forming portion having a portion having a line width larger and smaller than a predetermined width. Forming a second insulating film on a side surface of the mask pattern and embedding a portion where the line width is smaller than a certain width; and forming a portion where the line width is larger than a certain width. Forming a base of a pillar for selectively applying a first metal film to an exposed portion of the power supply film surrounded by the second insulating film and electrically connecting the lower wiring and the upper wiring, Removing the second insulating film by etching, forming a second metal film by plating on the newly exposed power supply film and the first metal film, and removing the mask pattern After that, the power supply film is etched using the second metal film as a mask. A removing step, a step of forming an interlayer film below the height of the column made of the first and second metal films, and a step of forming an upper layer wiring. A method for manufacturing a semiconductor device.