JPH05235075A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH05235075A
JPH05235075A JP3812692A JP3812692A JPH05235075A JP H05235075 A JPH05235075 A JP H05235075A JP 3812692 A JP3812692 A JP 3812692A JP 3812692 A JP3812692 A JP 3812692A JP H05235075 A JPH05235075 A JP H05235075A
Authority
JP
Japan
Prior art keywords
bus bar
bonding wire
wire
bonding
thin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3812692A
Other languages
Japanese (ja)
Inventor
Toshio Kawamura
村 敏 雄 川
Takashi Suzumura
村 隆 志 鈴
Hiroshi Sugimoto
本 洋 杉
Hiroyuki Kosaka
坂 博 之 高
Yoshinori Bando
東 良 則 坂
Ichiro Anjo
生 一 郎 安
Junichi Arita
田 順 一 有
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Cable Ltd
Hitachi Ltd
Original Assignee
Hitachi Cable Ltd
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Cable Ltd, Hitachi Ltd filed Critical Hitachi Cable Ltd
Priority to JP3812692A priority Critical patent/JPH05235075A/en
Publication of JPH05235075A publication Critical patent/JPH05235075A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/4826—Connecting between the body and an opposite side of the item with respect to the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73215—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]

Abstract

PURPOSE:To lessen a package in thickness by a method wherein a part of a bus bar confronting the transversing section of a bonding wire is cut out or set thin-walled. CONSTITUTION:A power supply bus bar 2 is pasted on an adhesive double-coated tape 3. A bonding wire 5 connects the inner lead 1a of a lead frame 1 to the pad 4a on a silicon chip 4, crossing over the bus bar 2. The bus bar 2 is connected to the silicon chip 4 with a bonding wire 6. The part of the bus bar 2 where the bonding wire 5 crosses over is made thin-walled. By this setup, the bonding wire 5 can be set low in bonding level, and the bus bar 2 can be surely separated from the bonding wire 5 by a distance enough for insulation.

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【産業上の利用分野】本発明は薄型パッケージ（THIN S
MALL OUTLINE PACKAGE）用半導体装置に関する。The present invention relates to a thin package (THIN S
Semiconductor device for MALL OUTLINE PACKAGE).

【０００２】[0002]

【従来の技術】面付け型のパッケージでは高密度実装の
要求から年々、薄型化してきている。図４、５は現在試
作検討中薄型パッケージである（タイプ１−ＴＳＯ
Ｐ）。2. Description of the Related Art Imposition type packages are becoming thinner year by year due to the demand for high-density mounting. 4 and 5 are thin packages currently under trial (Type 1-TSO
P).

【０００３】このパッケージ構造（LEAD ON CHIP）で
は、電源ライン（バスバー）２がチップ４内側に２本配
置されており信号用のワイヤ５が前記電源ライン２上を
通過してチップ４上のパッド４ａへワイヤボンドされる
構造となっている。また、薄型化を図るためにボンディ
ングワイヤ５の成形高さを低くする台形ループが採用さ
れ、パッケージの総厚さとして約１ｍｍのパッケージが
現在試作されている。１はリードフレーム、３はフィル
ム（両面接着剤付）である。In this package structure (LEAD ON CHIP), two power supply lines (bus bars) 2 are arranged inside the chip 4, and signal wires 5 pass over the power supply line 2 and pads on the chip 4 are provided. 4a is wire-bonded to the structure. In addition, a trapezoidal loop for reducing the molding height of the bonding wire 5 is adopted in order to reduce the thickness, and a package having a total package thickness of about 1 mm is currently being prototyped. Reference numeral 1 is a lead frame, and 3 is a film (with adhesive on both sides).

【０００４】[0004]

【発明が解決しようとする課題】従来技術の問題点を列
挙すると、 （１）例えば図６に示した従来のＴＳＯＰ構造図におい
て、信号用ワイヤ５はバスバー２を越えてシリコンチッ
プのパッドにボンディングされるが、バスバー２とボン
ディングワイヤ５の距離が近接しておりレジンモールド
時にショートする可能性が大である。The problems of the prior art are listed as follows: (1) In the conventional TSOP structure diagram shown in FIG. 6, for example, the signal wire 5 crosses the bus bar 2 and is bonded to the pad of the silicon chip. However, since the bus bar 2 and the bonding wire 5 are close to each other, there is a high possibility of short-circuiting during resin molding.

【０００５】（２）信号用リード１とシリコンチップ４
間のボンディングワイヤ５はバスバー２越えのためワイ
ヤ５の高さを低くできない。従って、パッケージを薄く
することが困難である。(2) Signal lead 1 and silicon chip 4
The height of the bonding wire 5 cannot be lowered because it exceeds the bus bar 2. Therefore, it is difficult to make the package thin.

【０００６】本発明の目的は、従来技術の欠点を解消
し、薄型パッケージ（ＴＳＯＰ）用半導体装置を提供す
ることにある。An object of the present invention is to eliminate the drawbacks of the prior art and provide a semiconductor device for a thin package (TSOP).

【０００７】[0007]

【課題を解決するための手段】上記目的を解決するため
に本発明によれば、リードフレームのインナーリード部
が半導体チップ上に絶縁部材を介して固定されるととも
に、前記インナーリード部の先端方向のさらに前方に離
間して電源用のバスバーが配設され絶縁部材を介して前
記チップ上に固定され、それぞれボンディングワイヤで
配線してなる半導体装置において、前記バスバーの少な
くともボンディングワイヤ横断部と対向する部分を切欠
きまたは薄肉としたことを特徴とする半導体装置が提供
される。In order to solve the above-mentioned problems, according to the present invention, an inner lead portion of a lead frame is fixed on a semiconductor chip via an insulating member, and a tip direction of the inner lead portion is In a semiconductor device in which a bus bar for power supply is disposed further apart from the front side of the bus bar, is fixed on the chip via an insulating member, and is wired by a bonding wire, the semiconductor device faces at least a crossing portion of the bus bar. There is provided a semiconductor device having a notch or a thin portion.

【０００８】[0008]

【実施例】以下に本発明を実施例に基づき具体的に説明
する。EXAMPLES The present invention will be specifically described below based on examples.

【０００９】図１は、本発明の一実施例を示すバスバー
近傍の斜視図である。なお、ボンディングワイヤ５、６
の一部は省略してある。FIG. 1 is a perspective view of the vicinity of a bus bar showing an embodiment of the present invention. The bonding wires 5 and 6
Are partially omitted.

【００１０】電源用のバスバー２は、両面に接着剤を有
するフィルム３に貼り付けられ、このバスバー２上を越
えてリードフレーム１のインナーリード部１ａとシリコ
ンチップ４上のパッド４ａとの間がボンディングワイヤ
５で接続される。また、６はバスバー２とシリコンチッ
プ４との間を接続するボンディングワイヤである。The bus bar 2 for power supply is attached to a film 3 having adhesive on both sides, and the space between the inner lead portion 1a of the lead frame 1 and the pad 4a on the silicon chip 4 is crossed over the bus bar 2. It is connected by a bonding wire 5. Further, 6 is a bonding wire for connecting the bus bar 2 and the silicon chip 4.

【００１１】前記バスバー２は、前記ボンディングワイ
ヤ５が横断する側の全面を薄肉に形成している。これに
より、前記ボンディングワイヤ５のボンディング高さを
低くすることが可能となり、十分にワイヤとの絶縁距離
を確保することができる。The bus bar 2 has a thin entire surface on the side traversed by the bonding wire 5. As a result, the bonding height of the bonding wire 5 can be reduced, and a sufficient insulation distance from the wire can be secured.

【００１２】前記バスバー２の薄肉化方法としては、バ
スバー２の全面をプレスによるコイニングまたはエッチ
ングによるハーフエッチ加工によって薄くすることがで
きる。なお、このコイニングまたはハーフエッチ加工に
よるバスバーの残存厚さは、元の厚さの約７０％以下で
あれば有効と考えられる。As a method of thinning the bus bar 2, the entire surface of the bus bar 2 can be thinned by coining by pressing or half etching by etching. It is considered effective if the remaining thickness of the bus bar by the coining or half-etching is about 70% or less of the original thickness.

【００１３】図２は、図１の変形例を示したもので、ワ
イヤ５の通過部のみを厚さ方向に切欠いたものである。FIG. 2 shows a modification of FIG. 1, in which only the passage portion of the wire 5 is cut out in the thickness direction.

【００１４】また、図３は図２と同様、バスバー２の幅
方向に切欠きを設けたものである。また、図２、図３を
組み合わせることも可能であり、この場合はボンディン
グワイヤ５の低ループ化と短尺化の両方において効果大
と考えられる。なお、図２および図３においてボンディ
ングワイヤ５、６の一部は省略してある。Further, in FIG. 3, similarly to FIG. 2, a notch is provided in the width direction of the bus bar 2. It is also possible to combine FIG. 2 and FIG. 3, and in this case, it is considered that the effect is great both in reducing the loop length and shortening the length of the bonding wire 5. 2 and 3, some of the bonding wires 5 and 6 are omitted.

【００１５】図１〜３におけるワイヤボンディング後、
ワイヤ５、バスバー２間に接着剤をポッティングし、ワ
イヤ５を固定することによってワイヤ５のショートを防
止することができる。After wire bonding in FIGS.
By shorting the wire 5 by potting an adhesive between the wire 5 and the bus bar 2 and fixing the wire 5.

【００１６】本発明において、リードフレーム１は材
質、ピン数等について特に限定されない。また、半導体
チップ４および電源用のバスバー２を固定している接着
剤付絶縁部材（フィルム３）の形状、材質も特に限定さ
れない。In the present invention, the lead frame 1 is not particularly limited in material, number of pins and the like. Further, the shape and material of the insulating member with adhesive (film 3) fixing the semiconductor chip 4 and the bus bar 2 for power supply are not particularly limited.

【００１７】[0017]

【発明の効果】本発明は以上説明したように構成されて
いるので、バスバー横断部のワイヤとバスバーとの絶縁
距離が確保されるため、ワイヤショートに対して信頼性
が向上する。Since the present invention is configured as described above, the insulation distance between the wire at the bus bar crossing portion and the bus bar is secured, so that the reliability against wire short circuit is improved.

【００１８】また、バスバー横断部のワイヤ高さを低く
することができるのでパッケージの厚さを薄くすること
ができる。Further, since the height of the wire across the bus bar can be reduced, the thickness of the package can be reduced.

【図面の簡単な説明】[Brief description of drawings]

【図１】 本発明の一実施例を示すバスバー近傍の斜視
図である。FIG. 1 is a perspective view near a bus bar showing an embodiment of the present invention.

【図２】 本発明の他の実施例を示すバスバー近傍の斜
視図である。FIG. 2 is a perspective view of the vicinity of a bus bar showing another embodiment of the present invention.

【図３】 本発明の他の実施例を示すバスバー近傍の斜
視図である。FIG. 3 is a perspective view showing the vicinity of a bus bar according to another embodiment of the present invention.

【図４】 従来のＴＳＯＰパッケージの要部を示す斜視
図である。FIG. 4 is a perspective view showing a main part of a conventional TSOP package.

【図５】 従来のＬＯＣ構造を示す断面図である。FIG. 5 is a cross-sectional view showing a conventional LOC structure.

【図６】 図４においてボンディングワイヤの一部を省
略した部分斜視図である。6 is a partial perspective view of the bonding wire in FIG. 4 with a part thereof omitted.

【符号の説明】[Explanation of symbols]

１ リードフレーム １ａ インナーリード部 ２ バスバー ３ フィルム（両面接着剤付） ４ シリコンチップ ４ａ パッド ５ ボンディングワイヤ ６ ボンディングワイヤ 1 lead frame 1a inner lead part 2 bus bar 3 film (with adhesive on both sides) 4 silicon chip 4a pad 5 bonding wire 6 bonding wire

フロントページの続き (72)発明者 杉 本 洋 茨城県土浦市木田余町3550番地 日立電線 株式会社金属研究所内 (72)発明者 高 坂 博 之 茨城県土浦市木田余町3550番地 日立電線 株式会社金属研究所内 (72)発明者 坂 東 良 則 茨城県日立市助川町３丁目１番１号 日立 電線株式会社電線工場内 (72)発明者 安 生 一 郎 東京都小平市上水本町５丁目20番１号 株 式会社日立製作所武蔵工場内 (72)発明者 有 田 順 一 東京都小平市上水本町５丁目20番１号 株 式会社日立製作所武蔵工場内Front page continued (72) Inventor Hiroshi Sugimoto 3550 Kidayomachi, Tsuchiura City, Ibaraki Prefecture Hitachi Cable Ltd. (72) Inventor Hiroyuki Takasaka 3550 Kidayomachi, Tsuchiura City, Ibaraki Hitachi Cable Ltd. Inside the Metals Research Institute (72) Inventor Yoshinori Bando 3-1-1 Sukegawa-cho, Hitachi City, Ibaraki Hitachi Cable Co., Ltd. Electric Wire Factory (72) Inventor Ichiro Yasu 5-20, Kamimizumoto-cho, Kodaira-shi, Tokyo No. 1 Incorporated company Hitachi, Ltd. Musashi factory (72) Inventor Junichi Arita 5-20-1 Kamimizuhonmachi, Kodaira-shi, Tokyo Incorporated company Hitachi Ltd. Musashi factory

Claims (1)

【特許請求の範囲】[Claims] 【請求項１】リードフレームのインナーリード部が半導
体チップ上に絶縁部材を介して固定されるとともに、前
記インナーリード部の先端方向のさらに前方に離間して
電源用のバスバーが配設され絶縁部材を介して前記チッ
プ上に固定され、それぞれボンディングワイヤで配線し
てなる半導体装置において、前記バスバーの少なくとも
ボンディングワイヤ横断部と対向する部分を切欠きまた
は薄肉としたことを特徴とする半導体装置。1. An insulating member in which an inner lead portion of a lead frame is fixed on a semiconductor chip via an insulating member, and a bus bar for a power source is arranged further away from the front end direction of the inner lead portion. A semiconductor device fixed on the chip via the wirings and wired with bonding wires respectively, wherein at least a portion of the bus bar facing the crossing portion of the bonding wires is notched or thin.
JP3812692A 1992-02-25 1992-02-25 Semiconductor device Pending JPH05235075A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3812692A JPH05235075A (en) 1992-02-25 1992-02-25 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3812692A JPH05235075A (en) 1992-02-25 1992-02-25 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH05235075A true JPH05235075A (en) 1993-09-10

Family

ID=12516764

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3812692A Pending JPH05235075A (en) 1992-02-25 1992-02-25 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH05235075A (en)

Similar Documents

Publication Publication Date Title
JP3118167B2 (en) Electronic package and manufacturing method thereof
US6459148B1 (en) QFN semiconductor package
JPH06105721B2 (en) Semiconductor device
US7098527B2 (en) Integrated circuit package electrical enhancement with improved lead frame design
JPH05235075A (en) Semiconductor device
JP2716405B2 (en) Semiconductor device and manufacturing method thereof
JPH0529528A (en) Semiconductor integrated circuit device and lead frame used for same
JP3055581B2 (en) Semiconductor device
JP3702152B2 (en) Semiconductor device
JP2968769B2 (en) Resin-sealed semiconductor device
JP2869596B2 (en) Resin-sealed semiconductor device
JP2001332684A (en) Resin-sealed semiconductor device and manufacturing method thereof
JP2629461B2 (en) Resin-sealed semiconductor device
JPH07335818A (en) Semiconductor device
KR0142756B1 (en) Loc package
KR100245258B1 (en) Lead on chip lead frame for down set inner lead
JP3179374B2 (en) Lead frame for semiconductor device and semiconductor device
JPH08227903A (en) Semiconductor device
JPH09246454A (en) Semiconductor device
JP2563507Y2 (en) Semiconductor device
JP2595908B2 (en) Semiconductor device
JPH10125850A (en) Lead frame, semiconductor device and manufacturing method thereof
JP2577880B2 (en) Semiconductor device
KR200169520Y1 (en) Leadframe of semiconductor package
KR200149156Y1 (en) Leadframe

Legal Events

Date Code Title Description
A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20000425