JP2563507Y2 - Semiconductor device - Google Patents

Description

[Detailed description of the invention]

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a LOC type (lead frame on chip) semiconductor device.
The present invention relates to a semiconductor device in which a loop of a bonding wire is formed low to prevent occurrence of a molding defect in resin sealing.

[0002]

2. Description of the Related Art In recent years, in semiconductor devices, the size of a semiconductor chip has been increasing with the increase in the degree of integration and capacity of semiconductor elements, but the resin sealing size has tended to be small and the mounting density has been increasing. Accordingly, this type of semiconductor device is disclosed in Japanese Patent Application Laid-Open No. 61-241959, in which an electrically insulating insulating tape having a large number of leads provided with adhesives on both surfaces is provided on a circuit forming surface of a semiconductor chip. One end of the bonding wire is connected to the electrode terminal pad of the semiconductor chip, and the other end is connected to the lead to form an electrical conduction circuit, and these are sealed with a resin member. has been adopted as of seals was LOC (Lead on Chip) structure.

According to this semiconductor device, since the leads can be freely routed to the electrode terminal pads of the semiconductor chip without being restricted by the shape of the semiconductor chip, a large-sized semiconductor chip can be sealed. However, in this kind of technology, when the insulating tape is bonded to the circuit surface area of the semiconductor chip, there is a problem that the circuit surface area of the semiconductor chip is damaged, and when the insulating tape is crimped and connected to the wire bonding area of the lead. In addition, there has been a problem that an impact load or a compression load is applied to the circuit surface area of the semiconductor chip to damage the circuit surface area of the semiconductor chip.

Therefore, in order to solve the above problems,
To disposed in a state in which a plurality of lead group of the lead frame body is lifted above the circuit surface area face of the semiconductor chip, the lead frame of the semiconductor chip mounting cage configured separately mounted with the semiconductor chip One end of the lead group is connected to an electrode terminal pad of the semiconductor chip with a bonding wire interposed therebetween to form an electrical conduction circuit, and the semiconductor chip and the lead are provided on the lower surface side of the main body. A semiconductor device having a structure in which one end side of a group is sealed with a mold resin has been proposed.

However, in the proposed prior art semiconductor device, a plurality of lead groups having a common lead (bus bar lead) are provided in a state of being floated on the circuit forming surface of the semiconductor chip, so that a wire bonding is required. wherein since the wire bonding over a shared lead, wire
It is necessary to form a high bonding loop, and there are economical and structural problems such as an increase in the amount of bonding wires used and an increase in the thickness of the resin sealing portion .

Further, the tip portion of the lead group connected to the semiconductor chip of the electrode terminal pad <br/> becomes a free end, before
Wire bonding position occurs more or ups and downs of the serial lead groups each other becomes unstable, there is a problem that reduces the efficiency of the wire bonding operation.

An object of the present invention is to provide a semiconductor device which is arranged in a state in which a plurality of lead groups are separated from each other on the circuit forming surface of the semiconductor chip, an electrical continuity circuit by connecting the lead groups and said semiconductor chip An object of the present invention is to provide a semiconductor device which prevents molding defects such as a flow phenomenon of a bonding wire used in the construction and has excellent long-term reliability of the semiconductor device.

Another object of the present invention is to provide a semiconductor device in which the leading end of a lead group is prevented from being shifted or raised and lowered, thereby improving the efficiency of wire bonding work and improving the economic efficiency.

According to a first aspect of the present invention, there is provided a semiconductor device including a common lead (bus bar lead) on a circuit forming surface side of a semiconductor chip and near an electrode terminal of the semiconductor chip. A support lead having a lead frame main body on which a plurality of lead groups are provided, a semiconductor chip mounting portion on the lower surface of the lead frame main body, and a down-set in the center parallel to the lead frame main body, and a bent portion connected to the semiconductor chip mounting portion Doo and the semiconductor chip mounting cage, which is formed separately from a conductive or non-conductive member provided with, is mounted on the semiconductor chip mounting cage, a semiconductor chip having a plurality of electrode terminal pad on the inner surface area, one end In front of the department
The other ends of the electrode terminal pads of the semiconductor chip and the corresponding leads of the lead frame and the bus bar
Bondin connecting to leads to form an electrical conduction circuit
Wire , one end side of the lead group, a semiconductor chip,
In the semiconductor device configured by including the bonding wires and the semiconductor chip molded resin portion mounted cage and the resin sealing, the side edge portions of the shared lead (bus bar leads), the required corresponding to the electrode terminal pads of the semiconductor chip A plurality of wire bonding tabs, and a wire bonding tab of the common lead (bus bar lead ) .
Lead and one end on the top side of the lead group so that the wire bonding area at the tip of each lead is exposed.
An insulating layer is provided in which the unit sides are collectively connected.

[0010]

In the semiconductor device according to the first aspect of the present invention, a required number of wire bonding tabs corresponding to the electrode terminal pads of the semiconductor chip are arranged on the side edges of the common lead (bus bar lead). In addition, the common lead (bus bar lead) and a predetermined portion on the upper surface of the lead group are provided with an insulating layer for connecting them collectively so that the wire bonding region at the tip of each lead is exposed. As compared with the case where the wire bonding region is exposed by removing the insulating layer of the required portion of the common lead, it is not necessary to remove the insulating layer of the portion of the common lead, and the work of forming the insulating layer becomes easier. .

[0011] Further, the length of the bonding wire can be shortened because the formation of an electrical conduction circuit between the electrode terminal pad of the semiconductor chip and the common lead can be connected via a wire bonding tab. It is possible,
The formation of an electrical conduction circuit between the electrode terminal pads of the semiconductor chip and the common leads is simplified.

[0012] Further, when performing wire bonding for connecting the lead group and the semiconductor chip, the upper surface of the common lead is coated with an insulating layer, a common lead and the electrode terminal pads of the lead group and semiconductor chips When connecting beyond, it is possible to prevent the bonding wire from directly contacting the common lead. As a result, the loop height of the bonding wire can be reduced.

Furthermore, a predetermined portion of an upper surface of said shared lead (bus bar leads) and lead group, these because they provided an insulating layer of collectively connecting, the less deviation and ups and downs of the tip portion of the lead group, wire The bonding region is stabilized, and the bondability can be improved.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The details of the present invention will be described below with reference to the accompanying drawings. FIG. 1 is a sectional view showing an outline of an embodiment of the semiconductor device according to the present invention. FIG. 2 is a plan view showing an outline of a lead frame body used in the embodiment shown in FIG.
FIG. 3 is a perspective view showing a state where a semiconductor chip is mounted on a semiconductor chip mounting cage used in an embodiment of the semiconductor device of the present invention.

Next, the semiconductor device of the present invention (LOC type)
As shown in FIG. 1, a semiconductor chip 11 in which a plurality of signal, power, and ground electrode terminal pads are arranged at predetermined positions in an internal surface area, and a signal lead 12 and a common power supply or ground. And lead groups A and B having leads 12a and 12b. The common lead (bus bar lead) has a side edge portion corresponding to a power supply or ground electrode terminal pad of the semiconductor chip. It is provided with a number of wire bonding tabs 12c and 12d. The common leads 12a and 12b and the lead groups A and B are so exposed that the wire bonding tabs 12c and 12d and the wire bonding area 20 provided at the tip of the lead 12 are exposed.
FIG. 5 shows a lead frame main body 16 in which a predetermined portion of the upper surface of the lead is integrally connected and covered with a bonding tape 13c in which an adhesive 13b is applied to an insulating resin tape 13a which is an example of the insulating layer 13. As described above, a part of the leads 12 of the lead groups A and B of the lead frame body 16 and the common leads 12a and 12b extend near electrode terminal pads provided on the inner surface side of the semiconductor chip 11, and extend from the semiconductor chip. The semiconductor chip mounting portion 18 on which the semiconductor chip 11 is mounted and the bent portions 1 connected to both end surfaces of the semiconductor chip mounting portion 18 so as to be connected in a separated state.
The semiconductor chip mounting cage 14 which is separately formed using a conductive material provided with the support lead 15 having the core 5a is used as a constituent member .

[0016] Thus, the bonding wire does not come into direct contact with the common lead, thereby reducing the loop of the bonding wire. Is stable and bondability can be improved.

Here, the wire bonding tab 1
2c, 12d and an insulating layer 1 covering a predetermined area except the wire bonding area on the upper surface of the lead of the lead group A, B
As an example of 3, an insulating resin tape 13a and an adhesive 13b
The insulating resin tape 13a is connected and covered with a joining tape 17a in which the insulating resin tape 13a is replaced with a non-conductive tape (for example, a thin alumina plate material) 17. (FIGS. 3A and 3B)
(See Reference) The same effect can be obtained, and a member that improves the heat diffusion efficiency can be selected, so that the degree of freedom in design can be improved.

The semiconductor chip mounting cage 14
The semiconductor chip 11 is mounted and fixed on the semiconductor chip mounting portion 18 of the above, and this is mounted via an adhesive so as to be positioned on the lower surface side of the lead frame main body 16. One end of the bonding wire 19 is connected to the semiconductor chip. And the other ends of the leads 12 of the lead groups A and B
Exposed wire bonding area 20 or wire bonding tabs 12c, 1b of common leads 12a, 12b.
2d is selectively connected to form an electrical conduction circuit.

The semiconductor chip 11, the semiconductor chip mounting cage 14, and one end of the lead groups A and B on the wire bonding area side are resin-sealed, and unnecessary portions of the leads exposed from the resin sealing portion 21 are removed. The semiconductor device is formed by forming the leads into a predetermined shape.

The embodiment of the present invention has been described above. The feature of the present invention is that the common terminal (bus bar lead) and the electrode terminal pads of the semiconductor chip are provided on the upper surfaces of the lead groups A and B. An insulating layer is provided so as to expose a required number of wire bonding tabs 12c and 12d corresponding to a wire bonding region for forming a typical conductive circuit and a power supply or ground electrode terminal pad , thereby lowering the bonding wire loop. That is, the configuration is formed. Therefore, the present invention is not limited to this embodiment, and it is needless to say that various modifications can be made without departing from the scope of the invention.

[0021]

According to the semiconductor device of the first aspect,
A wire bonding tab is provided on the side edge of the
The area near the wire bonding area at the tip of the
Semiconductor device with excellent long-term reliability
Can be provided at low cost.

[Brief description of the drawings]

FIG. 1 is a sectional view showing an outline of a semiconductor device as an example of an embodiment of the present invention.

FIG. 2 is a plan view showing an outline of a lead frame main body used for a semiconductor device which is an example of an embodiment of the present invention.

FIG. 3 is a perspective view showing a state in which a semiconductor chip is mounted on a semiconductor chip mounting cage used in a semiconductor device according to an embodiment of the present invention;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Semiconductor device 11 Semiconductor chip 12 Signal lead 12a Common lead for power supply 12b Common lead for ground 12c Tab for wire bonding 12d Tab for wire bonding 13 Insulating layer 13a Insulating resin tape 13b Adhesive 13c Joining tape 14 Semiconductor chip mounting Cage 15 Support lead 15a Bend 16 Lead frame main body 17 Non-conductive tape 17a Bonding tape 18 Semiconductor chip mounting part 19 Bonding wire 20 Wire bonding area 20a Wire bonding area 21 Resin sealing part A Lead group B Lead group

Claims (1)

(57) [Scope of request for utility model registration] 1. A method according to claim 1, further comprising the step of:
A lead frame main body in which a plurality of lead groups including a common lead (bus bar lead) are disposed so as to be located in the vicinity of the electrode terminal of the semiconductor chip; A semiconductor chip mounting cage formed separately from a conductive or non-conductive member having a semiconductor chip mounting portion downset in parallel with a support lead having a bent portion connected thereto,
It is mounted on the semiconductor chip mounting cage, a semiconductor chip having a plurality of electrode terminal pad on the inner surface area, one end
The electrode terminal pads of the semiconductor chip, the leads and the bus of the lead frame corresponding to the other end to
Bond that connects to bar leads to form an electrical conduction circuit
And Inguwaiya, one end of the lead group, a semiconductor chip, a semiconductor device which is configured by including the bonding wires and the semiconductor chip mounting cage and the resin sealing mold resin portion, the side of the shared lead (bus bar leads) the edge, provided with a required number of wire bonding tab corresponding to the electrode terminal pads of the semiconductor chip, the common lead wire
The common lead and lead are so exposed that the wire bonding area at the tip of each
A semiconductor device provided with an insulating layer integrally connecting one end side of the upper surface side of the gate group .