JPH05218606A - Circuit device - Google Patents

Circuit device

Info

Publication number
JPH05218606A
JPH05218606A JP4256389A JP25638992A JPH05218606A JP H05218606 A JPH05218606 A JP H05218606A JP 4256389 A JP4256389 A JP 4256389A JP 25638992 A JP25638992 A JP 25638992A JP H05218606 A JPH05218606 A JP H05218606A
Authority
JP
Japan
Prior art keywords
conductive layer
base material
metal base
insulating layer
heat
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP4256389A
Other languages
Japanese (ja)
Other versions
JPH07123186B2 (en
Inventor
Koichi Koga
公一 古賀
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Electric Works Co Ltd
Original Assignee
Matsushita Electric Works Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Works Ltd filed Critical Matsushita Electric Works Ltd
Priority to JP4256389A priority Critical patent/JPH07123186B2/en
Publication of JPH05218606A publication Critical patent/JPH05218606A/en
Publication of JPH07123186B2 publication Critical patent/JPH07123186B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144Gold (Au) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1306Field-effect transistor [FET]
    • H01L2924/13091Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]

Landscapes

  • Insulated Metal Substrates For Printed Circuits (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

PURPOSE:To dissipate heat from a highly heat-generating component with good efficiency by providing the following: an insulating layer in which a window part has been formed; a two-layer conductive layer formed on the insulating layer; and the highly heat-generating component on a metal base material which has been exposed. CONSTITUTION:Window parts 44 which partly expose the surface of a metal base material 11 are formed in an insulating layer 12 which has been pasted on the metal base material 11. In addition, a conductive layer 34 which is composed of at least two layers is formed on the insulating layer 12. A highly heat-generating component (a semiconductor chip) 15 is arranged on the metal base material 11; it is connected to the conductive layer 34. As a result, the highly heat-generating component 15 is pasted directly on the metal base material 11, and a heat sink and the like are not required. Thereby, heat from the highly heat-generating component can be dissipated with good efficiency.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明はパワー用半導体チップ等
の高発熱部品を含む回路を金属基材をベースとする回路
基板上に形成してなる回路装置に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit device in which a circuit including a high heat generating component such as a power semiconductor chip is formed on a circuit board based on a metal base material.

【0002】[0002]

【従来の技術】従来、パワー用半導体チップを実装した
パワー用の回路装置はその動作中に発生する熱の放散を
考慮して所謂ヒートシンクを使用する方式が採用される
ことが多い。このようなヒートシンクを使用する方式の
例として示したのが図8、図9に示す回路装置である。
高発熱部品が実装される金属基材をベースとする回路装
置は図8および図9に示すように、銅、アルミニウム等
の金属基材11の上に絶縁層212を介して導電層21
3を形成したものが使用されている。前記絶縁層212
にはエポキシ系の樹脂が使用されている。導電層213
は銅箔を貼り付けたものをエッチングしてパターン状に
回路を形成するもの、あるいは真空蒸着、スパッタリン
グ等で形成する方法がある。
2. Description of the Related Art Conventionally, a power circuit device mounted with a power semiconductor chip often employs a so-called heat sink in consideration of dissipation of heat generated during its operation. The circuit device shown in FIGS. 8 and 9 is shown as an example of a system using such a heat sink.
As shown in FIGS. 8 and 9, a circuit device based on a metal base material on which high heat-generating components are mounted has a conductive layer 21 on a metal base material 11 such as copper or aluminum via an insulating layer 212.
What formed 3 is used. The insulating layer 212
An epoxy resin is used for this. Conductive layer 213
There is a method of forming a circuit in a pattern by etching a copper foil attached, or a method of forming the circuit by vacuum deposition, sputtering or the like.

【0003】この導電層213の必要箇所に銅材ででき
たヒートシンクとなる金属ブロック14が取り付けられ
る。金属ブロック14の上にはパワー用の半導体チップ
等の高発熱部品15が取り付けられる。このように高発
熱部品15が半導体チップの場合、金属ブロック14へ
の接着には半田付けを使用することが多い。金属ブロッ
ク14の大きさは発熱部品15と同程度から数倍くらい
の大きさであり、厚みは0.5mm〜3mmのものが使用されて
いる。パワー用の半導体チップとしては例示のパワーM
OS−FETの他、パワートランジスタ、トライアッ
ク、SCR、ダイオード等がある。高発熱部品15用ボ
ンディングワイヤ16には金線、アルミニウム線、銅線
等が使用されチップと導電層213を接続するものであ
る。
A metal block 14 made of a copper material and serving as a heat sink is attached to a necessary portion of the conductive layer 213. A high heat-generating component 15 such as a power semiconductor chip is mounted on the metal block 14. When the high heat-generating component 15 is a semiconductor chip as described above, soldering is often used for bonding to the metal block 14. The size of the metal block 14 is about the same as that of the heat generating component 15 or several times, and the thickness thereof is 0.5 mm to 3 mm. An example power M is used as a power semiconductor chip.
Besides the OS-FET, there are power transistors, triacs, SCRs, diodes and the like. A gold wire, an aluminum wire, a copper wire, or the like is used as the bonding wire 16 for the high heat-generating component 15, and connects the chip and the conductive layer 213.

【0004】次に、回路例の動作を図7に基づき説明す
る。図7に示すように、回路は三相ブリッジ回路であ
る。電流iは回路の一方の入力端子18から半導体チッ
プ15へ流れ、出力端子28を通り負荷(図示せず)へ
流れる。負荷を通った電流は別の出力端子28に戻り、
別の半導体チップ15を通り、もう一方の入力端子18
に流れる。この場合の負荷はモータである。電流の大き
さはモータの負荷状態により変わる。最も大きい負荷は
モータの回転がロックされたようなときである。このと
きは電流が急激に増大し、半導体チップ15の発熱も急
激に増える。この発熱による熱はすぐ金属ブロック14
に伝えられ、半導体チップ15の温度上昇がおさえられ
る。金属ブロック14に伝えられた熱は絶縁層212を
介して金属基材11へ放熱される。
Next, the operation of the circuit example will be described with reference to FIG. As shown in FIG. 7, the circuit is a three-phase bridge circuit. The current i flows from one of the input terminals 18 of the circuit to the semiconductor chip 15 and through the output terminal 28 to a load (not shown). The current passing through the load returns to another output terminal 28,
The other input terminal 18 is passed through another semiconductor chip 15.
Flow to. The load in this case is the motor. The magnitude of the current depends on the load condition of the motor. The largest load is when the rotation of the motor seems to be locked. At this time, the current rapidly increases and the heat generation of the semiconductor chip 15 also rapidly increases. The heat generated by this heat is immediately transferred to the metal block 14
The temperature rise of the semiconductor chip 15 is suppressed. The heat transferred to the metal block 14 is radiated to the metal base material 11 via the insulating layer 212.

【0005】又、このような高発熱部品15を含む回路
においては、高発熱部品15からの発熱を放熱するのに
絶縁層212の熱伝導度の大小がその性能を左右する。
ここに示すような例においては、絶縁層212は樹脂あ
るいはセラミックを主成分とするものであり、金属と比
較するとその熱伝導度は小さい。
Further, in a circuit including such a high heat-generating component 15, the performance of the insulating layer 212 is large and small in radiating the heat generated from the high heat-generating component 15.
In the example shown here, the insulating layer 212 is mainly made of resin or ceramic, and its thermal conductivity is smaller than that of metal.

【0006】[0006]

【発明が解決しようとする課題】このような従来例の課
題として、瞬間的な発熱に対してはそれを金属ブロック
14の温度上昇により吸収することができるが、金属ブ
ロック14そのものは短時間で温度上昇してしまう。そ
の後の高発熱部品(半導体チップ)15からの放熱は、
絶縁層212を介しての金属基材11への熱伝導が律速
になる。従って、発熱が瞬時で終わらないようなもので
は絶縁層212を介しての放熱をいかに良くするかの工
夫が必要である。
As a problem of such a conventional example, it is possible to absorb momentary heat generation by increasing the temperature of the metal block 14, but the metal block 14 itself can be absorbed in a short time. The temperature will rise. After that, the heat radiation from the high heat generating component (semiconductor chip) 15
The heat conduction to the metal base material 11 via the insulating layer 212 is rate-determining. Therefore, it is necessary to devise how to improve the heat radiation through the insulating layer 212 in the case where the heat generation does not end instantly.

【0007】上記従来例における高発熱部品15は複数
個(例として6個)ありどれも同じ発熱量のものであ
る。しかし、一般にはそれぞれに異なった発熱量になる
場合がある。その場合、金属ブロック14の大きさをそ
れぞれに変えるべきである。しかし現実には部品の種類
が多くなり、部品管理、設備対応が大変であり、細かな
対応ができない。本発明は上記問題点の解決をし、連続
的に発熱が続くような回路装置でで放熱性のよい金属基
材をベースとする回路装置を提供することを目的とする
ものである。
There are a plurality (six as an example) of the high heat-generating components 15 in the above conventional example, and all have the same amount of heat generation. However, in general, the calorific value may be different for each. In that case, the size of the metal block 14 should be changed respectively. However, in reality, there are many types of parts, and it is difficult to manage parts and support equipment, so it is not possible to make detailed correspondences. SUMMARY OF THE INVENTION It is an object of the present invention to solve the above problems and provide a circuit device in which heat is continuously generated and which is based on a metal base material having good heat dissipation.

【0008】[0008]

【課題を解決するための手段】本発明は上記目的を達成
するため以下のような手段を有するものである。
The present invention has the following means in order to achieve the above object.

【0009】特許請求の範囲第1項に示すように、金属
基材と、前記金属基材上に貼り付けられ且つ前記金属基
材表面を部分的に露出させる窓明き部が設けられた絶縁
層と、前記絶縁層上に形成された少なくとも2層からな
る導電層と、前記窓明き部で部分的に露出した前記金属
基材上に配され前記導電層と接続された高発熱部品とを
備えた回路装置としたことを特徴とする。
Insulation provided with a metal base material and a window opening part which is stuck on the metal base material and partially exposes the surface of the metal base material, as described in claim 1. A layer, a conductive layer composed of at least two layers formed on the insulating layer, and a high heat-generating component arranged on the metal base material partially exposed at the window opening and connected to the conductive layer. It is characterized in that it is a circuit device provided with.

【0010】[0010]

【作用】特許請求の範囲第1項に示すように、金属基材
と、前記金属基材上に貼り付けられ且つ前記金属基材表
面を部分的に露出させる窓明き部が設けられた絶縁層
と、前記絶縁層上に形成された少なくとも2層からなる
導電層と、前記窓明き部で部分的に露出した前記金属基
材上に固着され前記導電層と接続された高発熱部品とを
備えた回路装置としたことにより、高発熱部品(半導体
チップ)を金属基材上に直接貼り付けるようになり高発
熱部品(半導体チップ)からの放熱が効率良く行われ
る。実施例におけるような複数の高発熱部品(半導体チ
ップ)がある場合は同電位となる高発熱部品(半導体チ
ップ)のみを金属基材上に直接貼着するようにする。
又、発熱量の違う複数の高発熱部品(半導体チップ)を
実装する場合は最も発熱量の大きい高発熱部品(半導体
チップ)を金属基材上に直接貼り付けるようにすればよ
り効率的に放熱を行なうことができる。
Insulation provided with a metal base material and a window opening part which is attached to the metal base material and partially exposes the surface of the metal base material, as described in claim 1. A layer, a conductive layer composed of at least two layers formed on the insulating layer, and a high heat-generating component fixedly connected to the metal base material partially exposed at the window opening part and connected to the conductive layer. By using the circuit device having the above, the high heat generating component (semiconductor chip) can be directly attached onto the metal base material, and the heat radiation from the high heat generating component (semiconductor chip) is efficiently performed. When there are a plurality of high heat generating components (semiconductor chips) as in the embodiment, only the high heat generating components (semiconductor chips) having the same potential are directly attached to the metal base material.
Also, when mounting multiple high heat-generating components (semiconductor chips) that generate different amounts of heat, if the high heat-generating components (semiconductor chips) with the highest heat generation are directly attached to the metal substrate, heat can be dissipated more efficiently. Can be done.

【0011】[0011]

【実施例】以下、本発明の回路装置の第一の実施例につ
き図5を参照し、詳細に説明する。図5において11は
銅、アルミニウムといった良熱伝導性金属基材である。
この金属基材11の上に第一の絶縁層12を形成する。
この第一の絶縁層12は例えばエポキシ樹脂あるいはエ
ポキシ樹脂を含浸したガラス繊維であり、ロールコータ
ー、フローコーター等での塗布法、スクリーン印刷法あ
るいはシート状プリプレグの貼り付け法等により形成す
る。この第一の絶縁層12の形成の際に、部分的に絶縁
層のない窓明き部44を形成する。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the circuit device of the present invention will be described in detail below with reference to FIG. In FIG. 5, 11 is a metal base material having good thermal conductivity such as copper or aluminum.
The first insulating layer 12 is formed on the metal base 11.
The first insulating layer 12 is, for example, epoxy resin or glass fiber impregnated with epoxy resin, and is formed by a coating method such as a roll coater or a flow coater, a screen printing method, or a sheet-like prepreg attaching method. At the time of forming the first insulating layer 12, the window opening portion 44 partially having no insulating layer is formed.

【0012】この第一の絶縁層12の上に銅等からなる
第一の導電層34を形成する。この第一の導電層34の
形成方法としては、パターン状に銅箔を打ち抜いたもの
を貼り付ける方法、全面に銅箔を貼り付けエッチングに
よりパターンを形成する方法、あるいはステンレス板等
の上に図5のようなパターンの電気銅めっきを行い、第
一の絶縁層12上に転写、貼り付ける方法等がある。こ
の第一の導電層34として上記の方法により、厚みが
0.03mm程度から3mm程度まで任意のものを作る
ことができる。この中で銅の厚みの薄いものは前記エッ
チングまたは電気めっきをして転写する方法により形成
する。
A first conductive layer 34 made of copper or the like is formed on the first insulating layer 12. The method of forming the first conductive layer 34 includes a method of sticking a copper foil punched in a pattern, a method of sticking a copper foil on the entire surface and forming a pattern by etching, or a method of forming a pattern on a stainless plate or the like. There is a method of performing electrolytic copper plating of a pattern like No. 5 and transferring or pasting it onto the first insulating layer 12. As the first conductive layer 34, an arbitrary layer having a thickness of about 0.03 mm to about 3 mm can be manufactured by the above method. Among them, the thin copper is formed by the above-mentioned etching or electroplating method and transferring.

【0013】この図5、図1および図2の実施例は図7
の回路での本発明の実施例である。この回路で6個のパ
ワーMOS−FET15は均等な発熱をする。図5で部
分的に絶縁層のない窓明き部44で露出した金属基材1
1の上に3個のパワーMOS−FETを実装し、同じく
第一の導電層34の上にはそれぞれ1個のパワーMOS
−FETを実装する。分離した第一の導電層34はそれ
ぞれが等しい面積となるようにパターンを設計する。一
般の回路にも適応できる表現にすると、発熱部品の発熱
量に応じて第一の導電層のそれぞれの面積を変えるよう
にする。
The embodiment shown in FIGS. 5, 1 and 2 is shown in FIG.
2 is an embodiment of the present invention in the circuit of FIG. In this circuit, the six power MOS-FETs 15 generate heat evenly. In FIG. 5, the metal substrate 1 partially exposed at the window opening portion 44 having no insulating layer
1 has three power MOS-FETs mounted on it, and one power MOS on each first conductive layer 34.
Implement the FET. The patterns are designed so that the separated first conductive layers 34 have the same area. In terms of expression applicable to a general circuit, each area of the first conductive layer is changed according to the heat generation amount of the heat generating component.

【0014】この後、第一の導電層34のパターン間お
よび基板端部、つまり図5の銅箔のない部分19に樹脂
を塗布し、表面の段差を極力なくすようにする。樹脂材
料は第一の絶縁層12と同じエポキシ樹脂である。塗布
にはディスペンサーまたはスクリーン印刷法を用いる。
このようにして、ほぼ段差のない状態にし、その上に図
1に示すように第二の絶縁層22を形成する。形成方法
はスクリーン印刷法であり、材料はエポキシ樹脂であ
る。
Thereafter, a resin is applied between the patterns of the first conductive layer 34 and at the end portions of the substrate, that is, in the portion 19 without the copper foil in FIG. 5, so as to eliminate the surface step as much as possible. The resin material is the same epoxy resin as the first insulating layer 12. A dispenser or a screen printing method is used for coating.
In this way, a state having almost no step is formed, and the second insulating layer 22 is formed thereon as shown in FIG. The forming method is a screen printing method, and the material is an epoxy resin.

【0015】この第二の絶縁層22の印刷の際に、金属
基材11または第一の導電層34を部分的に露出させる
ような絶縁層のない窓明き部54、64、74、84を
形成する。これらの窓明き部54、64、74、84の
うち54、64はは高発熱部品(半導体チップ)15が
取り付けられる窓、74は外部引出し端子の取り付けら
れる窓、84は半導体チップのワイヤボンディングのた
めの窓である。図5の基板の上に第二の絶縁層22を形
成した図1の窓明き部54、64、74、84では、金
属基材11または第一の導電層34が部分的に露出する
構造となる。
When the second insulating layer 22 is printed, the window openings 54, 64, 74, 84 having no insulating layer that partially exposes the metal substrate 11 or the first conductive layer 34. To form. Of these window opening parts 54, 64, 74, 84, 54 and 64 are windows to which the high heat generating component (semiconductor chip) 15 is attached, 74 is a window to which an external lead terminal is attached, and 84 is wire bonding of the semiconductor chip. For windows. In the window opening portions 54, 64, 74 and 84 of FIG. 1 in which the second insulating layer 22 is formed on the substrate of FIG. 5, the metal base material 11 or the first conductive layer 34 is partially exposed. Becomes

【0016】この第二の絶縁層22の上に図2に示す第
二の導電層13を形成する。形成方法は第一の導電層3
4と同じ方法であり、パターン状に銅箔を打ち抜いたも
のを貼り付ける方法、全面に銅箔を貼り付けエッチング
によりパターンを形成する方法、あるいはステンレス板
等の上に所望のパターンの電気銅めっきを行い、第二の
絶縁層12上に転写、貼り付ける方法あるいはセミアデ
ィティブ法等を用いることができる。
A second conductive layer 13 shown in FIG. 2 is formed on the second insulating layer 22. The formation method is the first conductive layer 3
The method is the same as that of 4, and a method of sticking a punched copper foil in a pattern, a method of forming a pattern by sticking a copper foil on the entire surface and etching, or electrolytic copper plating of a desired pattern on a stainless plate or the like Then, a method of transferring and pasting onto the second insulating layer 12 or a semi-additive method can be used.

【0017】第二の導電層をセミアディティブ法により
作る場合の例を図4(A)に示す。図4(A)におい
て、第二の絶縁層22の表面を例えば液体ホーニングに
より粗面化し、この第二の絶縁層22の全面に無電解め
っきをする。図中23が無電解めっき(銅)であり厚み
は0.5μm 〜1μm である。この無電解めっき23は
第二の絶縁層22の窓明き部54、64、74、84に
も形成される。無電解めっき23上にめっきレジスト1
11を印刷し配線パターンを形成する。その後、電気銅
めっきにより第二の導電層33を形成する。
An example of forming the second conductive layer by the semi-additive method is shown in FIG. In FIG. 4A, the surface of the second insulating layer 22 is roughened by, for example, liquid honing, and the entire surface of the second insulating layer 22 is electroless plated. In the figure, 23 is electroless plating (copper) and has a thickness of 0.5 μm to 1 μm. The electroless plating 23 is also formed on the window opening portions 54, 64, 74, 84 of the second insulating layer 22. Plating resist 1 on electroless plating 23
11 is printed to form a wiring pattern. Then, the second conductive layer 33 is formed by electrolytic copper plating.

【0018】この後、めっきレジスト111を除去
し、、めっき表面の銅を短時間エッチングすることによ
り、露出した無電解銅めっき23は溶解してしまう。こ
のように第二の導電層33の形成と同時に第二の絶縁層
22の窓明き部を介して第一の導電層と第二の導電層3
3の接合も形成される。
After that, the plating resist 111 is removed and the copper on the plating surface is etched for a short time, whereby the exposed electroless copper plating 23 is dissolved. Thus, at the same time as the formation of the second conductive layer 33, the first conductive layer and the second conductive layer 3 are formed through the window opening of the second insulating layer 22.
A junction of 3 is also formed.

【0019】図4(B),(C)はこの上に更に、ボン
ディングのランド部の金めっき等の部分めっき43を行
なう方法を示した断面図である。めっきレジスト111
を除去する前の状態の図4(B)で、部分的にめっきを
したい所を残して再度めっきレジスト121を印刷し、
窓明きされた部分に電気めっき43を行う。この電気め
っき43が金めっきの場合、正確にはニッケルめっきを
した後、重ねて金めっきを行う。この後、めっきレジス
ト111、121を除去し、めっき表面の銅を短時間エ
ッチングすることにより、露出した無電解銅めっき23
は溶解してしまう。従って、最終図4(C)に示すよう
な構成となり、部分的なめっき43を有し、第一の導電
層34と連結した第二の導電層33を持った、回路基板
を形成することができる。第二の導電層を他の方法によ
り形成した場合にも第二の導電層の形成後、半導体チッ
プ等がボンディングされるボンディングのランド部に金
めっき等の部分めっきを行う。
FIGS. 4B and 4C are cross-sectional views showing a method of further performing partial plating 43 such as gold plating on the land portion for bonding on the above. Plating resist 111
4B in a state before the removal is performed, the plating resist 121 is printed again, leaving a portion where plating is desired,
Electroplating 43 is performed on the window exposed portion. When the electroplating 43 is gold plating, nickel plating is performed accurately, and then gold plating is performed again. After that, the plating resists 111 and 121 are removed and the copper on the plating surface is etched for a short time to expose the exposed electroless copper plating 23.
Will dissolve. Therefore, the final structure as shown in FIG. 4C can be obtained, and a circuit board having the partial plating 43 and the second conductive layer 33 connected to the first conductive layer 34 can be formed. it can. Even when the second conductive layer is formed by another method, after the formation of the second conductive layer, the land portion of the bonding to which the semiconductor chip or the like is bonded is subjected to partial plating such as gold plating.

【0020】金属基材11の上に半導体チップ15がボ
ンディングされた状態を断面図で示したのが図6であ
る。この半導体チップ15と第一の導電層34あるいは
第二の導電層13のボンディングのランド部との間でワ
イヤボンディングが行われる。図6ではボンディングワ
イヤ16により半導体チップ15と第二の導電層13と
の間でワイヤボンディングが行われている。一方、第一
の導電層34上に半導体チップ15がボンディングされ
た状態を断面図で示したのが図3である。このように半
導体チップ15と第一の導電層34の間にはヒートシン
ク等の金属を設ける必要がない。ワイヤボンディングは
半導体チップ15側のボンディングポイントを起点と
し、第一の導電層34または第二の導電層13のボンデ
ィングポイントを終点として行う。通常半導体チップ1
5は取り付け後、そのまわりをシリコン樹脂17で封止
する。これはチップの保護による信頼性確保を目的とし
たものである。
FIG. 6 is a sectional view showing a state in which the semiconductor chip 15 is bonded on the metal base material 11. Wire bonding is performed between the semiconductor chip 15 and the bonding land portion of the first conductive layer 34 or the second conductive layer 13. In FIG. 6, wire bonding is performed between the semiconductor chip 15 and the second conductive layer 13 by the bonding wire 16. On the other hand, FIG. 3 is a sectional view showing a state in which the semiconductor chip 15 is bonded on the first conductive layer 34. Thus, it is not necessary to provide a metal such as a heat sink between the semiconductor chip 15 and the first conductive layer 34. The wire bonding is performed starting from the bonding point on the side of the semiconductor chip 15 and ending at the bonding point of the first conductive layer 34 or the second conductive layer 13. Normal semiconductor chip 1
After mounting 5, the area 5 is sealed with a silicone resin 17. This is intended to ensure reliability by protecting the chip.

【0021】第一の導電層と第二の導電層との間の接続
の別の方法として、第一の導電層の部分的な窓明き部と
第二の導電層のボンディングのランド部の金めっき等の
電気めっき部を使って、ワイヤボンディングによって接
続した回路装置を形成することができる。
As an alternative method of connection between the first conductive layer and the second conductive layer, a partial window opening of the first conductive layer and a bonding land portion of the second conductive layer are formed. An electroplated portion such as gold plating can be used to form a circuit device connected by wire bonding.

【0022】[0022]

【発明の効果】これまで述べたような構成とすることに
より以下に述べる効果が得られる。
The following effects can be obtained by using the above-described structure.

【0023】特許請求の範囲第1項に示すように、金属
基材と、前記金属基材上に貼り付けられ且つ前記金属基
材表面を部分的に露出させる窓明き部が設けられた絶縁
層と、前記絶縁層上に形成された少なくとも2層からな
る導電層と、前記窓明き部で部分的に露出した前記金属
基材上に配され前記導電層と接続された高発熱部品とを
備えた回路装置としたことにより、高発熱部品(半導体
チップ)を金属基材上に直接貼り付けるようになりヒー
トシンク等が不要であり、高発熱部品(半導体チップ)
からの放熱が効率良く行われる。又、発熱量の違う複数
の高発熱部品(半導体チップ)を実装する場合は最も発
熱量の大きい高発熱部品(半導体チップ)を金属基材上
に直接貼り付けることで効率的放熱が可能となる。
Insulation provided with a metal base material and a window opening part which is attached to the metal base material and partially exposes the surface of the metal base material, as shown in claim 1. A layer, a conductive layer composed of at least two layers formed on the insulating layer, and a high heat-generating component arranged on the metal base material partially exposed at the window opening and connected to the conductive layer. By using the circuit device equipped with the high heat generating component (semiconductor chip), the heat generating component (semiconductor chip) can be directly attached onto the metal base material, and a heat sink or the like is not required.
The heat is efficiently dissipated. Further, when mounting a plurality of high heat-generating components (semiconductor chips) having different heat generation amounts, the high heat-generating component (semiconductor chip) having the largest heat generation amount can be directly adhered to the metal base material for efficient heat dissipation. ..

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の第一の実施例の回路装置を形成する途
中の工程で、第二の絶縁層を形成した段階での斜視図で
ある。
FIG. 1 is a perspective view at a stage where a second insulating layer is formed in the process of forming the circuit device according to the first embodiment of the present invention.

【図2】本発明の第一の実施例の回路装置を形成する途
中の工程で、第二の導電層を形成した段階での斜視図で
ある。
FIG. 2 is a perspective view at a stage where a second conductive layer is formed in a process in the middle of forming the circuit device according to the first embodiment of the present invention.

【図3】本発明の半導体チップ実装部を示す実施例で第
一の導電層に実装された半導体チップ実装部を示す拡大
断面図である。
FIG. 3 is an enlarged cross-sectional view showing a semiconductor chip mounting portion mounted on the first conductive layer in the embodiment showing the semiconductor chip mounting portion of the present invention.

【図4】(A)は本発明の異なった実施例の回路装置を
形成する途中の工程で、第二の導電層を形成した段階の
断面図、(B)は部分めっきを形成した段階の断面図、
(C)はその完成した金属基材をベースとする回路装置
の部分拡大断面図である。
FIG. 4A is a cross-sectional view of a step in which a second conductive layer is formed in the process of forming a circuit device according to another embodiment of the present invention, and FIG. 4B is a step of forming a partial plating. Cross section,
FIG. 3C is a partially enlarged cross-sectional view of the completed metal base-based circuit device.

【図5】本発明の第一の実施例の回路装置を形成する途
中の工程で、第一の導電層を形成した段階での斜視図で
ある。
FIG. 5 is a perspective view at a stage where a first conductive layer is formed in a process in the middle of forming the circuit device according to the first embodiment of the present invention.

【図6】本発明の半導体チップ実装部を示す実施例で金
属基材上に実装された半導体チップ実装部を示す拡大断
面図である。
FIG. 6 is an enlarged cross-sectional view showing a semiconductor chip mounting portion mounted on a metal substrate in an example showing the semiconductor chip mounting portion of the present invention.

【図7】実施例を説明するための回路図である。FIG. 7 is a circuit diagram for explaining an example.

【図8】従来の回路装置を示す斜視図である。FIG. 8 is a perspective view showing a conventional circuit device.

【図9】従来の回路装置での半導体チップ実装部を示す
断面図である。
FIG. 9 is a cross-sectional view showing a semiconductor chip mounting portion in a conventional circuit device.

【符号の説明】[Explanation of symbols]

11 金属基材 12 第一の絶縁層 13 第二の導電層 14 金属ブロック 15 高発熱部品(半導体チップ) 16 ボンディングワイヤ 22 第二の絶縁層 34 第一の導電層 44 第一の絶縁層の窓明き部 54 第二の絶縁層の窓明き部 64 第二の絶縁層の窓明き部 74 第二の絶縁層の窓明き部 84 第二の絶縁層の窓明き部 11 Metal Base Material 12 First Insulating Layer 13 Second Conductive Layer 14 Metal Block 15 High Heat-generating Component (Semiconductor Chip) 16 Bonding Wire 22 Second Insulating Layer 34 First Conductive Layer 44 First Insulating Layer Window Window portion 54 Second window layer of insulating layer 64 Window window portion of second insulating layer 74 Window window portion of second insulating layer 84 Window window portion of second insulating layer

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】金属基材と、前記金属基材上に貼り付けら
れ且つ前記金属基材表面を部分的に露出させる窓明き部
が設けられた絶縁層と、前記絶縁層上に形成された少な
くとも2層からなる導電層と、前記窓明き部で部分的に
露出した前記金属基材上に配され前記導電層と接続され
た高発熱部品とを備えたことを特徴とする回路装置。
1. A metal base material, an insulating layer provided on the metal base material and provided with a window opening part for partially exposing the surface of the metal base material, and formed on the insulating layer. And a high heat-generating component connected to the conductive layer, the conductive layer being composed of at least two layers and disposed on the metal base material that is partially exposed in the window opening. ..
JP4256389A 1992-09-25 1992-09-25 Circuit device Expired - Fee Related JPH07123186B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4256389A JPH07123186B2 (en) 1992-09-25 1992-09-25 Circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4256389A JPH07123186B2 (en) 1992-09-25 1992-09-25 Circuit device

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP1141357A Division JPH0744322B2 (en) 1989-06-02 1989-06-02 Circuit board

Publications (2)

Publication Number Publication Date
JPH05218606A true JPH05218606A (en) 1993-08-27
JPH07123186B2 JPH07123186B2 (en) 1995-12-25

Family

ID=17292000

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4256389A Expired - Fee Related JPH07123186B2 (en) 1992-09-25 1992-09-25 Circuit device

Country Status (1)

Country Link
JP (1) JPH07123186B2 (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7313001B2 (en) 2001-03-24 2007-12-25 Marquardt Gmbh Electrical switch having a mount for an electrical circuit
WO2008069260A1 (en) * 2006-11-30 2008-06-12 Sanyo Electric Co., Ltd. Circuit element mounting board, circuit device using the same, and air conditioner
JP2011009475A (en) * 2009-06-25 2011-01-13 Panasonic Electric Works Co Ltd Heat radiating component integrated circuit board
EP2620980A1 (en) * 2012-01-25 2013-07-31 Shinko Electric Industries Co., Ltd. Wiring substrate, light emitting device, and manufacturing method of wiring substrate
US9029891B2 (en) 2012-01-25 2015-05-12 Shinko Electric Industries Co., Ltd. Wiring substrate, light emitting device, and manufacturing method of wiring substrate
US9084372B2 (en) 2012-01-25 2015-07-14 Shinko Electric Industries Co., Ltd. Wiring substrate, light emitting device, and manufacturing method of wiring substrate

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55117298A (en) * 1980-01-04 1980-09-09 Sharp Kk Circuit board and method of fabricating same
JPS62217698A (en) * 1986-03-19 1987-09-25 昭和電工株式会社 Metal base multilayer printed board
JPH036096A (en) * 1989-06-02 1991-01-11 Matsushita Electric Works Ltd Circuit board

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55117298A (en) * 1980-01-04 1980-09-09 Sharp Kk Circuit board and method of fabricating same
JPS62217698A (en) * 1986-03-19 1987-09-25 昭和電工株式会社 Metal base multilayer printed board
JPH036096A (en) * 1989-06-02 1991-01-11 Matsushita Electric Works Ltd Circuit board

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7313001B2 (en) 2001-03-24 2007-12-25 Marquardt Gmbh Electrical switch having a mount for an electrical circuit
WO2008069260A1 (en) * 2006-11-30 2008-06-12 Sanyo Electric Co., Ltd. Circuit element mounting board, circuit device using the same, and air conditioner
JPWO2008069260A1 (en) * 2006-11-30 2010-03-25 三洋電機株式会社 Circuit element mounting board, circuit device using the same, and air conditioner
US8436250B2 (en) 2006-11-30 2013-05-07 Sanyo Electric Co., Ltd. Metal core circuit element mounting board
JP2011009475A (en) * 2009-06-25 2011-01-13 Panasonic Electric Works Co Ltd Heat radiating component integrated circuit board
EP2620980A1 (en) * 2012-01-25 2013-07-31 Shinko Electric Industries Co., Ltd. Wiring substrate, light emitting device, and manufacturing method of wiring substrate
US9000474B2 (en) 2012-01-25 2015-04-07 Shinko Electric Industries Co. Ltd. Wiring substrate, light emitting device, and manufacturing method of wiring substrate
US9029891B2 (en) 2012-01-25 2015-05-12 Shinko Electric Industries Co., Ltd. Wiring substrate, light emitting device, and manufacturing method of wiring substrate
US9084372B2 (en) 2012-01-25 2015-07-14 Shinko Electric Industries Co., Ltd. Wiring substrate, light emitting device, and manufacturing method of wiring substrate

Also Published As

Publication number Publication date
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