JPH05198814A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

PURPOSE:To provide the title semiconductor device and manufacturing method thereof capable of reducing the defectives and dispersion in the element characteristics due to the bonding of carbon, etc., or the formation of a natural oxide film on the interface between a contact layer and a channel semiconductor layer. CONSTITUTION:A source electrode 14a and a drain electrode 14b comprising a transparent electrode layer such as ITO are formed on a transparent insulating substrate 10 and then a contact layer 16 comprising n<+> type alpha-Si layer and a protective layer 18 comprising an undoped alpha-Si layer about 10nm thick are successively laminated on said electrodes 14a, 14b. On the other hand, a channel semiconductor layer 20 is formed on said substrate 10 held between said electrodes 14a and 14b so as to be ohmic connected to said electrode 14a and 14b through the intermediary of the contact layer 16 and the protective layer 18. Finally, a gate electrode 24 is formed on the channel semiconductor layer 20 through the intermediary of a gate insulating layer 22.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a top gate staggered TFT (thin film transistor) matrix used for driving a liquid crystal display and a manufacturing method thereof. A liquid crystal display device driven by a TFT matrix has already been put to practical use in a small television and the like, and demand is expected for a display of a large television or a laptop personal computer. And this T
For the FT, a top gate staggered TFT whose gate electrode is above the channel semiconductor layer and a bottom gate staggered TFT whose gate electrode is below the channel semiconductor layer are mainly used.

The top gate staggered type TFT is slightly disadvantageous compared to the bottom gate staggered type TFT in that variations in TFT characteristics occur, but element isolation is performed in the same step as the patterning of the gate electrode. Therefore, it can be said that the structure is simpler than the bottom gate staggered TFT. In the future, simplification will be indispensable in terms of cost reduction, etc., so top gate staggered TFT
There is a problem to improve the device characteristics in the above.

[0003]

2. Description of the Related Art A conventional top gate staggered TFT
A method of manufacturing the matrix will be described with reference to FIGS. For example, a drain bus line 12 is formed by forming a metal layer such as an Al layer having a thickness of about 60 nm on a transparent insulating substrate 10 such as glass by a sputtering method and then patterning the metal layer into a predetermined shape. (See FIG. 7A).

Next, an IT film having a thickness of about 30 nm is formed on the entire surface.
After forming the transparent electrode layer 14 such as O, a contact layer 16 made of an n + type a-Si layer having a thickness of about 20 nm is formed by P-CVD (plasma vapor deposition) method. Subsequently, a resist 26 patterned into the source electrode and drain electrode patterns is formed on the contact layer 16 by using a photolithography technique (see FIG. 7B).

Next, using the resist 26 as a mask, dry etching is performed with a CF ₄ + O ₂ based gas to remove the contact layer 16 by etching, and then wet etching is performed with a hydrochloric acid based etching solution.
The transparent electrode layer 14 is removed by etching. Thus, the source electrode 14a and the drain electrode 1 formed of the transparent electrode layer 14 are formed.
4b are formed at a predetermined interval. The source electrode 14a constitutes a pixel electrode, and the drain electrode 14b is ohmic-connected to the drain bus line 12.

After that, the resist 26 is removed using a resist stripping solution such as acetone. At this time, carbon deposits and a natural oxide film 28 are formed on the surface of the contact layer 16 by the resist process and the like (see FIG. 7 (c)). Next, the contact layer 16 formed by a resist process or the like
The upper thin natural oxide film 28 is removed by etching with a hydrofluoric acid-based etching solution such as diluted hydrofluoric acid for several seconds. After that, a channel semiconductor layer 20 made of an undoped a-Si layer having a thickness of about 40 nm is formed on the entire surface by P-CVD quickly, and subsequently, a first layer of gate insulation made of a SiN layer having a thickness of 50 nm is formed. The layer 22a is formed (see FIG. 8A).

Next, a photolithography technique is used to form a resist patterned into a drive element pattern, and dry etching is performed using a CF ₄ + O ₂ based gas using this resist as a mask to form the gate insulating layer 22a and the channel semiconductor layer 20. Remove by etching. Then, the resist is peeled off. At this time, in portions other than the driving element, the gate insulating layer 22a and the channel semiconductor layer 20 are formed.
At the same time, the contact layer 16 is also removed by etching, and the source electrode 14a forming the pixel electrode and the drain electrode 14b connected to the drain bus line 12 are exposed.

Further, the channel semiconductor layer 20 is formed on the transparent insulating substrate 10 sandwiched between the source electrode 14a and the drain electrode 14b, and ohmic contacts the source electrode 14a and the drain electrode 14b via the contact layer 16. They are connected (see FIG. 8B). Then, on the whole surface,
A second gate insulating layer 22b made of a SiN layer having a thickness of 250 nm is formed by using the P-CVD method. Subsequently, a metal layer such as Al having a thickness of 300 nm is formed by using a sputtering method, and then patterned into a predetermined shape to form the gate electrode 24. Thus, the channel semiconductor layer 2
0, the electrode 24 is formed via the first-layer gate insulating layer 22a and the second-layer gate insulating layer 22b (see FIG. 8C).

The TFT is completed through the above steps.

[0010]

In the above conventional method of manufacturing a TFT, the contact layer 16 and the transparent electrode layer 1 are used.
4 is patterned, and immediately before the channel semiconductor layer 20 is formed, the contact layer 1 made of an n + type a-Si layer 1 is formed.
The thin natural oxide film 28 formed on 6 is removed by etching for several seconds with diluted hydrofluoric acid or the like. After this etching, the device is not removed until the channel semiconductor layer 20 made of an undoped a-Si layer is formed. It takes a certain amount of time to carry and raise the temperature in the P-CVD apparatus, and usually there is a time lag of about 1 hour. Therefore, due to the adhesion of carbon and the formation of a natural oxide film on the surface,
This is a major cause of defective TFT characteristics and variations in characteristics, and significantly reduces reliability.

FIG. 9 shows a structure manufactured by the conventional manufacturing method described above.
The device characteristics of the TFT are shown below. The graph of FIG.
Rain voltage V_D= V gate voltage V _GTo
Drain current I_DThe characteristics are shown in FIG.
F is the gate voltage V _GDrain voltage as a parameter
V_DDrain current I_DRepresents a characteristic.

It is clear from the graphs of FIGS. 9 (a) and 9 (b).
As you can see, drain voltage V_D= 5V, gate voltage V_G
Drain current I under the condition of = 30V_D, I.e.
Flow I _ONIs the on-current I_ONThe average value of 3.98 × 10^-6A
A large variation of ± 28% in the center, and also to Claudig
More lost drain voltage V_DIs about 1.1V
It is a large value.

Regarding the characteristic defects and characteristic variations of the TFT due to the adhesion of carbon or the like to the interface between the contact layer 16 and the channel semiconductor layer 20 and the formation of the natural oxide film, the characteristics on the contact layer 16 are reduced. From the removal of the natural oxide film 28 to the formation of the channel semiconductor layer 20 made of an a-Si layer, a method of performing surface treatment in-line while maintaining a vacuum to remove the natural oxide film and carbon is also conceivable.
Not only does this method require large-scale equipment,
Further, according to the experiments conducted by the present inventors, the reproducibility is poor and the technique has not been completed yet.

Therefore, the present invention is directed to a semiconductor device capable of reducing defects and variations in element characteristics due to adhesion of carbon or the like to the interface between a contact layer and a channel semiconductor layer and formation of a natural oxide film, and a method of manufacturing the same. The purpose is to provide.

[0015]

[Means for Solving the Problems] In the conventional TFT,
The cause of carbon or the like adhering to the interface between the contact layer and the channel semiconductor layer or the formation of a natural oxide film is, for example, n + type a- which is highly doped with P (phosphorus).
The contact layer made of a Si layer is an undoped a-Si.
Since the oxidation rate is faster than that of the layer, the thin natural oxide film formed on the contact layer is removed by hydrofluoric acid-based wet etching, and then the channel semiconductor layer formed of, for example, an undoped a-Si layer is formed. It is thought that this is because the degree of oxidation changes at warm temperatures.

[0016] Therefore, the above-mentioned problem is to provide a transparent insulating substrate,
The source electrode and the drain electrode are formed on the transparent insulating substrate at a predetermined distance, and the source electrode is formed on the transparent insulating substrate sandwiched between the source electrode and the drain electrode. In a semiconductor device having a channel semiconductor layer which is ohmic-connected on an upper portion and on the drain electrode via a contact layer doped with an impurity, and a gate electrode formed on the channel semiconductor layer via a gate insulating film. The semiconductor device is characterized in that an intrinsic semiconductor layer is interposed between the contact layer and the channel semiconductor layer.

Further, the above-mentioned problem is that a step of forming a transparent electrode layer on a transparent insulating substrate, and a step of forming a contact layer doped with impurities on the transparent electrode layer, and then continuously forming a contact layer on the contact layer. A step of forming a protective layer made of an intrinsic semiconductor layer, and selectively etching the protective layer, the contact layer and the transparent electrode layer to form a source electrode and a drain electrode made of the transparent electrode layer at predetermined intervals. And the step of forming the channel semiconductor layer and the first gate insulating film are sequentially deposited on the entire surface, and then the first gate insulating film, the channel semiconductor layer, the protective layer, and the contact layer are selectively etched. Then, the channel semiconductor layer is formed on the transparent insulating substrate sandwiched between the source electrode and the drain electrode, and the channel semiconductor layer is protected. And a step of respectively ohmic connected to the source electrode and the drain electrode through the contact layer, the first on the channel semiconductor layer
And a step of forming a gate electrode on the gate insulating film with a second gate insulating film interposed therebetween.

In the method of manufacturing a semiconductor device described above, the contact layer is a first amorphous-silicon layer doped with impurities, and the protective layer is an undoped second amorphous-silicon layer. After forming the first amorphous-silicon layer on the transparent electrode layer, the second amorphous-silicon layer having a thickness of 1 is continuously formed on the first amorphous-silicon layer.
It is achieved by a method for manufacturing a semiconductor device, which has a step of forming the film having a thickness of not less than 10 nm.

Further, in the above-described method for manufacturing a semiconductor device, the channel semiconductor layer is an undoped third amorphous-silicon layer, and the total thickness of the transparent electrode layer, the contact layer and the protective layer is 150 nm
This is achieved by a method of manufacturing a semiconductor device characterized by the following.

[0020]

According to the present invention, the contact layer is formed even when the channel semiconductor layer is formed by continuously forming the protective layer made of the intrinsic semiconductor layer after forming the contact layer to which the impurity is added. Since the surface is covered with the protective layer and the layer to which the impurity is added is not exposed, adhesion of carbon or the like to the surface of the contact layer and formation of a natural oxide film on the surface are less likely to occur.

Therefore, it is possible to prevent the adhesion of carbon or the like to the interface between the contact layer and the channel semiconductor layer and the formation of a natural oxide film, so that the variation of the on-current I _ON can be suppressed and the drain lost by the crowding. The device characteristics can be improved by reducing the voltage V _D.

[0022]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be specifically described below based on illustrated embodiments. FIG. 1 is a sectional view showing a top gate staggered type TFT according to a first embodiment of the present invention. For example, on a transparent insulating substrate 10 such as glass, a thickness of 60 nm
Drain bus line 1 consisting of a metal layer such as an Al layer
2 is formed. Further, on the transparent insulating substrate 10, a source electrode 14a and a drain electrode 14b made of a transparent electrode layer such as ITO having a thickness of about 30 nm are formed at a predetermined interval. The source electrode 14a constitutes a pixel electrode, and the drain electrode 14b is ohmic-connected to the drain bus line 12.

Further, on the source electrode 14a and the drain electrode 14b, a contact layer 16 made of an n + -type a-Si layer having a thickness of about 20 nm and a protective layer made of an undoped a-Si layer having a thickness of about 10 nm. 18 are sequentially stacked. And an undoped aS having a thickness of about 40 nm
The channel semiconductor layer 20 including the i-layer is the source electrode 14
transparent insulating substrate 1 sandwiched between a and the drain electrode 14b
It is formed on the protective layer 18 as well as on the protective layer 18. Therefore, the channel semiconductor layer 20 is ohmic-connected to the source electrode 14a and the drain electrode 14b via the contact layer 16 and the protective layer 18.

Further, on the channel semiconductor layer 20, a gate electrode 24 made of a metal layer such as an Al layer having a thickness of about 300 nm is formed via a gate insulating layer 22 made of a SiN layer having a thickness of about 300 nm. There is. Next, a method of manufacturing the top gate staggered type TFT shown in FIG. 1 will be described with reference to the process diagrams shown in FIGS.

After forming a metal layer such as an Al layer having a thickness of about 60 nm on the transparent insulating substrate 10 by the sputtering method, the resist patterned into a predetermined shape by the photolithography technique is used as a mask. , The metal layer is selectively etched to form the drain bus line 12 (see FIG. 2A). Next, after forming a transparent electrode layer 14 such as ITO having a thickness of about 30 nm on the entire surface, P-CV is performed.
Using the D (plasma vapor deposition) method, a contact layer 16 made of an n + type a-Si layer having a thickness of about 20 nm and a protective layer 18 made of an undoped a-Si layer having a thickness of about 10 nm are successively formed. (See FIG. 2B).

Next, a resist 26 patterned into a source electrode pattern and a drain electrode pattern is formed on the protective layer 18 by using a photolithography technique (see FIG. 2C). Then, using the resist 26 as a mask, dry etching with a CF ₄ + O ₂ based gas is performed to remove the protective layer 18 and the contact layer 16 by etching, followed by wet etching with a hydrochloric acid based etching solution to form a transparent electrode layer. 14 is removed by etching. After that, the resist 26 is removed using a resist stripping solution such as acetone.

In this way, the source electrode 14a and the drain electrode 14b made of the transparent electrode layer 14 are formed at a predetermined interval. The source electrode 14a constitutes a pixel electrode, and the drain electrode 14b is ohmic-connected to the drain bus line 12 (see FIG. 3A). Then, a channel semiconductor layer 20 made of an undoped a-Si layer having a thickness of about 40 nm is formed on the entire surface by P-CVD method, and subsequently, a first layer made of a SiN layer having a thickness of 50 nm is formed. The gate insulating layer 22a is formed (see FIG. 3B).

Next, a photolithography technique is used to form a resist patterned into a drive element pattern, and dry etching is carried out with a CF ₄ + O ₂ based gas using this resist as a mask to form the gate insulating layer 22.
The a and the channel semiconductor layer 20 are removed by etching. After that, the resist is peeled off. At this time, in portions other than the driving element, the gate insulating layer 22a and the channel semiconductor layer 2 are formed.
At the same time as 0, the protective layer 18 and the contact layer 16 are also removed by etching, and the source electrode 14 a forming the pixel electrode and the drain electrode 14 connected to the drain bus line 12 are connected.
b is exposed.

The channel semiconductor layer 20 is formed on the transparent insulating substrate 10 sandwiched between the source electrode 14a and the drain electrode 14b, and the contact layer 16 and the contact layer 16 are formed on the source electrode 14a and the drain electrode 14b. It is formed via the protective layer 18. Therefore, the channel semiconductor layer 20 is ohmic-connected to the source electrode 14a and the drain electrode 14b via the contact layer 16 and the protective layer 18 (see FIG. 4A).

Then, a second gate insulating layer 22b made of a SiN layer having a thickness of 250 nm is formed on the entire surface by P-CVD. Subsequently, a metal layer of Al or the like having a thickness of 300 nm is formed by using a sputtering method, and then the metal layer is selectively etched using a resist patterned into a predetermined shape by photolithography as a mask to form a gate. The electrode 24 is formed. Thus, the electrode 24 is formed on the channel semiconductor layer 20 through the gate insulating layer 22 having the thickness of 300 nm including the first-layer gate insulating layer 22a and the second-layer gate insulating layer 22b (FIG. Four
(See (b)).

Through the above steps, the top gates shown in FIG.
Complete a tagard type TFT. Next, the top game of FIG.
Use the graph in Figure 5 for the device characteristics of the Tostaguard TFT.
And explain. The graph of FIG. 5A shows the drain voltage V
_D= V gate voltage V _GAgainst dray
Current I_DThe characteristic is shown in the graph of FIG.
Voltage V _GDrain voltage V_DAgainst
Drain current I_DRepresents a characteristic.

The device characteristics of the TFT shown in the graphs of FIGS. 5A and 5B are compared with the device characteristics of the conventional TFT shown in the graphs of FIGS. 9A and 9B. It becomes like Table 1.

[0033]

[Table 1] As is clear from this table, the drain voltage V _D = 5V,
Drain current I under the condition of gate voltage V _G = 30V
_D , that is, the variation of the _ON current I _ON , is ±
It is decreased from 28% to ± 17%, and the drain voltage V _D lost due to Claudig is also decreased from about 1.1 V in the conventional example to 0.5 V or less, showing a considerable improvement.

As described above, according to this embodiment, as shown in FIG.
As shown in FIG. 3, when the contact layer 16 made of an n + type a-Si layer is formed, a protective layer 18 made of an undoped a-Si layer having a thickness of about 10 nm is continuously laminated to obtain a The n + -type a-Si layer in which the contact layer 16 has its surface covered with the protective layer 18 and is heavily doped with impurities even at the time of temperature rise when the channel semiconductor layer 20 made of the -Si layer is formed. Since carbon is not exposed, adhesion of carbon or the like to the surface of the contact layer 16 and formation of a natural oxide film on the surface are less likely to occur.

Further, the manufacturing method according to the present embodiment is almost the same as the conventional manufacturing method in terms of steps, and therefore can be easily carried out without newly modifying the device or the like. In this way, by preventing carbon or the like from adhering to the interface between the contact layer and the channel semiconductor layer and forming a natural oxide film, it is possible to suppress variations in the on-current I _ON as shown in Table 1, and Top gate staggered TF, such as reducing lost drain voltage V _D
The element characteristics of T can be improved. Therefore, the TFT
It greatly contributes to the improvement of the matrix yield, the improvement of display quality, and the cost reduction.

In the above embodiment, the protective layer 18
Although an undoped a-Si layer having a thickness of about 10 nm is used as the protective layer 18, if the protective layer 18 is too thin, the n + type of the contact layer 16 and the protective layer 18 when the protective layer 18 is formed is formed. By mixing at the a-Si / a-Si interface,
If the impurities in the contact layer 16 diffuse to the surface of the protective layer 18, the effect of the above embodiment cannot be exhibited.

According to the experiments conducted by the present inventors, the contact layer is composed of an n + -type a-Si layer, and the protective layer is undoped a-Si.
-If it consists of a Si layer, the thickness of the protective layer is at least 1 n.
m is necessary and is preferably 5 nm or more in order to obtain a sufficient effect. Further, if the thickness of the protective layer 18 and the like is too large, in the step shown in FIG. 3B, when the channel semiconductor layer 20 made of the undoped a-Si layer is formed, "step breakage" at the step portion is formed. May occur, resulting in poor characteristics.

For example, the height of the step, that is, the transparent electrode layer 14,
The total thickness of the contact layer 16 and the protective layer 18 is 20
When the thickness is set to 0 nm, the characteristics of the manufactured TFT have a large variation in the on-current I _ON , as shown in the graph of FIG. Therefore, when the semiconductor layer is formed of an undoped a-Si layer, the total thickness of the transparent electrode layer, the contact layer and the protective layer is preferably 150 nm or less, though it depends on the step coverage and the film thickness.

Further, in the above embodiment, the protective layer 18
Although the undoped a-Si layer is used as the above, it is not limited to the a-Si layer, but is an authentic semiconductor layer that is continuously formed with the contact layer and prevents the contact layer surface that is highly doped with impurities from being exposed. It suffices to use it, and it is also possible to use, for example, an a-SiGe layer.

[0040]

As described above, according to the present invention, after the contact layer doped with impurities is formed on the transparent electrode layer,
A protective layer made of an intrinsic semiconductor layer is continuously formed, and the protective layer, the contact layer, and the transparent electrode layer are selectively etched so that the source electrode and the drain electrode made of the transparent electrode layer are spaced by a predetermined distance. And sequentially depositing the channel semiconductor layer and the first gate insulating film on the entire surface, and selectively ohmic-connecting the channel semiconductor layer to the source electrode and the drain electrode through the protective layer and the contact layer, respectively. As a result, even when the channel semiconductor layer is deposited, the surface of the contact layer is covered with the protective layer, and the layer to which the impurity is added is not exposed. The formation of an oxide film is less likely to occur.

Therefore, by preventing carbon or the like from adhering to the interface between the contact layer and the channel semiconductor layer or forming a natural oxide film, it is possible to prevent the deterioration of the device characteristics due to these and to improve the device characteristics. Therefore, yield improvement, display quality improvement, and cost reduction can be realized.

[Brief description of drawings]

FIG. 1 is a sectional view showing a TFT according to an embodiment of the present invention.

2A to 2D are process diagrams (No. 1) for explaining the method for manufacturing the TFT shown in FIG.

3A to 3D are process diagrams (No. 2) for explaining the method for manufacturing the TFT shown in FIG.

FIG. 4 is a process diagram (3) for explaining the method for manufacturing the TFT shown in FIG. 1.

5 is a graph showing device characteristics of the TFT shown in FIG.

FIG. 6 is a graph showing device characteristics of a TFT when “step break” occurs in a channel semiconductor layer.

FIG. 7 is a process diagram (1) for explaining a conventional method for manufacturing a TFT.

FIG. 8 is a process diagram (No. 2) for explaining a conventional TFT manufacturing method.

FIG. 9 is a graph showing device characteristics of a conventional TFT.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 ... Transparent insulating substrate 12 ... Drain bus line 14 ... Transparent electrode layer 14a ... Source electrode 14b ... Drain electrode 16 ... Contact layer 18 ... Protective layer 20 ... Channel semiconductor layers 22, 22a, 22b ... Gate insulating layer 24 ... Gate electrode 26 ... Resist 28 ... Natural oxide film

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Koji Ogata 1015 Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture, Fujitsu Limited (72) Inventor Kenichi Oki 1015, Kamedotachu, Nakahara-ku, Kawasaki City, Kanagawa Prefecture Fujitsu Limited Within

Claims (4)

[Claims] 1. A transparent insulating substrate, a source electrode and a drain electrode formed on the transparent insulating substrate at a predetermined interval, and the transparent insulating substrate sandwiched between the source electrode and the drain electrode. A channel semiconductor layer formed on a substrate and ohmic-connected via a contact layer doped with impurities on the source electrode and the drain electrode, and a gate insulating film on the channel semiconductor layer. A semiconductor device having a formed gate electrode, wherein a layer made of an intrinsic semiconductor layer is interposed between the contact layer and the channel semiconductor layer. 2. A step of forming a transparent electrode layer on a transparent insulating substrate, and a step of forming an impurity-added contact layer on the transparent electrode layer, and then successively forming an intrinsic semiconductor layer on the contact layer. A step of forming a protective layer made of, and selectively etching the protective layer, the contact layer, and the transparent electrode layer to form a source electrode and a drain electrode made of the transparent electrode layer at predetermined intervals. And a step of sequentially depositing a channel semiconductor layer and a first gate insulating film on the entire surface, and selectively etching the first gate insulating film, the channel semiconductor layer, the protective layer, and the contact layer, A channel semiconductor layer is formed on the transparent insulating substrate sandwiched between the source electrode and the drain electrode, and the channel semiconductor layer is formed on the protective layer and the contact layer. A ohmic contact to each of the source electrode and the drain electrode via an insulating layer, and a step of forming a gate electrode on the first gate insulating film on the channel semiconductor layer via a second gate insulating film. A method of manufacturing a semiconductor device, comprising: 3. The method for manufacturing a semiconductor device according to claim 2, wherein the contact layer is a first amorphous-silicon layer doped with impurities, and the protective layer is an undoped second amorphous-silicon layer. A first amorphous-silicon layer is formed on the transparent electrode layer, and then the first amorphous-silicon layer is continuously formed.
A method of manufacturing a semiconductor device, comprising the step of forming the second amorphous-silicon layer having a thickness of 1 nm or more on a silicon layer. 4. The method of manufacturing a semiconductor device according to claim 2, wherein the channel semiconductor layer is an undoped third amorphous-silicon layer, and the transparent electrode layer, the contact layer, and the protective layer are formed. A method of manufacturing a semiconductor device, wherein the combined thickness is 150 nm or less.