JPH05190672A - Semiconductor device and layout system - Google Patents

Abstract

PURPOSE:To realize effective layout of power supply line in order to reduce man-hour in the design step, while effectively enabling floor plan of a logical integrated circuit device introducing a standard cell system. CONSTITUTION:A power supply cell SC for connecting a power supply line SVC3 and a grounding voltage supply line SVS3 arranged in the X axis direction and power source voltage supply lines SVC2 and SVS2 arranged in the Y axis direction in the intermediate area of cell string CG1 to CG7 and a dummy cell DC for filling a vacant region generated when a power supply cell SC is inserted are added in a cell library. Moreover, in the course of automatic arrangement and design steps of a logical integrated circuit device LSI or the like, a total sum of gate width of MOSFET in each cell string is calculated and the power supply cell SC and dummy cell DC are inserted to the position where the total sum of all cell string SG1 to CG7 has reached the distances L1 to L7 corresponding to the predetermined maximum value.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a layout system thereof, and more particularly to a logic integrated circuit device adopting a standard cell system and a technique particularly effective for use in automatic layout design thereof.

[0002]

2. Description of the Related Art There is a so-called standard cell type logic integrated circuit device which is constituted by combining polycells or macrocells registered in a cell library in units of logically united functional units.

Large-scale integrated circuit devices adopting the standard cell system are issued, for example, by Nikkei McGraw-Hill Inc., 1
"Nikkei Electronics" No. 175, September 9, 985
Pp.-179.

[0004]

In a logic integrated circuit device or the like adopting the standard cell system, a plurality of combined poly cells are arranged in a row at a predetermined wiring region to form a plurality of cell rows. The power supply voltage and the ground potential of the circuit are respectively supplied to the respective cell columns through the power supply voltage supply line and the ground potential supply line which are arranged in parallel in the X-axis direction, and these power supply voltage supply line and the ground potential supply are supplied. The line is
It is coupled to a larger capacity power supply voltage supply line and a ground potential supply line arranged at both ends of the cell row, respectively.

However, as the integrated circuit becomes large-scaled and highly integrated and the cell column length thereof becomes large, the following problems occur in the above logic integrated circuit device or the like. It became clear by the person etc. That is, there are restrictions on the wiring widths of the power supply voltage supply lines and the ground potential supply lines that are provided in parallel with the cell columns of the logic integrated circuit device, and as the cell column length increases, these power supply voltage supply lines and the ground potential supply lines are supplied. It is not possible to obtain the specified operating power supply due to the voltage drop of the line. Therefore, the shapes of the cell rows and the cell blocks are restricted by the power supply conditions, and an efficient floor plan of the logic integrated circuit device or the like cannot be realized.
Further, in order to deal with this, if an attempt is made to add a power supply voltage supply line and a ground potential supply line in the Y-axis direction to the middle of the cell row, the amount of manual work is increased, and the number of design steps for a logic integrated circuit device or the like is increased. ..

An object of the present invention is to provide a layout system of power supply lines effective for a large-scale logic integrated circuit device adopting the standard cell system. Another object of the present invention is to reduce the design man-hours of a logic integrated circuit device or the like adopting the standard cell method while making the floor plan more efficient.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0008]

The outline of a typical invention among the inventions disclosed in the present application will be briefly described as follows. That is, the power supply voltage supply line and the ground potential supply line arranged in the X axis direction in the middle of the cell line and in parallel with the cell line are coupled to the power supply voltage supply line and the ground potential supply line arranged in the Y axis direction. And a dummy cell for extending the power supply voltage supply line and the ground potential supply line in the X-axis direction, which is inserted in an empty area generated by the provision of the power supply cell, to the cell library,
In the process of automatic layout design of logic integrated circuit devices, X
The power supply cell is automatically located at a position where the current density in the axial power supply line or the ground potential supply line has reached a predetermined value or the sum of the gate widths of the MOSFETs in all cell rows has reached the maximum allowable value. Are arranged, and dummy cells are further arranged if necessary.

[0009]

According to the above-mentioned means, a power supply voltage supply line for a logic integrated circuit device or the like adopting the standard cell system is provided without causing an excessive or insufficient supply of the power supply voltage to each cell column, and while making the floor plan efficient. Also, the ground potential supply line can be efficiently laid out, and the number of design steps can be reduced.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a board layout diagram of an embodiment of a logic integrated circuit device (LSI) to which the present invention is applied. Further, FIGS. 2, 3 and 4 are plan layout views showing one embodiment of the poly cell PC, the power supply cell SC and the dummy cell DC mounted in the logic integrated circuit device of FIG. 1, respectively. Based on these figures, the configuration and board layout of the logic integrated circuit device of this embodiment, and the outline and characteristics of the layout system will be described. The logic integrated circuit device of this embodiment is a combination of P-channel and N-channel MOSFETs (metal oxide semiconductor type field effect transistors. In this specification, MOSFETs are collectively referred to as insulated gate field effect transistors). So-called CMOS (complementary MOS)
It is formed on the basis of a logic gate and is formed on one semiconductor substrate SUB made of P-type single crystal silicon. In the following description, the vertical and horizontal directions on the surface of the semiconductor substrate SUB are represented by the positional relationships of FIGS. 1 to 4, and the horizontal direction is referred to as the X axis and the vertical direction is referred to as the Y axis. Furthermore, FIG.
Then, the power supply voltage supply line SVC3 and the ground potential supply line SV
The middle of S3 is omitted.

In FIG. 1, the logic integrated circuit device of this embodiment includes seven cell columns CG1 to CG7 arranged on a semiconductor substrate SUB with a predetermined wiring region. Each of the cell columns CG1 to CG7 has a plurality of poly-cells P registered in advance in a cell library as various CMOS logic gates, that is, various functional units logically grouped together.
It is configured by arranging Cs in a row. These polycells PC are further combined on the basis of a predetermined logic condition to form, for example, a logic operation unit having a predetermined logic operation function.

Around the cell columns CG1 to CG7, a power supply voltage supply line SVC1 and a ground potential supply line SVS1 made of a second aluminum wiring layer are arranged along the four sides of the semiconductor substrate SUB. These power supply voltage supply line and ground potential supply line are respectively coupled to a power supply voltage supply pad and a ground potential supply pad (not shown) as a power supply trunk line, and further apply operating power to the cell columns CG1 to CG7.
The pair of power supply voltage supply lines SVC3 (first power supply line) and the ground potential supply line SVS3 (second power supply line) are respectively coupled. The power supply voltage supply line SVC3 and the ground potential supply line SVS3 are formed of the first aluminum wiring layer.

In this embodiment, the cell columns CG1 to CG
In the middle of 7, power supply cells SC are provided,
A power supply voltage supply line SVC2 (third power supply line) and a ground potential supply line SVS2 (fourth power supply line) formed of a second aluminum wiring layer are formed on the upper layer thereof.
Further, dummy cells DC of a predetermined size are arranged in the empty areas of the cell columns CG1 and CG3 and CG5 to CG7, which are caused by the provision of the power supply cells SC. The power supply voltage supply line SVC3 and the ground potential supply line SVS3 of each cell column are coupled to the corresponding power supply cell SC via the corresponding dummy cell DC, and further, the power supply voltage supply line SVC2 and the ground are connected via this power supply cell SC. Each is connected to the potential supply line SVS2. In addition,
The power supply cell SC and the dummy cell DC, the power supply voltage supply line SVC2 and the ground potential supply line SVS2 are automatically inserted according to a predetermined algorithm described later in the process of automatic placement design by the computer of the logic integrated circuit device.

Here, each of the polycells PC is shown in FIG.
As represented by the CMOS inverter of, the P-type diffusion layer DP formed on the N-type well region NWELL.
And an N-type diffusion layer DN formed adjacently. A gate layer G serving as the gates of the P-channel and N-channel MOSFETs is formed on the upper layers of these diffusion layers with a predetermined insulating film interposed therebetween. Although not particularly limited, the gate layer G is formed of polysilicon (PolySi), and both ends of the gate layer G have input terminals IN1 of the CMOS inverter.
And IN2 are coupled to corresponding input terminals of a subsequent circuit (not shown) through corresponding contacts.

A P-type diffusion layer DP is formed on the upper end of the polycell PC.
The first aluminum wiring layer AL1 to cover a part of
1 is formed, and the ground potential supply line SV formed of the aluminum wiring layer AL12 of the first layer is formed at the lower end of the power supply voltage supply line SVC3 so as to cover a part of the N-type diffusion layer DN.
S3 is formed. These power supply voltage supply lines and ground potential supply lines are arranged in the X-axis direction in parallel with each cell row by connecting a plurality of polycells PC in a row, and the power supply voltage supply lines SVC3 and Ground potential supply line SVS
3 respectively, and further connected to the power supply voltage supply line SVC1 and the ground potential supply line SVS1 at both ends thereof.

The region on the left side of the P type diffusion layer DP, which sandwiches the gate layer G, serves as the source of the P channel MOSFET.
A region on the left side of the N-type diffusion layer DN, which is coupled to the power supply voltage supply line SVC3 through the plurality of contacts and sandwiches the gate layer G, serves as a source of the N-channel MOSFET and is connected to the ground potential supply line SVS3 through the plurality of contacts. Be combined. The regions on the right side of the P-type diffusion layer DP and the N-type diffusion layer DN are P-channel and N-channel MOSFE, respectively.
As a drain of T, a plurality of corresponding contacts and a first
It is commonly coupled via the aluminum wiring layer AL13 of the layer and becomes the output terminal OUT of the CMOS inverter. The output terminal OUT is further coupled to an input terminal of a post-stage circuit (not shown) through a through hole.

On the other hand, each of the power supply cells SC does not include an active element such as MOSFET as shown in FIG. A power supply voltage supply line SVC3 formed of a first-layer aluminum wiring layer AL11 is formed at the upper end of the power supply cell SC, and a ground potential supply line SVS3 formed of a first-layer aluminum wiring layer AL12 is formed at the lower end thereof. To be done. Further, on the left end of the power supply cell SC, the power supply voltage supply line SVC including the second-layer aluminum wiring layer AL21 is provided.
2 is formed, and the ground potential supply line SVS2 made of the second-layer aluminum wiring layer AL22 is formed at the right end thereof. In this embodiment, the power supply voltage supply line SVC2
Is a power supply voltage supply line SVC through a plurality of through holes.
3, the ground potential supply line SVS2 is coupled to the ground potential supply line SVS3 through a plurality of through holes.

The power supply voltage supply line SVC2 and the ground potential supply line SVS2 are connected to the seven power supply cells SC provided corresponding to the cell columns CG1 to CG7.
The power supply voltage supply line SVC2 and the ground potential supply line SV of FIG. 1 arranged in the Y-axis direction orthogonal to the cell columns CG1 to CG7.
Configure S2 respectively. In addition, the power supply voltage supply line SVC
3 and the ground potential supply line SVS3 are provided on the left and right sides of the power supply voltage supply line SVC of the poly cell PC or the dummy cell DC.
3 and the ground potential supply line SVS3, respectively, and are arranged in the X-axis direction in parallel with the cell columns CG1 to CG7, and the power supply voltage supply line SVC3 and the ground potential supply line SVS of FIG.
3, respectively.

As shown in FIG. 4, each of the dummy cells DC does not include an active element such as MOSFET like the power supply cell SC. A power supply voltage supply line SVC3 made of the first-layer aluminum wiring layer AL11 is formed at the upper end of the dummy cell DC, and a ground potential supply line SVS made of the first-layer aluminum wiring layer AL12 is formed at the lower end thereof.
3 is formed.

In this embodiment, the dummy cell DC is
As will be described later, the power supply voltage supply line SVC3 and the ground potential supply line SVS3 of the polycells PC arranged in the empty regions of the cell columns CG1 to CG7, which are generated by the insertion of the power supply cells SC, correspond to each other. The power supply cell SC has a function of extending and connecting to the power supply voltage supply line SVC3 and the ground potential supply line SVS3.

Next, returning to FIG. 1, the outline of the layout method of the logic integrated circuit device will be described. The logic integrated circuit device of this embodiment is configured by combining various polycells PC registered in the cell library as described above. These polycells PC are combined in columns so that the wiring length as a whole is the shortest, and form the cell columns CG1 to CG7 in FIG. The power supply voltage and ground potential of the circuit are supplied to the cell columns CG1 to CG7 through the corresponding power supply voltage supply line SVC3 and ground potential supply line SVS3, and each of the polycells PC forming each cell column is
A predetermined basic logic function is achieved by using the power supply voltage and ground potential of the circuit as operating power supplies.

In the logic integrated circuit device of this embodiment, when laying out the cell columns CG1 to CG7, the value of the operating current and the voltage drop flowing through the power supply voltage supply line SVC3 and the ground potential supply line SVS3 are calculated, When the current density or the total gate width of MOSFETs in each cell row reaches a predetermined value, the power supply cell SC and the dummy cell D
Insert C etc. automatically. That is, in this embodiment,
First, the maximum value Wmax of the total gate widths of the MOSFETs in the cell row is defined as Wmax = (ALw × Ipeak) / (Itrp × K) (1). Here, ALw is the width of the power supply voltage supply line that supplies the operating power to each cell column, and Ipeak
Is the maximum allowable current per unit width of the power supply voltage supply line. Further, Itrp is a peak current value during the operation of the MOSFET, and K is a MOSF in each cell column.
It is the activity rate of ET.

Next, starting from the left end of the cell rows CG1 to CG7, the MOSFET of each cell row is calculated according to the above equation (1).
Calculate the sum of the gate widths of
Distances L1 to L7 exceeding max are obtained. And FIG.
As illustrated in FIG. 7, a total of seven power supply cells SC are arranged in the cell rows CG1 to CG7 in accordance with the cell rows CG2 and CG4 having the longest distances, and the power supply cells SC are connected to each other. Power supply line SVC in the Y-axis direction
2 and SVS2. Furthermore, power supply cell SC
Cell columns CG1 and CG caused by the insertion of
3 and the empty areas of CG5 to CG7, dummy cells DC having a predetermined width are arranged, and these dummy cells D
The polycell PC and the corresponding power supply cell SC are connected via C. As a result of these, cell columns CG1 to CG7
Are the power supply voltage supply line SVC3 and the ground potential supply line SV.
Immediately before the voltage drop in S3 reaches an unacceptable value, the power supply voltage supply line SVC2 and the ground potential supply line SVS
The power supply voltage and the ground potential of the circuit are replenished via 2 respectively, whereby the stable operation of the poly cell PC constituting each cell row is guaranteed.

As described above, since the process of inserting the power supply cell SC and the dummy cell DC is automatically performed in the process of automatic wiring design of the logic integrated circuit device, the manual design work is substantially eliminated. Further, since these insertion processes are performed by quantitatively calculating the current density in the power supply voltage supply line and the ground potential supply line of each cell row or the total sum of the gate widths of the MOSFETs, the power supply voltage of each cell row is calculated. Oversupply and undersupply logically cease to exist. Further, the power supply cell SC and the dummy cell D
By automatically inserting C and the like, the designer of the logic integrated circuit device is relieved of the constraint on the shape of the cell row and the cell block due to the power supply condition, and efficiently performs the floor plan on the semiconductor substrate surface. be able to. As a result, the layout design of the logic integrated circuit device adopting the standard cell method can be made efficient and the number of design steps can be reduced.

As shown in the above-mentioned embodiment, by applying the present invention to the logic integrated circuit device adopting the standard cell system and its automatic layout design, the following operational effects can be obtained. That is, (1) a power supply voltage supply line and a ground potential supply line arranged in the X axis direction in the middle of the cell line and parallel to the cell line, and a power supply voltage supply line and a ground potential supply line arranged in the Y axis direction. And a dummy cell for extending a power supply voltage supply line and a ground potential supply line in the X-axis direction, which is provided in a vacant area of each cell column generated by the provision of the power supply cell. In the process of automatic layout design of a logic integrated circuit device or the like in the library, the current density in the power supply voltage supply line or the ground potential supply line in the X-axis direction reaches a predetermined value or the MOS in all cell columns is added.
Excessive or excessive supply of the power supply voltage to each cell row is automatically arranged by arranging the power supply cells at the positions where the total sum of the FET gate widths reaches the maximum value that can be tolerated. The effect that the shortage can be solved is obtained. (2) According to the above item (1), it is possible to solve the constraint on the shape of the cell column and the cell block due to the power supply condition of the logic integrated circuit device, etc., and it is possible to efficiently perform the floorplan. (3) According to the above items (1) and (2), it is possible to efficiently lay out the power supply voltage supply line and the ground potential supply line of the logic integrated circuit device adopting the standard cell method and reduce the design man-hours. can get.

The invention made by the present inventor has been specifically described above based on the embodiments, but the present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say. For example, in FIG. 1, the logic integrated circuit device may include an arbitrary number of cell columns, or may include a plurality of cell blocks formed by combining these cell columns.
In the embodiment of FIG. 1, the power supply cell SC is a MOSFET
Distance L1 in which the total sum of the gate widths exceeds the maximum value Wmax
Although the cells are arranged according to the cell rows CG2 and CG4 in which L7 is the largest, the cells can also be arranged according to the cell row CG3 in which the distances L1 to L7 are the smallest. However,
In this case, excessive supply of power supply voltage occurs in other cell columns, and there is a case where another power supply cell SC has to be added to the right side of the power supply cell SC. The logic integrated circuit device may include a memory integrated circuit such as a random access memory or a macro cell including an arithmetic logic operation unit. Three or more aluminum wiring layers can be used for the wiring layout of the logic integrated circuit device, and materials for these metal wiring layers and gate layers can be appropriately selected. Further, the semiconductor substrate SUB can be formed of N-type single crystal silicon, and the shapes and configurations of the poly cell PC and the power supply cell SC and the dummy cell DC shown in FIGS. 2 to 4 are not restricted by these embodiments. ..

In the above description, the case where the invention made by the present inventor is mainly applied to the logic integrated circuit device adopting the standard cell system which is the background field of application has been described, but the invention is not limited thereto. Of course, the present invention can be widely applied to a semiconductor device including a plurality of cell rows in which at least a plurality of polycells are arranged in a row and a layout method thereof.

[0028]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, the power supply voltage supply line and the ground potential supply line arranged in the X axis direction in the middle of the cell line and in parallel with the cell line are coupled to the power supply voltage supply line and the ground potential supply line arranged in the Y axis direction. And a dummy cell for inserting the power supply voltage supply line and the ground potential supply line in the X-axis direction, which are inserted in the empty area generated by the provision of the power supply cell, are added to the cell library to perform logic integration. In the process of automatic layout design of circuit devices, etc., the current density in the power supply voltage supply line or the ground potential supply line in the X-axis direction reaches a predetermined value, or the total sum of the gate widths of the MOSFETs in all cell columns is the maximum allowable value. By automatically arranging the power supply cells at the position where the value has been reached, and by arranging the dummy cells as needed, the power supply voltage is over-supplied or supplied to each cell column. It is possible to efficiently layout the power supply voltage supply line and the ground potential supply line of the logic integrated circuit device adopting the standard cell method without inviting a foot and to improve the efficiency of the floor plan, and reduce the design man-hours. ..

[Brief description of drawings]

FIG. 1 is a board layout diagram showing an embodiment of a logic integrated circuit device to which the present invention is applied.

2 is a plan layout view showing an embodiment of a poly cell included in the logic integrated circuit device of FIG. 1. FIG.

3 is a plan layout view showing an embodiment of a power supply cell included in the logic integrated circuit device of FIG. 1. FIG.

4 is a plan layout view showing an embodiment of a dummy cell included in the logic integrated circuit device of FIG. 1. FIG.

[Explanation of symbols]

LSI ... Logical integrated circuit device, SUB ... Semiconductor substrate, CG1 to CG7 ... Cell row, PC ... Polycell, SC ... Power supply cell, DC ... Dummy cell,
SVC1 to SVC3 ... Power supply voltage supply line, SVS1 to
SVS3 ... Ground potential supply line. NWELL ... N-type well region, DP ... P-type diffusion layer, DN ... N-type diffusion layer, G ... Gate layer (Pol)
ySi ... polysilicon), AL11 to AL13, A
L21 to AL22 ... Aluminum wiring layer, IN1 to
IN2 ... Input terminal, OUT ... Output terminal.

Claims (6)

[Claims] 1. A plurality of polycells are arranged in the X-axis direction, and in the Y-axis direction, in the middle of a cell row that receives operating power through first and second power supply lines that are arranged in parallel. A semiconductor device, wherein power supply cells are provided for connecting the third and fourth power supply lines, which are arranged to transmit the operating power, and the first and second power supply lines, respectively. 2. A plurality of polycells are arranged in the X-axis direction, and in the Y-axis direction, in the middle of a cell row receiving operating power through first and second power supply lines arranged in parallel. A layout of a semiconductor device, characterized in that power supply cells for inserting the third and fourth power supply lines arranged to transmit the operating power and the first and second power supply lines respectively are inserted. method. 3. The layout method according to claim 2, wherein the power supply cells are automatically inserted in a process of automatic layout design of the semiconductor device by a computer. 4. The position where the power supply cell is inserted is
3. It is determined according to the current density in the first and second power supply voltage supply lines.
Alternatively, the layout method according to claim 3. 5. The polycell is composed of a MOSFET, and the power supply cell is inserted at a position where a total sum of gate widths in all the cell rows has reached an allowable maximum value. The layout method according to claim 2 or 3, wherein 6. A dummy cell for extending the first and second power supply lines is inserted in an empty area generated by the insertion of the power supply cell. The layout method according to claim 1, claim 2, claim 3, claim 4, or claim 5.