JPH05190373A - Manufacture of laminated ceramic capacitor - Google Patents
Manufacture of laminated ceramic capacitorInfo
- Publication number
- JPH05190373A JPH05190373A JP3048933A JP4893391A JPH05190373A JP H05190373 A JPH05190373 A JP H05190373A JP 3048933 A JP3048933 A JP 3048933A JP 4893391 A JP4893391 A JP 4893391A JP H05190373 A JPH05190373 A JP H05190373A
- Authority
- JP
- Japan
- Prior art keywords
- internal electrode
- electrode layer
- ceramic
- layer
- ceramic capacitor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、積層セラミックコンデ
ンサの製造方法に係り、特に内部電極の形成方法に関す
るものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a laminated ceramic capacitor, and more particularly to a method for forming internal electrodes.
【０００２】[0002]
【従来の技術】従来、積層セラミックコンデンサは、小
型大容量、半永久的な寿命、高周波低インピーダンスな
どそのすぐれた特性から広い範囲で使用されており、特
に交換機や電源等に多く使用されている。その製造方法
は図１及び図２に示すように、強誘電体セラミック粉末
を有機バインダと溶剤を用いて混合分散させたスラリー
を得たあと、ドクターブレード法等を用いて一定の厚み
をもった強誘電体セラミック層２のグリーンシートを作
成する。そのグリーンシート上にＡｕ、Ｐｄ、Ａｇ、Ｃ
ｕ、Ｎｉなどの低抵抗金属粉末を有機ビヒクルに分散さ
せたペーストを用いて、内部電極層１を一定の形状で交
互に取り出し口を得られるようスクリーン印刷等により
成膜を行い、そのグリーンシートを打ち抜き、後の外部
電極４成形の際、コンデンサの並列構造が取れるように
積層することで積層セラミックコンデンサの生チップを
得る。その後、脱バインダ、焼成を行い、内部に積層さ
れた電極（以下内部電極と称す）を取り出すように外部
電極４を両端に焼付することで、コンデンサ素子を得て
いる。2. Description of the Related Art Hitherto, monolithic ceramic capacitors have been used in a wide range because of their excellent characteristics such as small size and large capacity, semi-permanent life, high frequency and low impedance, and particularly, they are often used in exchanges and power supplies. As shown in FIG. 1 and FIG. 2, the manufacturing method thereof is such that a ferroelectric ceramic powder is mixed and dispersed with an organic binder and a solvent to obtain a slurry, and then a certain thickness is obtained by using a doctor blade method or the like. A green sheet of the ferroelectric ceramic layer 2 is created. Au, Pd, Ag, C on the green sheet
Using a paste in which a low resistance metal powder such as u or Ni is dispersed in an organic vehicle, a film is formed by screen printing or the like so that the internal electrode layers 1 can be alternately taken out in a fixed shape, and the green sheet Is punched out, and when the external electrode 4 is formed later, the raw chips of the multilayer ceramic capacitor are obtained by stacking so as to obtain the parallel structure of the capacitor. After that, binder removal and firing are performed, and external electrodes 4 are baked on both ends so as to take out electrodes (hereinafter referred to as internal electrodes) laminated inside, to obtain a capacitor element.
【０００３】ここで、焼成の際に内部電極１に使用され
る低抵抗金属と強誘電体セラミックの収縮率の違いか
ら、クラックや積層部剥離が発生し易く、ショート不良
を生じたり、信頼性が不十分な製品となることが多いと
いう問題があった。そこでチップを構成する強誘電体セ
ラミック粉末と同組成のセラミック粉末を共材として混
入した内部電極ペーストを用いて素子形成を行う試みも
あるが内部電極層全体にセラミック粉末が混入している
ことと、セラミックへの内部電極金属の拡散により内部
電極の切れを生じやすく等価直列抵抗が増大しリップル
電流を助長することから素子そのものが発熱し、コンデ
ンサ実働時に障害を起こしやすいという欠点があった。Here, due to the difference in shrinkage ratio between the low resistance metal used for the internal electrode 1 and the ferroelectric ceramic during firing, cracks and peeling of the laminated portion are likely to occur, short circuit failure may occur, and reliability may deteriorate. There is a problem that the product is often inadequate. Therefore, there is an attempt to form an element by using an internal electrode paste in which a ceramic powder having the same composition as the ferroelectric ceramic powder composing the chip is mixed as a co-material, but the ceramic powder is mixed in the entire internal electrode layer. However, the diffusion of the internal electrode metal into the ceramic tends to cause breakage of the internal electrode, which increases the equivalent series resistance and promotes the ripple current, so that the element itself generates heat, which is liable to cause a failure during actual operation of the capacitor.
【０００４】[0004]
【発明が解決しようとする課題】本発明の課題は、この
ような強誘電体セラミックと内部電極の収縮差から生じ
る層間剥離や、クラックの発生を減少させ、かつ等価直
列抵抗の小さい積層セラミックコンデンサを提供するこ
とにある。SUMMARY OF THE INVENTION An object of the present invention is to reduce the occurrence of delamination and cracks caused by the difference in shrinkage between the ferroelectric ceramic and the internal electrode, and to reduce the equivalent series resistance of the laminated ceramic capacitor. To provide.
【０００５】[0005]
【課題を解決するための手段】本発明は、強誘電体セラ
ミック層と内部電極層との間に強誘電体セラミックと同
材質の強誘電体セラミック粉末、または強誘電体セラミ
ックより融点の高いセラミック粉末を混入した共材入り
内部電極層を有することを特徴とする方法である。即
ち、本発明は、強誘電体セラミック層と低抵抗金属から
なる内部電極層を交互に積層して構成する積層セラミッ
クコンデンサにおいて、強誘電体セラミック層と内部電
極層の間に、前記内部電極を構成する金属重量に対し５
ｗｔ％から６０ｗｔ％の範囲で強誘電体セラミックと同
組成の粉末を共材として混入した共材入り内部電極層を
設けることを特徴とする積層セラミックコンデンサの製
造方法。または、強誘電体セラミック層と低抵抗金属か
らなる内部電極層との間に設けられる共材入り内部電極
層として、積層セラミックコンデンサを構成する強誘電
体セラミックおよびその強誘電体セラミックよりも高融
点のセラミック粉末のうち、少なくとも１種類以上を混
入した内部電極層を設けることを特徴とする積層セラミ
ックコンデンサの製造方法である。According to the present invention, a ferroelectric ceramic powder made of the same material as the ferroelectric ceramic or a ceramic having a higher melting point than the ferroelectric ceramic is provided between the ferroelectric ceramic layer and the internal electrode layer. The method is characterized by having an internal electrode layer containing a co-material mixed with powder. That is, the present invention relates to a multilayer ceramic capacitor configured by alternately stacking a ferroelectric ceramic layer and an internal electrode layer made of a low resistance metal, wherein the internal electrode is provided between the ferroelectric ceramic layer and the internal electrode layer. 5 for the weight of the constituent metal
A method for manufacturing a monolithic ceramic capacitor, comprising: providing an internal electrode layer containing a co-material, in which a powder having the same composition as a ferroelectric ceramic is mixed as a co-material in the range of wt% to 60 wt%. Alternatively, as the internal electrode layer containing a common material provided between the ferroelectric ceramic layer and the internal electrode layer made of a low-resistance metal, the ferroelectric ceramic constituting the monolithic ceramic capacitor and a higher melting point than the ferroelectric ceramic. In the method for manufacturing a monolithic ceramic capacitor, an internal electrode layer in which at least one kind of the ceramic powder is mixed is provided.
【０００６】[0006]
【作用】図１に積層セラミックコンデンサの断面図を示
す。図２は図１の内部電極層の周辺を従来のコンデンサ
について拡大した断面図を示す。図２に示すように従来
の積層セラミックコンデンサでは、強誘電体セラミック
層と内部電極層が直接接するように構成されている。FIG. 1 shows a sectional view of a monolithic ceramic capacitor. FIG. 2 is an enlarged cross-sectional view of a conventional capacitor around the internal electrode layer of FIG. As shown in FIG. 2, the conventional monolithic ceramic capacitor is configured so that the ferroelectric ceramic layer and the internal electrode layer are in direct contact with each other.
【０００７】本発明では、この強誘電体セラミック層と
内部電極層との間に強誘電体セラミック粉末を共材とし
て混入した共材入り内部電極層を設けることを特徴とし
たもので、図３に示す断面図のように強誘電体セラミッ
ク層２と内部電極層１の間に強誘電体セラミック粉末を
共材として含む共材入り内部電極層３を中間層としてと
ることにより、焼成時に発生する強誘電体セラミックと
内部電極材の収縮差が緩和され、層間剥離やクラックの
発生が少なくなりまた共材としてのセラミック粉末を含
まない内部電極層も存在するため、等価直列抵抗を上昇
させることもない。The present invention is characterized in that an internal electrode layer containing a co-material in which ferroelectric ceramic powder is mixed as a co-material is provided between the ferroelectric ceramic layer and the internal electrode layer. As shown in the cross-sectional view of FIG. 2, when the internal electrode layer 3 containing the co-material containing the ferroelectric ceramic powder as the co-material is taken as the intermediate layer between the ferroelectric ceramic layer 2 and the internal electrode layer 1, it occurs during firing. The contraction difference between the ferroelectric ceramic and the internal electrode material is eased, delamination and cracks are reduced, and there is an internal electrode layer that does not contain ceramic powder as a co-material, so the equivalent series resistance can be increased. Absent.
【０００８】[0008]
実施例１。本実施例では、強誘電体セラミック粉末にＰ
ｂ系の複合ペロブスカイト構造をもつ粉末を使用し、内
部電極としてＡｇとＰｄ粉末を７０：３０の割合で混合
したペーストを用いた。又、中間層としての共材入り内
部電極層用ペーストにはＡｇ、Ｐｄ混合粉末に対して、
５ｗｔ％から７５ｗｔ％の範囲で強誘電体セラミック粉
末を混合したペーストを作成し用いた。コンデンサチッ
プ作成は図３に示すように通常のドクターブレードによ
り成膜された強誘電体セラミック層２のグリーンシート
上に共材入り内部電極層３を共材入り内部電極層用ペー
ストを約１μｍ程度の厚みにて内部電極パターンとして
印刷乾燥の後、共材を含まない内部電極用ペーストを約
２μｍ程度の厚みに前記パターンに重ねて印刷、乾燥を
行った。さらに共材入り内部電極層用ペーストを１回目
と同じように印刷、乾燥した。内部電極パターンの位置
合わせは、ピンガイドにて行った。又乾燥は、ドライヤ
ーにて仮乾燥を繰り返しながら行った。このようにして
得られた内部電極用多層膜を有するグリーンシートを５
０枚打ち抜き積層し、加熱プレスにてグリーンの積層体
を形成し、積層体生チップで５×５ｍｍの大きさに切り
出し、脱バインダ、焼成を行い、最終的に外部電極を焼
付けることでコンデンサ素子を得た。本発明の効果を層
間剥離の発生率及び等価直列抵抗の変化率と共材入り内
部電極層の共材の添加量との割合の関係として、図４、
図５に各々示す。５ｗｔ％から６０ｗｔ％の範囲で共材
添加により層間剥離及び等価直列抵抗の双方で改善され
ていることがわかる。Example 1. In this embodiment, P is added to the ferroelectric ceramic powder.
A powder having a b-type composite perovskite structure was used, and a paste prepared by mixing Ag and Pd powder at a ratio of 70:30 was used as an internal electrode. In addition, the internal electrode layer paste containing the common material as the intermediate layer, for Ag, Pd mixed powder,
A paste prepared by mixing the ferroelectric ceramic powder in the range of 5 wt% to 75 wt% was prepared and used. As shown in FIG. 3, the capacitor chip is made by forming the co-material-containing internal electrode layer 3 on the green sheet of the ferroelectric ceramic layer 2 formed by a normal doctor blade with the co-material-containing internal electrode layer paste of about 1 μm. After printing and drying as an internal electrode pattern with a thickness of 1 .mu.m, an internal electrode paste containing no common material was printed on the pattern to a thickness of about 2 .mu.m and dried. Further, the internal electrode layer paste containing a common material was printed and dried in the same manner as the first time. The alignment of the internal electrode pattern was performed with a pin guide. The drying was performed while repeating temporary drying with a dryer. The green sheet having the multilayer film for internal electrodes obtained in this manner
0 capacitors are laminated by punching, a green laminate is formed by heating press, the laminate raw chip is cut into a size of 5 × 5 mm, binder is removed, firing is performed, and finally external electrodes are baked to form a capacitor. The device was obtained. The effect of the present invention is shown in FIG.
Each is shown in FIG. It can be seen that addition of the co-material in the range of 5 wt% to 60 wt% improves both delamination and equivalent series resistance.
【０００９】実施例２。実施例１で述べたプロセスに従
い、コンデンサ素子を得た。ここでも、図３に示すよう
に共材を含まない内部電極層１として実施例１と同様に
Ａｇ／Ｐｄに７０／３０の混合ペーストを用いた。本実
施例２では、実施例１で共材を含んだ共材入り内部電極
層３として用いた強誘電体セラミックよりも高融点の酸
化ジルコニウム（ＺｒＯ2）を共材として用い、Ａｇ／
Ｐｄ混合粉末重量に対して５ｗｔ％から７０ｗｔ％の範
囲の割合でＺｒＯ2粉末を混入させた共材入り内部電極
層用ペーストを調整した。印刷厚みは、それぞれ実施例
１と同様に共材を含まない内部電極層１として約２μ
ｍ、共材入り内部電極層３として１μｍを成膜した。得
られたコンデンサ素子の層間剥離の発生率及び等価直列
抵抗の変化率と共材入り内部電極層の共材の添加量の割
合との関係として、図６、図７に各々示す。５ｗｔ％か
ら６０ｗｔ％の範囲の酸化ジルコニウム添加により層間
剥離及び等価直列抵抗の双方が改善されていることがわ
かる。実施例１及び実施例２で示すように、従来法に比
較して５ｗｔ％から６０ｗｔ％の範囲の共材の添加によ
り不良品の発生率が低くしかも優れた特性の製品を得る
ことができた。又、本実施例で、高融点のセラミックス
としてＺｒＯ2を示したが、他にＭｇＯ、Ａｌ2Ｏ3等の
セラミックスも同様の効果がある。Example 2. A capacitor element was obtained according to the process described in Example 1. Again, as shown in FIG. 3, as the internal electrode layer 1 containing no common material, a mixed paste of Ag / Pd of 70/30 was used as in Example 1. In Example 2, zirconium oxide (ZrO 2 ) having a higher melting point than the ferroelectric ceramic used as the internal electrode layer 3 containing a common material containing the common material in Example 1 was used as a common material, and Ag /
An internal electrode layer paste containing a common material, in which ZrO 2 powder was mixed in a ratio of 5 wt% to 70 wt% with respect to the Pd mixed powder weight, was prepared. The printing thickness was about 2 μm for the internal electrode layer 1 containing no common material as in Example 1.
m, and 1 μm was formed as the internal electrode layer 3 containing a common material. The relationship between the occurrence rate of delamination and the change rate of equivalent series resistance of the obtained capacitor element and the ratio of the additive amount of the co-material of the co-material-containing internal electrode layer are shown in FIGS. 6 and 7, respectively. It can be seen that addition of zirconium oxide in the range of 5 wt% to 60 wt% improves both delamination and equivalent series resistance. As shown in Examples 1 and 2, by adding the additive in the range of 5 wt% to 60 wt% as compared with the conventional method, it was possible to obtain a product having a low defective rate and excellent characteristics. . Further, in the present embodiment, ZrO 2 is shown as the high melting point ceramics, but other ceramics such as MgO and Al 2 O 3 have the same effect.
【００１０】[0010]
【発明の効果】以上、述べたごとく、本発明によれば層
間剥離やクラック発生が少なくかつ等価直列抵抗の小さ
な信頼性の高い積層セラミックコンデンサの歩留よい製
造が可能となった。As described above, according to the present invention, it is possible to manufacture a highly reliable laminated ceramic capacitor with less delamination and cracking and a small equivalent series resistance with high yield.
【図１】一般的な積層セラミックコンデンサの断面図。FIG. 1 is a sectional view of a general monolithic ceramic capacitor.
【図２】従来の積層セラミックコンデンサの強誘電体セ
ラミック層と内部電極層の積層部の拡大断面図。FIG. 2 is an enlarged cross-sectional view of a laminated portion of a ferroelectric ceramic layer and an internal electrode layer of a conventional laminated ceramic capacitor.
【図３】本発明の積層セラミックコンデンサの一例の強
誘電体セラミック層と内部電極層との間に共材入り内部
電極層を有する積層セラミックコンデンサの拡大断面
図。FIG. 3 is an enlarged cross-sectional view of a monolithic ceramic capacitor having an internal electrode layer containing a common material between a ferroelectric ceramic layer and an internal electrode layer, which is an example of the monolithic ceramic capacitor of the present invention.
【図４】実施例１に示す本発明の一実施例の積層セラミ
ックコンデンサにおける共材入り内部電極層の共材の添
加量の割合と層間剥離の発生率の関係を示す図。FIG. 4 is a diagram showing the relationship between the ratio of the additive amount of the co-material of the co-material-containing internal electrode layer and the incidence of delamination in the monolithic ceramic capacitor of the embodiment 1 of the present invention.
【図５】実施例１に示す本発明の一実施例の積層セラミ
ックコンデンサにおける共材入り内部電極層の共材の添
加量の割合と等価直列抵抗の変化率の関係を示す図。FIG. 5 is a graph showing the relationship between the ratio of the additive amount of the co-material-containing internal electrode layer and the change rate of the equivalent series resistance in the monolithic ceramic capacitor of the embodiment 1 of the present invention.
【図６】実施例２に示す本発明の一実施例の積層セラミ
ックコンデンサにおける共材入り内部電極層の共材の添
加量の割合と等価直列抵抗の変化率の関係を示す図。FIG. 6 is a diagram showing a relationship between the ratio of the additive amount of the co-material-containing internal electrode layer and the change rate of the equivalent series resistance in the monolithic ceramic capacitor of the embodiment 1 of the present invention.
【図７】実施例２に示す本発明の一実施例の積層セラミ
ックコンデンサにおける共材入り内部電極層の共材の添
加量の割合と等価直列抵抗の変化率の関係を示す図。FIG. 7 is a diagram showing the relationship between the ratio of the additive amount of the co-material-containing internal electrode layer and the rate of change of the equivalent series resistance in the monolithic ceramic capacitor of the embodiment 1 of the present invention.
１ 内部電極層 ２ 強誘電体セラミック層 ３ 共材入り内部電極層 ４ 外部電極 1 Internal Electrode Layer 2 Ferroelectric Ceramic Layer 3 Internal Electrode Layer with Common Material 4 External Electrode
Claims (2)
なる内部電極層を交互に積層して構成する積層セラミッ
クコンデンサにおいて、強誘電体セラミック層と内部電
極層の間に、前記内部電極を構成する金属重量に対し５
ｗｔ％から６０ｗｔ％の範囲で強誘電体セラミックと同
組成の粉末を共材として混入した共材入り内部電極層を
設けることを特徴とする積層セラミックコンデンサの製
造方法。1. A laminated ceramic capacitor comprising a ferroelectric ceramic layer and an internal electrode layer made of a low resistance metal, which are alternately laminated, wherein the internal electrode is formed between the ferroelectric ceramic layer and the internal electrode layer. 5 for the weight of metal
A method for manufacturing a monolithic ceramic capacitor, comprising: providing an internal electrode layer containing a co-material, in which a powder having the same composition as a ferroelectric ceramic is mixed as a co-material in the range of wt% to 60 wt%.
と低抵抗金属からなる内部電極層との間に設けられる共
材入り内部電極層として、積層セラミックコンデンサを
構成する強誘電体セラミックおよびその強誘電体セラミ
ックよりも高融点のセラミック粉末のうち、少なくとも
１種類以上を混入した内部電極層を設けることを特徴と
する積層セラミックコンデンサの製造方法。2. A ferroelectric ceramic constituting a monolithic ceramic capacitor as an internal electrode layer containing a common material provided between the ferroelectric ceramic layer according to claim 1 and an internal electrode layer made of a low resistance metal, and A method for manufacturing a laminated ceramic capacitor, comprising providing an internal electrode layer containing at least one kind of ceramic powder having a melting point higher than that of the ferroelectric ceramic.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP04893391A JP3241054B2 (en) | 1991-02-21 | 1991-02-21 | Multilayer ceramic capacitor and method of manufacturing the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP04893391A JP3241054B2 (en) | 1991-02-21 | 1991-02-21 | Multilayer ceramic capacitor and method of manufacturing the same |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH05190373A true JPH05190373A (en) | 1993-07-30 |
| JP3241054B2 JP3241054B2 (en) | 2001-12-25 |
Family
ID=12817063
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP04893391A Expired - Fee Related JP3241054B2 (en) | 1991-02-21 | 1991-02-21 | Multilayer ceramic capacitor and method of manufacturing the same |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3241054B2 (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4813629A (en) * | 1987-03-06 | 1989-03-21 | Daiwa Seiko, Inc. | Fishing reel having a waterproof drag mechanism |
| KR100714129B1 (en) * | 2005-12-08 | 2007-05-02 | 한국전자통신연구원 | Low temperature co-fired ceramic multilayer type microwave tunable device and method of fabricating the same device |
| US7518849B2 (en) | 2006-03-31 | 2009-04-14 | Tdk Corporation | Multilayer electronic device and the production method |
| JP2009170848A (en) * | 2008-01-21 | 2009-07-30 | Taiyo Yuden Co Ltd | Ceramic electronic component and its manufacturing method |
| US20170011850A1 (en) * | 2015-07-06 | 2017-01-12 | Samsung Electro-Mechanics Co., Ltd. | Multilayer ceramic electronic component |
| JP2017120871A (en) * | 2015-12-28 | 2017-07-06 | サムソン エレクトロ−メカニックス カンパニーリミテッド． | Multilayer ceramic electronic component and manufacturing method of the same |
| US11955286B2 (en) | 2020-11-19 | 2024-04-09 | Samsung Electro-Mechanics Co., Ltd. | Multilayered electronic component and method of manufacturing the same |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6410138B2 (en) | 1997-09-30 | 2002-06-25 | Kimberly-Clark Worldwide, Inc. | Crimped multicomponent filaments and spunbond webs made therefrom |
-
1991
- 1991-02-21 JP JP04893391A patent/JP3241054B2/en not_active Expired - Fee Related
Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4813629A (en) * | 1987-03-06 | 1989-03-21 | Daiwa Seiko, Inc. | Fishing reel having a waterproof drag mechanism |
| KR100714129B1 (en) * | 2005-12-08 | 2007-05-02 | 한국전자통신연구원 | Low temperature co-fired ceramic multilayer type microwave tunable device and method of fabricating the same device |
| US7518849B2 (en) | 2006-03-31 | 2009-04-14 | Tdk Corporation | Multilayer electronic device and the production method |
| JP2009170848A (en) * | 2008-01-21 | 2009-07-30 | Taiyo Yuden Co Ltd | Ceramic electronic component and its manufacturing method |
| CN106340385A (en) * | 2015-07-06 | 2017-01-18 | 三星电机株式会社 | Multilayer ceramic electronic component |
| KR20170005645A (en) * | 2015-07-06 | 2017-01-16 | 삼성전기주식회사 | Multi-layered ceramic electronic component |
| US20170011850A1 (en) * | 2015-07-06 | 2017-01-12 | Samsung Electro-Mechanics Co., Ltd. | Multilayer ceramic electronic component |
| US10262795B2 (en) * | 2015-07-06 | 2019-04-16 | Samsung Electro-Mechanics Co., Ltd. | Multilayer ceramic electronic component including ceramic-metal compound layers |
| CN106340385B (en) * | 2015-07-06 | 2019-06-04 | 三星电机株式会社 | Multilayer ceramic electronic component |
| JP2017120871A (en) * | 2015-12-28 | 2017-07-06 | サムソン エレクトロ−メカニックス カンパニーリミテッド． | Multilayer ceramic electronic component and manufacturing method of the same |
| KR20170077542A (en) * | 2015-12-28 | 2017-07-06 | 삼성전기주식회사 | Multi-layered ceramic electronic component and method for manufacturing the same |
| JP2022009433A (en) * | 2015-12-28 | 2022-01-14 | サムソン エレクトロ－メカニックス カンパニーリミテッド． | Multilayer ceramic electronic component and manufacturing method thereof |
| US11955286B2 (en) | 2020-11-19 | 2024-04-09 | Samsung Electro-Mechanics Co., Ltd. | Multilayered electronic component and method of manufacturing the same |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3241054B2 (en) | 2001-12-25 |
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| LAPS | Cancellation because of no payment of annual fees |