JPH05182858A - Manufacture of laminated ceramic capacitor - Google Patents

Manufacture of laminated ceramic capacitor

Info

Publication number
JPH05182858A
JPH05182858A JP35794491A JP35794491A JPH05182858A JP H05182858 A JPH05182858 A JP H05182858A JP 35794491 A JP35794491 A JP 35794491A JP 35794491 A JP35794491 A JP 35794491A JP H05182858 A JPH05182858 A JP H05182858A
Authority
JP
Japan
Prior art keywords
slits
capacitor element
capacitor
divided
electrodes
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP35794491A
Other languages
Japanese (ja)
Inventor
Fujio Makuta
富士雄 幕田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sumitomo Metal Mining Co Ltd
Original Assignee
Sumitomo Metal Mining Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sumitomo Metal Mining Co Ltd filed Critical Sumitomo Metal Mining Co Ltd
Priority to JP35794491A priority Critical patent/JPH05182858A/en
Publication of JPH05182858A publication Critical patent/JPH05182858A/en
Pending legal-status Critical Current

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  • Ceramic Capacitors (AREA)

Abstract

PURPOSE:To form outer electrodes and to facilitate marking by forming slits on a laminated block, providing, after baking, marking, dividing it into element rows to form the outer electrodes, and eventually separating it into capacitor element units. CONSTITUTION:Slits 4 of V-shaped section to be divided into capacitor element units are provided on one surface of a laminated block 3 in which many capacitor structures are formed longitudinally and laterally of a green sheet 1 of dielectric ceramics and paste of inner electrodes 2. The block is baked, marks 5 are formed of paste for marking on all capacitor element zones on the surface provided with the slits 4. Then, it is so divided in one of row or column direction of the slits as to expose the electrodes 2. The obtained capacitor element rows 6 are coated with paste for outer electrodes, and baked to form the outer electrodes 7. Thereafter, it is divided into capacitor element units via the slits between the elements to be separated.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、誘電体セラミックと内
部電極が交互に積層された構造を有する積層セラミック
コンデンサの製造方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a monolithic ceramic capacitor having a structure in which dielectric ceramics and internal electrodes are alternately laminated.

【0002】[0002]

【従来の技術】積層セラミックコンデンサは、最上層と
最下層がセラミック層となるようにセラミックと内部電
極が交互に積層されて直方体が形成され、内部電極の端
部が直方体の一方の端面と反対側の端面に交互に露出す
るようにされ、この両端それぞれに外部電極が形成され
たものである。このような積層セラミックコンデンサ
は、同体積の別種コンデンサに比べて大容量を得ること
ができるので、種々の電子機器に使用されている。
2. Description of the Related Art A monolithic ceramic capacitor has a rectangular parallelepiped formed by alternately laminating ceramics and internal electrodes so that the uppermost layer and the lowermost layer are ceramic layers, and the end of the internal electrode is opposite to one end face of the rectangular parallelepiped. The external electrodes are alternately exposed on the side end surfaces, and external electrodes are formed on both ends of the external electrodes. Since such a monolithic ceramic capacitor can obtain a large capacity as compared with another type of capacitor having the same volume, it is used in various electronic devices.

【0003】従来の積層セラミックコンデンサは通常、
誘電体セラミックのグリーンシートの表面に複数行、複
数列のパターンで例えばPdを主成分とする内部電極用
ペーストを塗布、乾燥し、各コンデンサ素子に分離した
時に内部電極が交互に端部が露出するようにして複数枚
重ね、さらにこの積層体の上面と下面に補強用のグリー
ンシートを複数枚重ね、加熱して圧着したブロック状の
積層体(以後積層ブロックと略す)とし、各コンデンサ
素子単位に切断し、このチップ状のコンデンサ素子を焼
成し、切断した端面の各エッジを面取りし、例えばAg
を主成分とする外部電極用ペーストをチップの内部電極
が露出する両端に塗布、焼成して外部電極を形成し、さ
らに、各コンデンサ素子の表面に静電容量などを表示す
るマークを施すという方法で製造されている。
Conventional monolithic ceramic capacitors are usually
For example, an internal electrode paste mainly composed of Pd is applied in a pattern of a plurality of rows and a plurality of columns on the surface of a dielectric ceramic green sheet, dried, and the end portions of the internal electrodes are alternately exposed when separated into each capacitor element. In this way, a plurality of stacked green sheets are stacked on top of each other, and a plurality of reinforcing green sheets are stacked on the upper surface and the lower surface of the stacked body. The chip-shaped capacitor element is fired, and each edge of the cut end face is chamfered.
A method in which a paste for external electrodes containing as a main component is applied to both ends of the chip where the internal electrodes are exposed and fired to form external electrodes, and a mark indicating capacitance etc. is provided on the surface of each capacitor element. Is manufactured in.

【0004】しかしながら、従来の製造方法において
は、例えば縦3.2mm、横1.6mmという小さいサイズ
のコンデンサ素子単位に切断して焼成し、外部電極を形
成するため、取り扱いに大変手数を要する。また、マー
キングにおいても同様に手数がかかっていた。何れの欠
点も積層セラミックコンデンサの生産性向上に制約とな
っており、この改善が強く要請されている。
However, in the conventional manufacturing method, the external electrodes are formed by cutting into small capacitor element units having a size of 3.2 mm in length and 1.6 mm in width and firing to form external electrodes. In addition, marking is also troublesome. Each of these drawbacks is a constraint on improving the productivity of the monolithic ceramic capacitor, and there is a strong demand for this improvement.

【0005】[0005]

【発明が解決しようとする課題】本発明は、従来の欠点
を解消して、外部電極の形成、マーキングを容易に行う
ことができ、生産性を著しく向上させ得る積層セラミッ
クコンデンサの製造方法を提供することを目的とする。
DISCLOSURE OF THE INVENTION The present invention provides a method of manufacturing a monolithic ceramic capacitor which solves the drawbacks of the prior art, facilitates formation and marking of external electrodes, and can significantly improve productivity. The purpose is to do.

【0006】[0006]

【課題を解決するための手段】上記目的を達成するため
に本発明の方法は、誘電体セラミックのグリーンシート
と内部電極用ペーストにより多数のコンデンサ構造が縦
横に形成された積層ブロックの一方の表面に、各コンデ
ンサ素子単位に区分する断面がV字状のスリットを施
し、該ブロックを焼成し、スリットの施された表面の全
てのコンデンサ素子区画にマーキング用ペーストにより
マークを施し、次いで内部電極が露出する様にスリット
の行または列方向のうち何れか一方向に分割を行い、得
られた各コンデンサ素子列に外部電極用ペーストを塗
布、焼成して外部電極を形成した後、素子と素子の間の
スリットで各コンデンサ素子単位に分割して分離する点
に特徴がある。
In order to achieve the above object, the method of the present invention is one surface of a laminated block in which a large number of capacitor structures are formed vertically and horizontally by a dielectric ceramic green sheet and an internal electrode paste. A slit having a V-shaped cross section for dividing each capacitor element unit is formed, the block is fired, all the capacitor element sections on the slit surface are marked with a marking paste, and then the internal electrodes are Divide into either the row direction or the column direction of the slit so that it is exposed, and apply the external electrode paste to each obtained capacitor element column and fire it to form the external electrode. It is characterized in that it is divided into each capacitor element unit by the slit between them and separated.

【0007】図1は本発明法の各工程を概念的に説明す
る図である。先ず(a)に示すように、グリーンシート
1にPdを主成分とするペーストにより内部電極2を印
刷する。次いで(b)のようにこれらグリーンシートを
複数層積み重ね、最上層には内部電極用ペーストが印刷
されていないグリーンシートを重ね、加熱して圧着する
ことにより積層ブロック3を作成し、該積層ブロック3
の表面に、各コンデンサ素子単位に区分するようにスリ
ット4を施す。
FIG. 1 is a diagram conceptually explaining each step of the method of the present invention. First, as shown in (a), the internal electrodes 2 are printed on the green sheet 1 with a paste containing Pd as a main component. Next, as shown in (b), a plurality of layers of these green sheets are stacked, a green sheet on which the internal electrode paste is not printed is stacked on the uppermost layer, and the stacked block 3 is prepared by heating and press-bonding the stacked green block. Three
Slits 4 are provided on the surface of the capacitor so as to be divided into each capacitor element unit.

【0008】このスリット入り積層ブロック3を焼成
し、(c)に示すようにマーキング用のガラスペースト
をスクリーン印刷し、焼成することによりこのブロック
上の全てのコンデンサ素子区画にマーク5を施す。
The laminated block with slits 3 is fired, and a glass paste for marking is screen-printed as shown in FIG. 3C, and fired to mark 5 on all the capacitor element sections on this block.

【0009】続いて(d)に示すように、内部電極の端
部が露出するようにスリットの行または列方向のうち何
れかの一方向に分割を行い、コンデンサ素子が一列に並
んだ素子列6を得る。この素子列6の内部電極の露出し
た両端面に、Agを主成分とする外部電極ペーストを塗
布、焼成して外部電極7を形成する。
Subsequently, as shown in (d), the slits are divided in one of the row direction and the column direction of the slits so that the end portions of the internal electrodes are exposed, and the element rows in which the capacitor elements are arranged in a row. Get 6. The external electrode paste containing Ag as a main component is applied to both exposed end surfaces of the internal electrodes of the element array 6 and fired to form the external electrodes 7.

【0010】最後に前記素子列6の素子と素子の間のス
リットで各コンデンサ素子単位に分割して分離すれば、
(e)に示すように、マーキングされ、外部電極の形成
された積層セラミックコンデンサ8を得ることが出来
る。
Finally, if the slits between the elements of the element array 6 are divided into individual capacitor elements and separated,
As shown in (e), it is possible to obtain a laminated ceramic capacitor 8 which is marked and has external electrodes formed thereon.

【0011】[0011]

【作用】本発明法によれば、マーキングは積層ブロック
の状態で行うことになり、極めて作業性が改善される。
又、外部電極の形成を素子列単位で行なうことができ、
取り扱いが容易である上、効率的である。
According to the method of the present invention, the marking is performed in the state of the laminated block, and the workability is remarkably improved.
In addition, the external electrodes can be formed in each element row unit,
It is easy to handle and efficient.

【0012】[0012]

【実施例】厚さ約35μmのBaTiO3 を主成分とす
る乳白色のグリーンシートを一片約25mmの正方形に切
断したものを30枚用意し、このうち10枚に内部電極
用Pdペーストを図2に示すようなパターンを持つ内部
電極印刷用のスクリーンを用いて印刷し、80℃で18
0秒間乾燥させ、水平面内で交互に180度ずつ回転さ
せ積層する。この積層体の上下に内部電極を印刷してい
ないグリーンシートを10枚ずつ積層し、合計30枚の
グリーンシートを積層する。これを約80℃に温められ
たモールド中で、約200kg/cm2 の圧力をかけ、約6
0秒保持する。ここまでの作業により、およその大きさ
が縦25mm横25mm厚さ1100μmの積層ブロックを
作成する。
[Example] 30 milky white green sheets containing BaTiO 3 as a main component having a thickness of about 35 μm were cut into squares each having a size of about 25 mm, and 30 sheets were prepared. Print using a screen for internal electrode printing with the pattern shown, and
It is dried for 0 seconds, and alternately rotated by 180 degrees in a horizontal plane to be laminated. Ten green sheets on which the internal electrodes are not printed are laminated on the upper and lower sides of this laminated body, and a total of 30 green sheets are laminated. In a mold heated to about 80 ° C, apply a pressure of about 200 kg / cm 2 to about 6
Hold for 0 seconds. By the operations up to this point, a laminated block having a size of 25 mm in length and 25 mm in width and 1100 μm in thickness is prepared.

【0013】この積層ブロックの表面に、各コンデンサ
素子単位に区分するように鋭い刃物でV字形、深さ約1
00μmのスリットを施す。これを1300℃で2時間
保持するような温度プロファイルで焼成する。積層ブロ
ックは焼成されたことにより茶褐色になり、焼結収縮を
起こし、サイズはおよそ縦20mm、横20mm、厚さ65
0μmとなる。
On the surface of this laminated block, a V-shape with a sharp blade and a depth of about 1 is used to divide each capacitor element unit.
A slit of 00 μm is formed. This is fired with a temperature profile that holds it at 1300 ° C. for 2 hours. The laminated block turns brown when fired, causing sintering shrinkage, and the size is about 20 mm in length, 20 mm in width, and 65 in thickness.
It becomes 0 μm.

【0014】次に、マーキング用の黒色ガラスペースト
を、スリットを入れた方の表面にスクリーン印刷する。
このとき、区分された素子の全てに一度に印刷を行う。
120℃10分間の乾燥を行い、800℃で10分間の
焼成を行い、マーキングを完了した。
Next, a black glass paste for marking is screen-printed on the surface having slits.
At this time, printing is performed at once on all the divided elements.
The marking was completed by drying at 120 ° C. for 10 minutes and baking at 800 ° C. for 10 minutes.

【0015】次に内部電極の端部が露出するようにスリ
ットの行または列方向のうち何れかの一方向に分割を行
い、内部電極が露出している表面に外部電極用Agペー
ストを塗布し、120℃10分間の乾燥を行い、800
℃で10分間の焼成を行い、外部電極を形成した。
Next, the slit is divided in one of the row and column directions of the slit so that the end of the internal electrode is exposed, and the Ag paste for the external electrode is applied to the surface where the internal electrode is exposed. , Dry at 120 ℃ for 10 minutes, then 800
The external electrodes were formed by firing at 10 ° C. for 10 minutes.

【0016】最後に素子と素子の間のスリットで各コン
デンサ素子単位に分割を行い、およそ縦3.2mm、横
2.5mmサイズの積層セラミックコンデンサ18個を得
た。
Finally, the slits between the elements were divided into individual capacitor elements to obtain 18 monolithic ceramic capacitors each having a length of 3.2 mm and a width of 2.5 mm.

【0017】[0017]

【発明の効果】以上、詳細に説明した様に、本発明の積
層セラミックコンデンサの製造方法によれば、マーキン
グおよび外部電極の形成を容易にすることが出来る。
As described above in detail, according to the method for manufacturing a laminated ceramic capacitor of the present invention, the marking and the formation of the external electrode can be facilitated.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明にかかる積層セラミックコンデンサの製
造方法の各工程を概念的に説明する図である。
FIG. 1 is a diagram conceptually explaining each step of the method for manufacturing a monolithic ceramic capacitor according to the present invention.

【図2】実施例にて用いた内部電極パターンを示す。FIG. 2 shows internal electrode patterns used in Examples.

【符号の説明】[Explanation of symbols]

1 グリーンシート 2 内部電極用ペースト 3 積層ブロック 4 スリット 5 マーク 6 素子列 7 外部電極 8 積層セラミックコンデンサ 1 Green Sheet 2 Internal Electrode Paste 3 Multilayer Block 4 Slit 5 Mark 6 Element Row 7 External Electrode 8 Multilayer Ceramic Capacitor

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 最上層と最下層がセラミック層となるよ
うにセラミックと内部電極が交互に積層されて直方体が
形成され、内部電極の端部が直方体の一方の端面と反対
側の端面に交互に露出するようにされ、この両端にそれ
ぞれ外部電極が形成された積層セラミックコンデンサを
製造する方法において、誘電体セラミックのグリーンシ
ートと内部電極用ペーストにより多数のコンデンサ構造
が縦横に形成された積層ブロックの一方の表面に、各コ
ンデンサ素子単位に区分するスリットを施し、該ブロッ
クを焼成し、スリットの施された表面の全てのコンデン
サ素子区画にマーキング用ペーストによりマークを施
し、内部電極が露出する様にスリットの行または列方向
の何れか一方向に分割を行い、得られた各コンデンサ素
子列に外部電極用ペーストを塗布、焼成して電極を形成
した後、素子と素子の間のスリットで各コンデンサ素子
単位に分割して分離することを特徴とする積層セラミッ
クコンデンサの製造方法。
1. A rectangular parallelepiped is formed by alternately stacking ceramics and internal electrodes such that the uppermost layer and the lowermost layer are ceramic layers, and the end portions of the internal electrodes are alternately arranged on one end surface and the opposite end surface of the rectangular parallelepiped. In a method of manufacturing a laminated ceramic capacitor in which external electrodes are formed on both ends of the laminated ceramic capacitor, a multilayer block in which a large number of capacitor structures are formed vertically and horizontally by a dielectric ceramic green sheet and an internal electrode paste. Slits for dividing each capacitor element unit are provided on one surface, the block is baked, all capacitor element sections on the slitted surface are marked with a marking paste so that the internal electrodes are exposed. The slits are divided in either the row or column direction of the slits, and each capacitor element column is divided into rows for external electrodes. A method for manufacturing a monolithic ceramic capacitor, characterized in that after forming an electrode by applying a strike and firing the electrode, a slit between elements is divided into individual capacitor element units for separation.
JP35794491A 1991-12-27 1991-12-27 Manufacture of laminated ceramic capacitor Pending JPH05182858A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP35794491A JPH05182858A (en) 1991-12-27 1991-12-27 Manufacture of laminated ceramic capacitor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP35794491A JPH05182858A (en) 1991-12-27 1991-12-27 Manufacture of laminated ceramic capacitor

Publications (1)

Publication Number Publication Date
JPH05182858A true JPH05182858A (en) 1993-07-23

Family

ID=18456747

Family Applications (1)

Application Number Title Priority Date Filing Date
JP35794491A Pending JPH05182858A (en) 1991-12-27 1991-12-27 Manufacture of laminated ceramic capacitor

Country Status (1)

Country Link
JP (1) JPH05182858A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0876089A2 (en) * 1997-03-28 1998-11-04 TDK Corporation Method for judging the propriety of cutting position on laminated board and laminated ceramic electronic part
JP2006351821A (en) * 2005-06-16 2006-12-28 Matsushita Electric Ind Co Ltd Manufacturing method of stacked ceramic electronic component

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0876089A2 (en) * 1997-03-28 1998-11-04 TDK Corporation Method for judging the propriety of cutting position on laminated board and laminated ceramic electronic part
JP2006351821A (en) * 2005-06-16 2006-12-28 Matsushita Electric Ind Co Ltd Manufacturing method of stacked ceramic electronic component

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