JPH10106887A - Monolithic ceramic capacitor array - Google Patents

Monolithic ceramic capacitor array

Info

Publication number
JPH10106887A
JPH10106887A JP27410296A JP27410296A JPH10106887A JP H10106887 A JPH10106887 A JP H10106887A JP 27410296 A JP27410296 A JP 27410296A JP 27410296 A JP27410296 A JP 27410296A JP H10106887 A JPH10106887 A JP H10106887A
Authority
JP
Japan
Prior art keywords
internal electrode
capacitor array
pattern
internal
external electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP27410296A
Other languages
Japanese (ja)
Inventor
Koji Amano
弘司 天野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Rohm Co Ltd
Original Assignee
Rohm Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Rohm Co Ltd filed Critical Rohm Co Ltd
Priority to JP27410296A priority Critical patent/JPH10106887A/en
Publication of JPH10106887A publication Critical patent/JPH10106887A/en
Pending legal-status Critical Current

Links

Abstract

PROBLEM TO BE SOLVED: To enlarge the range of use or application, by causing the area of effective overlap portions of internal electrode patterns connected to one external electrode and corresponding internal electrode patterns connected to the other external electrode to differ from one another. SOLUTION: A dielectric material 6 made of BaTiO3 , or the like is molded on a dielectric ceramic sheet, and internal electrodes 2a, 2b are printed on the sheet by a screen printing method. In this case, using a screen mask in which the area of a printing pattern to be used is varied, one internal electrode pattern 2a and the other internal electrode pattern 2b are printed. Thus, after a predetermined numlrer of intenal electrodes are stacked, heated, pressurized, and then cut into a size for four elements by using a blade, the internal electrodes are fired at 1000 to 100 deg.C. Then, end portions of the internal electrodes are exposed, coated with an external electrode 4, and fired at 800 deg.C. Thus, by varying values A1 to A4 of the area of an effective overlap portion in individual patterns C1 to C4 , a capacitance of C1 ≠C2 ≠C3 ≠C4 may be provided.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は積層セラミックコン
デンサに関する。更に詳細には、本発明は各素子の静電
容量が異なる積層セラミックコンデンサアレイに関す
る。
The present invention relates to a multilayer ceramic capacitor. More specifically, the present invention relates to a multilayer ceramic capacitor array in which each element has a different capacitance.

【0002】[0002]

【従来の技術】積層セラミックコンデンサはその実装効
率の高さから、最近の小型電子機器類で多用されてい
る。
2. Description of the Related Art Multilayer ceramic capacitors are widely used in recent small electronic devices because of their high mounting efficiency.

【0003】図2は従来の積層セラミックコンデンサア
レイ10の平面透視図である。図3は図2におけるII−
II線に沿った断面図である。図2及び図3において、符
号12a,12bは、外部電極14に接続された内部電
極を示し、16は誘電体を示す。
FIG. 2 is a plan perspective view of a conventional multilayer ceramic capacitor array 10. FIG. FIG. 3 shows II- in FIG.
FIG. 2 is a sectional view taken along line II. 2 and 3, reference numerals 12a and 12b indicate internal electrodes connected to the external electrodes 14, and reference numeral 16 indicates a dielectric.

【0004】積層セラミックコンデンサアレイは一般的
に、スクリーン印刷法を用いて誘電体グリーンシート上
に12a及び12bの内部電極を印刷して、これをn枚
積み重ねて生素体を作成する。内部電極12a及び12
bパターンの重複部の面積Aが静電容量を得る有効部で
あり、内部電極をn層積層することにより目的の静電容
量を得る。隣接する各コンデンサ素子C1〜C4は誘電体
16により絶縁隔離され、全体でコンデンサアレイを構
成する。
In general, a multilayer ceramic capacitor array is formed by printing internal electrodes 12a and 12b on a dielectric green sheet using a screen printing method, and stacking n pieces of these to form a green body. Internal electrodes 12a and 12
The area A of the overlapping portion of the b-pattern is an effective portion for obtaining a capacitance, and a desired capacitance is obtained by stacking n layers of internal electrodes. Each of the adjacent capacitor elements C 1 to C 4 is insulated and isolated by the dielectric 16 and forms a capacitor array as a whole.

【0005】静電容量は下記の様に算出して、目的の容
量を得る。 Cap=(ε・A・n)/t (式中、εは誘電率であり、Aは有効部面積であり、n
は有効部枚数であり、tは誘電体の厚さである)しか
し、この場合、図2のコンデンサアレイにおいては、C
ap(静電容量)はC1≒C2≒C3≒C4となる。
[0005] The capacitance is calculated as follows to obtain a desired capacitance. Cap = (ε · A · n) / t (where, ε is a dielectric constant, A is an effective area, and n
Is the number of effective parts, and t is the thickness of the dielectric.) However, in this case, in the capacitor array of FIG.
The ap (capacitance) is C 1 ≒ C 2 ≒ C 3 ≒ C 4 .

【0006】前記のように、図2に示されるようなコン
デンサアレイでは、C1≒C2≒C3≒C4であり、各素子
は同一の静電容量である。このようなコンデンサアレイ
の場合、誘電体の上下の両表面に内部電極を設けている
ので、同じ厚さ(t)の同じ誘電体を同じ有効部面積
(A)で用いる限り、素子毎に様々な静電容量を作り出
すことができないという問題がある。しかし、使用する
回路によっては、C1≠C2≠C3≠C4を必要とする場合
もある。
As described above, in the capacitor array as shown in FIG. 2, C 1 ≒ C 2 ≒ C 3 ≒ C 4 , and each element has the same capacitance. In such a capacitor array, the internal electrodes are provided on both upper and lower surfaces of the dielectric, so that as long as the same dielectric having the same thickness (t) and the same effective area (A) is used, there are various elements for each element. There is a problem that it is not possible to create a large capacitance. However, C 1 ≠ C 2 ≠ C 3 ≠ C 4 may be required depending on the circuit used.

【0007】[0007]

【発明が解決しようとする課題】従って、本発明の目的
は、同じ大きさの同じ誘電体を用いても静電容量を様々
な値に設計でき、例えば、C1≠C2≠C3≠C4を有する
積層セラミックコンデンサアレイを提供することであ
る。
SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to make it possible to design the capacitance to various values even when the same dielectric material having the same size is used, for example, C 1 ≠ C 2 ≠ C 3 ≠ to provide a multilayer ceramic capacitor array having a C 4.

【0008】[0008]

【課題を解決するための手段】前記課題は、セラミック
誘電体層と、該セラミック誘電体層の同一平面上に配置
された複数個の内部電極層とが交互に積層され、略直方
体の形状を有し、該直方体の対向する二側面にそれぞ
れ、前記内部電極層と接続された外部電極を有する積層
セラミックコンデンサにおいて、一方の外部電極に接続
された各内部電極パターンと他方の外部電極に接続され
た対応する各内部電極パターンとの重複有効部面積とが
相互に異なることを特徴とする積層セラミックコンデン
サアレイにより解決される。
According to the present invention, a ceramic dielectric layer and a plurality of internal electrode layers arranged on the same plane of the ceramic dielectric layer are alternately laminated to form a substantially rectangular parallelepiped shape. In the multilayer ceramic capacitor having external electrodes connected to the internal electrode layers on two opposing side surfaces of the rectangular parallelepiped, each internal electrode pattern connected to one external electrode and the other external electrode are connected to the other external electrode. In addition, the present invention is solved by a multilayer ceramic capacitor array characterized in that the overlapping effective area with each corresponding internal electrode pattern is different from each other.

【0009】[0009]

【発明の実施の形態】図1は本発明による積層セラミッ
クコンデンサアレイ1の一例の平面透視図である。Ba
TiO3等からなる誘電体材料6を既知の方法で誘電体
セラミックシートに成形し、このシート上に内部電極2
a,2bをスクリーン印刷法により印刷する。この際、
使用する印刷パターンの面積を変えたスクリーンマスク
を用いて、一方の内部電極パターン2aと他方の内部電
極パターン2bを印刷する。例えば、一方の内部電極パ
ターン2aは全て同じ長さに印刷し、他方の内部電極パ
ターン2bはそれぞれ異なる長さに印刷する。このよう
にして所定の枚数の内部電極を積層して加熱、加圧し、
その後、4素子分のサイズに剃刀を用いて切断する。そ
の後、1000℃〜1300℃程度の温度で焼成する。
焼成後、研磨又はサンドブラスト処理して内部電極の端
部を露出させ、この内部電極露出面に外部電極4をディ
ップ印刷法により塗布し、800℃で焼成して形成し
た。外部電極は例えば、厚膜Agペースト又は厚膜Ag
/Pdペーストにより形成することができる。更に、常
法により外部電極の外表面にNi及びSn/Pbのメッ
キを施す。
FIG. 1 is a perspective plan view of an example of a multilayer ceramic capacitor array 1 according to the present invention. Ba
A dielectric material 6 made of TiO 3 or the like is formed into a dielectric ceramic sheet by a known method.
a and 2b are printed by the screen printing method. On this occasion,
One internal electrode pattern 2a and the other internal electrode pattern 2b are printed using a screen mask in which the area of the print pattern used is changed. For example, one internal electrode pattern 2a is printed at the same length, and the other internal electrode pattern 2b is printed at a different length. In this way, a predetermined number of internal electrodes are laminated, heated and pressed,
After that, it is cut into a size of four elements using a razor. Thereafter, firing is performed at a temperature of about 1000 ° C. to 1300 ° C.
After firing, the end of the internal electrode was exposed by polishing or sandblasting, and the external electrode 4 was applied to the exposed surface of the internal electrode by dip printing, and fired at 800 ° C. to form the electrode. The external electrode is, for example, a thick film Ag paste or a thick film Ag.
/ Pd paste. Further, the outer surfaces of the external electrodes are plated with Ni and Sn / Pb by a conventional method.

【0010】前記のように、一方の内部電極パターン2
aと他方の内部電極パターン2bとの重複有効部面積が
それぞれのパターンで異なる。すなわち、各パターンC
1〜C4における重複有効部面積の値A1〜A4を変えるこ
とにより、同一積層枚数及び同一誘電体厚さにあって、
1≠C2≠C3≠C4の静電容量を得ることができる。
As described above, one internal electrode pattern 2
a and the other internal electrode pattern 2b have different overlapping effective area for each pattern. That is, each pattern C
By changing the value A 1 to A 4 of the overlapping effective portion area in 1 -C 4, In the same lamination number and the same dielectric thickness,
The capacitance of C 1 1C 2 ≠ C 3 ≠ C 4 can be obtained.

【0011】従来のコンデンサアレイと異なり、本発明
のコンデンサではアレイの各素子の静電容量が変えられ
ることにより、使用範囲又は用途が拡大される。例え
ば、各素子の静電容量が異なるので1個で、同じ各静電
容量を有するコンデンサ4個と同じ機能を発揮すること
ができる。従って、各静電容量を有するコンデンサ4個
を実装するのに対し、本発明のコンデンサアレイは1個
だけ実装すればよいので、実装速度が4倍になる。
Unlike the conventional capacitor array, in the capacitor of the present invention, the range of use or application can be expanded by changing the capacitance of each element of the array. For example, since the capacitance of each element is different, one element can exhibit the same function as four capacitors having the same capacitance. Therefore, the mounting speed is quadrupled because only one capacitor array of the present invention needs to be mounted while four capacitors having each capacitance are mounted.

【0012】更に、従来の各静電容量を有するコンデン
サを4個実装する場合、各コンデンサ間にスペースを設
けなければならなかったが、本発明のコンデンサアレイ
によれば1個実装するだけでよいので、基板上の実装空
間を大幅に節約することができる。
Furthermore, when four conventional capacitors having respective capacitances are mounted, a space has to be provided between the capacitors. However, according to the capacitor array of the present invention, only one mounting is required. Therefore, the mounting space on the substrate can be greatly reduced.

【0013】一方の内部電極パターン2aと他方の内部
電極パターン2bとの重複有効部面積を変える方法は、
(1)同じ幅のパターン2aとパターン2bとを用い、
このパターン2aとパターン2bとを長さ方向(又は突
込み方向)で変化させることにより重複有効部面積を変
えるか、(2)長さは同一であるが、幅が異なるパター
ン2aとパターン2bとを用いることにより、すなわち
幅方向を変化させることにより重複有効部面積を変える
か、又は(3)長さ及び幅を適宜変化させたパターン2
aとパターン2bとを用いることにより重複有効部面積
を変える、ことの3つの方法がある。本発明のコンデン
サアレイでは何れの方法も使用できる。
The method of changing the overlapping effective area of one internal electrode pattern 2a and the other internal electrode pattern 2b is as follows.
(1) Using the pattern 2a and the pattern 2b having the same width,
The overlapping effective portion area is changed by changing the pattern 2a and the pattern 2b in the length direction (or the protruding direction), or (2) the pattern 2a and the pattern 2b having the same length but different widths are used. The pattern 2 in which the overlapping effective area is changed by using, that is, changing the width direction, or (3) the length and the width are appropriately changed
a and the pattern 2b to change the overlapping effective area. Either method can be used in the capacitor array of the present invention.

【0014】[0014]

【実施例】誘電率ε=10.000,誘電体厚さt=1
4μm、有効層数n=18において、長さ方向のみ変動
させることにより重複有効部面積Aを変えた素子C1
2,C3及びC4を作成し、各素子の静電容量を測定し
た。結果を下記の表1に要約して示す。
DESCRIPTION OF THE PREFERRED EMBODIMENTS Dielectric constant ε = 10000, dielectric thickness t = 1
At 4 μm and the number of effective layers n = 18, the element C 1 , in which the overlapping effective area A was changed by changing only the length direction,
C 2 , C 3 and C 4 were prepared, and the capacitance of each element was measured. The results are summarized in Table 1 below.

【0015】[0015]

【表1】 [Table 1]

【0016】[0016]

【発明の効果】以上説明したように、本発明のコンデン
サアレイでは各素子の静電容量が変えられることによ
り、使用範囲又は用途が拡大される。例えば、4個の各
素子の静電容量が異なるのでアレイ1個で、同じ各静電
容量を有するコンデンサ4個と同じ機能を発揮すること
ができる。従って、各静電容量を有するコンデンサ4個
を実装するのに対し、本発明のコンデンサアレイは1個
だけ実装すればよいので、実装速度が4倍になる。更
に、従来の各静電容量を有するコンデンサを4個実装す
る場合、各コンデンサ間にスペースを設けなければなら
なかったが、本発明のコンデンサアレイによれば1個実
装するだけでよいので、基板上の実装空間を大幅に節約
することができる。
As described above, in the capacitor array of the present invention, the range of use or application can be expanded by changing the capacitance of each element. For example, since the capacitance of each of the four elements is different, one array can exhibit the same function as four capacitors having the same capacitance. Therefore, the mounting speed is quadrupled because only one capacitor array of the present invention needs to be mounted while four capacitors having each capacitance are mounted. Furthermore, when four conventional capacitors having respective capacitances are mounted, a space must be provided between the capacitors. However, according to the capacitor array of the present invention, only one mounting is required. The above mounting space can be greatly saved.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の積層セラミックコンデンサアレイの一
例の平面透視図である。
FIG. 1 is a plan perspective view of an example of a multilayer ceramic capacitor array of the present invention.

【図2】従来の積層セラミックコンデンサアレイの一例
の平面透視図である。
FIG. 2 is a plan perspective view of an example of a conventional multilayer ceramic capacitor array.

【図3】図2におけるII-II線に沿った断面図である。FIG. 3 is a sectional view taken along the line II-II in FIG.

【符号の説明】[Explanation of symbols]

1 積層セラミックコンデンサ 2a,2b 内部電極 4 外部電極 6 誘電体 DESCRIPTION OF SYMBOLS 1 Multilayer ceramic capacitor 2a, 2b Internal electrode 4 External electrode 6 Dielectric

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 セラミック誘電体層と、該セラミック誘
電体層の同一平面上に配置された複数個の内部電極層と
が交互に積層され、略直方体の形状を有し、該直方体の
対向する二側面にそれぞれ、前記内部電極層と接続され
た外部電極を有する積層セラミックコンデンサにおい
て、一方の外部電極に接続された各内部電極パターンと
他方の外部電極に接続された対応する各内部電極パター
ンとの重複有効部面積とが相互に異なることを特徴とす
る積層セラミックコンデンサアレイ。
1. A ceramic dielectric layer and a plurality of internal electrode layers arranged on the same plane of the ceramic dielectric layer are alternately stacked, have a substantially rectangular parallelepiped shape, and are opposed to each other. In a multilayer ceramic capacitor having external electrodes connected to the internal electrode layers on two side surfaces, each internal electrode pattern connected to one external electrode and a corresponding internal electrode pattern connected to the other external electrode. And an overlapping effective part area different from each other.
【請求項2】 一方の外部電極に接続された各内部電極
パターンと他方の外部電極に接続された対応する各内部
電極パターンとの、幅及び/又は長さを変化させること
により重複有効部面積を変化させた請求項1の積層セラ
ミックコンデンサアレイ。
2. The overlapping effective area is changed by changing the width and / or length of each internal electrode pattern connected to one external electrode and each corresponding internal electrode pattern connected to the other external electrode. 2. The multilayer ceramic capacitor array according to claim 1, wherein
JP27410296A 1996-09-25 1996-09-25 Monolithic ceramic capacitor array Pending JPH10106887A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP27410296A JPH10106887A (en) 1996-09-25 1996-09-25 Monolithic ceramic capacitor array

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP27410296A JPH10106887A (en) 1996-09-25 1996-09-25 Monolithic ceramic capacitor array

Publications (1)

Publication Number Publication Date
JPH10106887A true JPH10106887A (en) 1998-04-24

Family

ID=17537037

Family Applications (1)

Application Number Title Priority Date Filing Date
JP27410296A Pending JPH10106887A (en) 1996-09-25 1996-09-25 Monolithic ceramic capacitor array

Country Status (1)

Country Link
JP (1) JPH10106887A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007180323A (en) * 2005-12-28 2007-07-12 Matsushita Electric Ind Co Ltd Manufacturing method of laminated ceramic capacitor and its selector
JP2011035312A (en) * 2009-08-05 2011-02-17 Tdk Corp Mounting structure of multilayer capacitor array

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007180323A (en) * 2005-12-28 2007-07-12 Matsushita Electric Ind Co Ltd Manufacturing method of laminated ceramic capacitor and its selector
JP2011035312A (en) * 2009-08-05 2011-02-17 Tdk Corp Mounting structure of multilayer capacitor array

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