JP3538758B2 - Capacitor array and method of manufacturing the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a capacitor array in which a plurality of capacitor units are integrally formed using one ceramic sintered body, and more particularly, to an improved structure between adjacent capacitor units. It relates to a capacitor array.

[0002]

2. Description of the Related Art With the miniaturization of electronic equipment, miniaturization and high-density mounting of electronic components have been promoted. For example, as a capacitor, an ultra-small multilayer ceramic capacitor has been developed, and a circuit in which a number of these ultra-small multilayer ceramic capacitors are mounted on a printed circuit board has been realized.

In order to achieve high-density mounting of electronic components, a capacitor array in which a plurality of capacitors are integrated has been used. In a conventional capacitor array, 1
A plurality of capacitor units formed by forming internal electrodes so as to overlap with each other via a ceramic layer in ceramic sintered bodies are arranged in parallel in the sintered bodies. The electrical connection of the internal electrodes of each capacitor unit is made using a through-hole electrode provided in the sintered body.

The use of the above-mentioned capacitor array makes it possible to reduce the number of capacitors to be prepared and to simplify the mounting operation.

[0005]

To enable high-density mounting of electronic components, it is necessary to use smaller multilayer capacitors as described above. However, as the size of the multilayer capacitor becomes smaller, the area of the internal electrodes becomes smaller and becomes very light. As a result, when mounted on a printed circuit board, the multilayer capacitor rises with one external electrode side as the lower end due to the surface tension of the molten solder,
There is a problem that a phenomenon (tombstone phenomenon) that the other external electrode side floats above the printed circuit board occurs. In other words, the smaller the multilayer capacitor is, the more difficult it is to mount it on a printed circuit board.

On the other hand, when the above capacitor array is used, since a plurality of capacitor units are formed in one sintered body, the tombstone phenomenon due to the surface tension of the molten solder hardly occurs. However,
Since a plurality of capacitor units are arranged side by side in one sintered body, it is unavoidable to generate a stray capacitance between adjacent capacitor units.
Therefore, the circuit using the capacitor array may be adversely affected by the stray capacitance.

An object of the present invention is to provide a structure suitable for high-density mounting, capable of stably mounting on a printed circuit board, and capable of reducing an adverse effect due to stray capacitance between adjacent capacitor units. It is to provide a capacitor array.

[0008]

Means for Solving the Problems The invention described in claim 1, a plurality constructed by forming a plurality of internal electrodes so as to overlap in the thickness direction through the ceramic layer to the single ceramic sintered body Are arranged in a matrix of m rows × n columns (where m and n are integers of 2 or more) in the sintered body. Grooves or end faces of the sintered body extending in the thickness direction from at least one of the upper surface or the lower surface, on both sides of each capacitor unit, are alternately exposed in the thickness direction, and are electrically connected to internal electrodes. An external electrode formed on the inner surface of the groove and the end surface of the sintered body, and a capacitor having a dielectric constant lower than that of the sintered body is provided between capacitor units other than the side on which the external electrode is formed. A capacitor array characterized by being separated by a body layer.

The dielectric layer having a lower relative dielectric constant than the sintered body according to the first aspect of the present invention is provided between the capacitor units other than the side on which the external electrodes are formed, for example, as described in the second aspect. A groove may be formed so as to extend in a thickness direction from at least one of an upper surface and a lower surface of the sintered body, and the dielectric layer may be constituted by an air layer in the groove. The groove may be filled with a solid dielectric material having a lower dielectric constant than the sintered body. The method for manufacturing a capacitor array according to the present invention is a method for manufacturing the capacitor array according to the present invention, comprising the steps of obtaining a sintered body including a plurality of capacitor units, and sintering both sides of each of the capacitor units. Forming a groove extending in the thickness direction from at least one of the upper surface or the lower surface of the body so that the internal electrodes of each capacitor unit are alternately exposed to the groove or the end face of the sintered body; and forming a conductive paste in the groove. forming a conductive layer by baking filling, deeper than the conductive layer, and said forming a thin groove than the groove, than the groove
To form the respective external electrodes on both sides of the narrow groove, said groove
Forming a dielectric layer having a lower dielectric constant than the sintered body by the narrower grooves . In a specific aspect of the manufacturing method according to the present invention, the method further includes a step of filling a solid dielectric material having a lower dielectric constant than the sintered body into a groove smaller than the groove .

[0010]

In the capacitor array according to the first aspect of the present invention, in the direction in which the internal electrodes are drawn out between the capacitor units, the grooves extend from at least one of the upper surface and the lower surface of the sintered body in the thickness direction. The internal electrodes of the capacitor unit are alternately exposed in the thickness direction on both sides of the capacitor unit on the groove or the end surface of the sintered body, and the external electrodes are formed on the inner surface of the groove and the end surface of the sintered body. . Therefore, the adjacent capacitor units are separated from each other via the groove, and the relative permittivity of the portion of the groove is equal to the relative permittivity of air, so that the relative permittivity is extremely lower than the relative permittivity of the sintered body. . Further, between the capacitor units on the side different from the side on which the external electrodes are formed, adjacent capacitor units are separated by a dielectric layer having a lower dielectric constant than the sintered body.

Therefore, the stray capacitance between adjacent capacitor units is extremely reduced by the groove and the dielectric layer. According to the second aspect of the present invention, since the low dielectric constant dielectric layer is made of air in the groove, the external electrode is formed in the same manner as the external electrode is formed. The other side and the other capacitor units are also separated by air.

Further, according to the third aspect of the invention, the capacitor units other than the side on which the external electrodes are formed are separated by the solid dielectric layer, and the relative dielectric constant of the dielectric layer is reduced by sintering. Lower than the dielectric constant of the body.

Therefore, also in the inventions according to the second and third aspects, the stray capacitance between adjacent capacitor units is extremely reduced, as in the invention according to the first aspect. Therefore, according to the first to third aspects of the present invention, it is possible to reliably prevent an adverse effect on the stray capacitance between adjacent capacitor units.

Also, as compared with the conventional case where a plurality of ultra-small multilayer capacitors are mounted, the mounting cost can be reduced and the tombstone phenomenon at the time of mounting can be prevented. Furthermore, when compared with the conventional multilayer capacitor array, the adverse effect due to the stray capacitance between adjacent capacitor units can be reduced, so that a circuit that can exhibit desired characteristics can be reliably configured.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below with reference to a capacitor array with reference to the drawings. In the following description, the structure of the capacitor array will be clarified by first describing the method of manufacturing the capacitor array of each embodiment.

First Embodiment First, as shown in FIGS. 1A and 1B, rectangular ceramic green sheets 1 and 2 are prepared. The ceramic green sheets 1 and 2 are formed by mixing a slurry obtained by kneading a dielectric ceramic powder such as a barium titanate-based ceramic powder with a known and commonly used binder and an organic solvent into an appropriate sheet forming method such as a doctor blade method. It is obtained by molding and punching.

On the upper surface of the ceramic green sheet 1,
Rectangular internal electrodes 3 to 8 are formed by printing a conductive paste so that the length direction extends from one edge 1a to the other edge 1b. Similarly, also on the upper surface of the ceramic green sheet 2, rectangular internal electrodes 9 to 14 are formed by printing a conductive paste so that the length between the edges 2a and 2b is the length direction.

On the upper surface of the ceramic green sheet 1, the internal electrodes 3 to 8 have the same dimensions in the width direction, and similarly, the internal electrodes 5, 5 are formed such that the internal electrodes 3, 4 form the same row. 6 and the internal electrodes 7 and 8 are arranged so as to constitute the same row. Similarly, on the upper surface of the ceramic green sheet 2, the external electrodes 9,
10 are arranged in the same row, internal electrodes 11 and 12 are arranged in the same row, and internal electrodes 13 and 14 are arranged in the same row.

As the conductive paste, a conductive paste containing a conductive powder such as Ag or Ag-Pd is used. However, other than the printing of the conductive paste, the internal electrodes 3 may be formed by another conductive film forming method such as evaporation or plating.
~ 8, 9 ~ 14 may be formed.

Next, the ceramic green sheets 1
2 were prepared, and a plurality of them were prepared, and alternately, as shown in FIG.
As shown schematically in FIG. 2, an appropriate number of plain ceramic green sheets 15 and 16 are stacked above and below the stack as shown in FIG. 2 and pressed in the thickness direction. The laminate is obtained by pressure bonding as described above. By firing the obtained laminate, the sintered body 17 shown in FIGS. 3 and 4 is obtained.

As is apparent from FIG. 3, one end face 17a of the sintered body 17 has a structure as shown in FIG.
The internal electrodes 4, 8, and 12 are exposed. Other end face 17
Although the b side is not shown, the internal electrodes 5 and 5 of FIG.
9 and 13 are exposed.

FIGS. 4A and 4B are cross-sectional views taken along lines AA and BB in FIG. 3 (the hatching is omitted to make it easier to see the internal electrodes. The hatching is omitted for the similar drawings.)
However, it can be seen that the above-described internal electrodes on the ceramic green sheet 1 and the internal electrodes on the ceramic green sheet 2 are alternately stacked with the sintered body layer interposed therebetween.

Next, as shown in FIG. 5, grooves 18 and 19 are formed from the upper surface 17c side of the ceramic sintered body 17 to the lower surface 17d side, but not to the lower surface 17d. FIG. 6 is a cross-sectional view of a portion along the line AA in FIG. 6, the internal electrode 3 shown in FIG. 1 is divided by the formation of the groove 18, and the internal electrodes 3a and 3b are formed.
Is configured to be exposed in the groove 18. Similarly, the internal electrode 10 formed on the upper surface of the ceramic green sheet 2 is divided by the groove 19, and the internal electrodes 10a, 10
b are configured to be exposed on both sides of the groove 19 and on the inner surface of the groove 19. That is, the groove 18 is formed so as to divide the internal electrodes 3 and 7 shown in FIG. 1 in the width direction. Although not necessarily clear in FIG. 6, the internal electrode formed on the upper surface of the ceramic green sheet 2 is formed. Similarly, the electrode 11 is divided into two internal electrodes having the same length.

Similarly, the formation of the groove 19 allows the internal electrode 1
Two internal electrodes 10a, 10b having equal lengths 0
The internal electrodes 6 and 14 in FIG. 1 are also divided into two internal electrode portions.

The processing of the grooves 18 and 19 can be performed using a diamond cutter, a dicing machine, or the like. 6, the widths of the grooves 18 and 19 are selected such that the internal electrodes 4 and 9 are not exposed in the grooves 18 and 19, and the depths of the grooves 18 and 19 overlap. It is preferable that the selection is made so as to reach below the lowermost internal electrode of the internal electrode. This is because the grooves 18 and 19 are portions where the external electrodes are formed on the inner peripheral surface thereof in a process described later, and the inside of the grooves 18 and 19 constitutes a portion separating adjacent capacitors.

Next, as is apparent from FIG. 7 which is a cross-sectional view of the portion shown in FIG. 6, Ag or Ag-Pd pastes 20 and 21 are formed in the grooves 18 and 19 by using a micro dispenser, for example. Fill.

Thereafter, the conductive pastes 20 and 21 are baked at a temperature of, for example, 850 ° C. to form a conductive layer. Next, in the conductive layer configured as described above, the grooves 22, 23 which are deeper than the lowermost portion of the conductive layer.
Is formed as shown in FIG. The grooves 22 and 23 need to be formed narrower than the initially formed grooves 18 and 19 and must be formed deeper than the first grooves 18 and 19. Thereby, external electrodes 24 to 27 are formed on both sides of the grooves 22 and 23 as shown in FIG. External electrode 24
27 are formed by leaving a part of the conductive layers 20 and 21 described above, and are electrically connected to the internal electrodes 3a, 3b, 10a and 10b exposed in the grooves 18 and 19. Will be. That is, taking the external electrode 24 as an example, it is electrically connected to one of the internal electrodes formed by dividing the internal electrodes 3a, 3a, 3a shown in FIG. 6 and the internal electrodes 7, 11 in FIG. You. Similarly, for the other external electrodes 25 to 27, the internal electrodes in the sintered body 17 are electrically connected every other layer in the thickness direction.

FIG. 9 is a perspective view showing the sintered body on which the external electrodes 24 to 27 are formed as described above. Next, the grooves 22,
As shown in FIG. 10 in a cross-sectional view of the portion shown in FIG.
A glass paste containing a material having a lower relative dielectric constant than the sintered body 17 such as a Si-based glass;
9 is formed. When the dielectric layers 28 and 29 are formed by filling with the above-mentioned glass paste, they are formed by heat treatment at a temperature of, for example, about 800 ° C. after the filling. However, the material constituting the dielectric layers 28 and 29 is not limited to the above-mentioned glass paste, but may be the sintered body 17.
Any material can be used as long as it has a relative permittivity lower than the relative permittivity of the ceramic constituting the ceramic layer. The dielectric layer 28, 29 can be formed.

The dielectric layers 28 and 29 need to be formed so as not to cover the upper surfaces of the external electrodes 24 to 27 arranged on both sides thereof. Next, in the direction perpendicular to the grooves 18, 19, 22, and 23 described above,
The grooves 31 and 32 shown in FIG.

FIG. 1 is a sectional view taken along line AA in FIG.
As is clear from FIG.
Between the internal electrodes arranged on both sides of the groove 32, 32
The width is formed so as not to be exposed on the inner wall. That is,
Referring to the internal electrodes formed on the ceramic green sheets 1 and 2 of FIG.
The groove 31 is formed between a row where the internal electrodes 3 and 4 are formed and a row where the internal electrodes 5 and 6 are formed so that the internal electrodes 5 and 6 are separated from each other. The groove 31 is formed in such a width that the side edges of the internal electrodes 3, 4, 5, 6 are not exposed in the groove 31. The same applies to the groove 32.

Next, the internal electrodes exposed on the outer end faces of the capacitor units formed on both sides of each row are respectively provided on both end faces 17a and 17b of the sintered body 17, respectively.
It is configured by forming external electrodes 34 to 39 as shown. The external electrodes 34 to 39 can be formed according to a known external electrode forming method.

As described above, the multilayer capacitor array 33 of this embodiment shown in FIG. 11 is obtained. In the multilayer capacitor array 33 of the present embodiment, nine capacitor units are configured. In other words, three rows of capacitor unit portions are constituted by being separated by the grooves 31, 32,
The capacitor unit portion of each row corresponds to the dielectric layer 2 described above.
It has three capacitor units separated by 8,29. That is, in this embodiment, an attrix-like capacitor array with m = 3 and n = 3 is formed, and FIG.
1, each capacitor unit, reference number 33A ~
33I.

In the above-described embodiment, the ceramic green sheets 1 and 2 shown in FIG. 1 are stacked as they are, and the capacitor array 33 of 3 rows × 3 columns is obtained through the above steps. A capacitor array of m ≧ 4 and n ≧ 4 may be manufactured using a larger ceramic green sheet, and then cut in the thickness direction to obtain a capacitor array of 3 rows × 3 columns shown in FIG.

Next, specific experimental results will be described.
As the ceramic green sheets 1 and 2, using a slurry mainly composed of a barium titanate-based dielectric ceramic powder and forming a 10 μm-thick slurry, each internal electrode is formed by applying and baking an Ag-Pd paste. Then, the sintered body 17 shown in FIG.
A sintered body having a width of 8.1 mm and a thickness of 1.0 mm was obtained. Thereafter, the grooves 18 and 19 are formed (having a width of 300 μm).
An Ag paste was filled as a conductive paste for forming an external electrode, and baked at a temperature of 850 ° C.
External electrodes 24 to 27 facing grooves 22 and 23 were formed by forming 2 and 23. Also, as for the grooves 22 and 23, grooves (width = 100 μm) having a smaller width than the grooves 18 and 19 (width = 300 μm) are formed, and a Pb-Al-Si-based glass is filled as the dielectric layer. Finally, 2.5mm ×
A three-row, three-column capacitor array 33 having a planar shape of 2.5 mm was obtained.

The capacitor array 33 and a conventional capacitor array 40 in which the grooves 22, 23, 31, 32 are not formed are prepared for comparison.
As shown in FIG. 11B, the circuit board was mounted on the test circuit board 41 by using solder in the direction shown in FIG.
Next, while being mounted on the test circuit board 41,
Cooling to a temperature of −25 ° C., then heating to + 125 ° C., and cooling to −25 ° C. again as one cycle;
After the completion of the 1000 cooling / heating cycles, the insulation resistance of each capacitor array was measured. A sample in which the insulation resistance changed by 10% or more from the initial insulation resistance was regarded as a failure, and the above measurement was performed for each of the 50 capacitor arrays of the example and the comparative example. The results are shown in Table 1 below.
In addition, when the above-mentioned failure occurred in one capacitor unit in one capacitor array, one capacitor array was counted as a failure.

[0036]

[Table 1]

As is clear from Table 1, the failure rate of the capacitor array of the comparative example is 24%, whereas the failure does not occur at all in the capacitor array 33 of the embodiment.

The capacitor array of the second embodiment the second embodiment is an embodiment of the invention described in claim 3.

First, as in the first embodiment, FIG.
Is obtained. Thereafter, the grooves 31 and 32 of the capacitor array 33 are filled with a glass paste mainly composed of Pb-Al-Si glass powder by a micro-dispenser as shown in a sectional view of FIG. To form dielectric layers 51 and 52. For other structures,
Since it is completely the same as the first embodiment, the description of the first embodiment described above will be referred to in the second embodiment.

In the second embodiment, since a dielectric layer having a lower dielectric constant than that of the sintered body 17 is formed in the grooves 31 and 32, the dielectric layers between the capacitor units on both sides of the grooves 31 and 32 are formed. The stray capacitance is effectively reduced. And the second
In this embodiment, since the grooves 31 and 32 are also filled with the solid dielectric layer, it is possible to form a capacitor array having better mechanical strength than the first embodiment.

In each of the embodiments described above, the grooves for separating adjacent capacitor units are formed so as to extend from the upper surface to the lower surface of the sintered body. it may be grooves formed, or may be groove formed to extend from both the top and bottom surfaces along the thickness direction. However, to reduce stray capacitance between adjacent capacitor units,
The groove needs to be located on the side of the part where the overlapping internal electrodes are located. Therefore, it is preferable to form the groove from one of the upper surface and the lower surface. Note that the components of the present invention
The method of manufacturing the denser array is based on the process order and method of the above embodiment.
It is pointed out here that it is not limited to law
Good.

[Brief description of the drawings]

FIGS. 1A and 1B are plan views respectively showing the shapes of a ceramic green sheet prepared in a first embodiment and internal electrodes formed thereon.

FIG. 2 is a schematic perspective view for explaining a step of laminating a plurality of ceramic green sheets.

FIG. 3 is a perspective view showing a sintered body.

FIGS. 4A and 4B are respectively AA in FIG.
FIG. 2 is a schematic cross-sectional view along the line BB.

FIG. 5 is a perspective view showing a sintered body in which a groove is formed.

FIG. 6 is a sectional view taken along line AA of FIG. 5;

FIG. 7 is a cross-sectional view showing a state in which a conductive paste is filled in a groove.

FIG. 8 is a sectional view showing a state in which a relatively narrow groove is formed for forming an external electrode.

FIG. 9 is a perspective view showing a sintered body in which an external electrode is formed on an inner wall of a groove.

FIG. 10 is a cross-sectional view showing a state where a low dielectric constant dielectric layer made of glass paste is formed in a groove in which an external electrode is formed.

FIG. 11 is a perspective view showing a capacitor array according to the first embodiment.

FIG. 12 is a sectional view taken along the line AA in FIG. 11;

FIGS. 13A and 13B are side views showing a state where the capacitor arrays of the first embodiment and the comparative example are mounted on a test circuit board, respectively.

FIG. 14 is a sectional view illustrating a capacitor array according to a second embodiment.

[Explanation of symbols]

17 ... Sintered body 31, 32 ... groove 33 ... Capacitor array 33A to 33I: Capacitor unit 28, 29 ... dielectric layer 24 to 27: External electrodes

Claims (5)

(57) [Claims] 1. A plurality of capacitor units each formed by forming a plurality of internal electrodes so as to overlap in a thickness direction via a ceramic layer in one ceramic sintered body, and m rows × n are formed in the sintered body. In a multilayer capacitor array arranged in a matrix of rows (where m and n are integers of 2 or more), an internal electrode of each capacitor unit is provided on at least one of an upper surface or a lower surface of a sintered body on both sides of each capacitor unit. A groove extending in the thickness direction or an external electrode which is alternately exposed to the end face of the sintered body, and which is formed on the inner face of the groove and the end face of the sintered body so as to be electrically connected to the internal electrode, Wherein the capacitor units other than the side on which the external electrodes are formed are separated by a dielectric layer having a lower relative dielectric constant than the sintered body. Array. 2. A groove is formed between capacitor units other than the side on which the external electrodes are formed so as to extend in a thickness direction from at least one of an upper surface and a lower surface of the sintered body, and air in the groove is formed. The capacitor array according to claim 1, wherein a layer comprises the dielectric layer. 3. A groove is formed between capacitor units other than the side on which the external electrodes are formed so as to extend in a thickness direction from at least one of an upper surface and a lower surface of the sintered body. 2. The capacitor array according to claim 1, wherein the capacitor array is filled with a solid dielectric material having a relative dielectric constant lower than that of the sintered body, and the dielectric material forms the dielectric layer. 3. 4. The method for manufacturing a capacitor array according to claim 1, wherein a step of obtaining a sintered body including a plurality of capacitor units is performed, and an upper surface of the sintered body on both sides of each of the capacitor units. Or forming grooves extending in at least one of the lower surfaces in the thickness direction such that the internal electrodes of each capacitor unit are alternately exposed to the grooves or the end faces of the sintered body; and filling and firing the conductive paste in the grooves. Forming a conductive layer by forming a groove deeper than the conductive layer and narrower than the groove, forming each external electrode on both sides of the groove narrower than the groove, and narrower than the groove. Forming a dielectric layer having a lower dielectric constant than the sintered body by the groove. 5. The method of manufacturing a capacitor array according to claim 4, further comprising a step of filling a solid dielectric material having a lower dielectric constant than a sintered body into a groove smaller than the groove.