KR101871281B1 - Multilayer ceramic capacitor, mounting structure of multilayer ceramic capacitor, and taping electronic component array - Google Patents

Multilayer ceramic capacitor, mounting structure of multilayer ceramic capacitor, and taping electronic component array Download PDF

Info

Publication number
KR101871281B1
KR101871281B1 KR1020160008615A KR20160008615A KR101871281B1 KR 101871281 B1 KR101871281 B1 KR 101871281B1 KR 1020160008615 A KR1020160008615 A KR 1020160008615A KR 20160008615 A KR20160008615 A KR 20160008615A KR 101871281 B1 KR101871281 B1 KR 101871281B1
Authority
KR
South Korea
Prior art keywords
multilayer ceramic
dimension
ceramic capacitor
face
electrode
Prior art date
Application number
KR1020160008615A
Other languages
Korean (ko)
Other versions
KR20160094854A (en
Inventor
에이지 테라오카
Original Assignee
가부시키가이샤 무라타 세이사쿠쇼
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 가부시키가이샤 무라타 세이사쿠쇼 filed Critical 가부시키가이샤 무라타 세이사쿠쇼
Publication of KR20160094854A publication Critical patent/KR20160094854A/en
Application granted granted Critical
Publication of KR101871281B1 publication Critical patent/KR101871281B1/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/002—Details
    • H01G4/005—Electrodes
    • H01G4/012—Form of non-self-supporting electrodes
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B65—CONVEYING; PACKING; STORING; HANDLING THIN OR FILAMENTARY MATERIAL
    • B65H—HANDLING THIN OR FILAMENTARY MATERIAL, e.g. SHEETS, WEBS, CABLES
    • B65H20/00—Advancing webs
    • B65H20/20—Advancing webs by web-penetrating means, e.g. pins
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/002—Details
    • H01G4/018—Dielectrics
    • H01G4/06—Solid dielectrics
    • H01G4/08—Inorganic dielectrics
    • H01G4/12—Ceramic dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/002—Details
    • H01G4/228—Terminals
    • H01G4/232—Terminals electrically connecting two or more layers of a stacked or rolled capacitor
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K13/00—Apparatus or processes specially adapted for manufacturing or adjusting assemblages of electric components
    • H05K13/04—Mounting of components, e.g. of leadless components
    • H05K13/0417—Feeding with belts or tapes

Abstract

A stacked body including a plurality of stacked dielectric layers and a plurality of internal electrodes, and a pair of external electrodes. Wherein the width dimension of the laminate is larger than the thickness dimension, the length dimension is 0.4 mm or less, the width dimension is 0.15 mm or more and 0.35 mm or less, the thickness dimension is 0.2 mm or less, and the internal electrode is made of Cu or Ag as a main component The width dimension of the internal electrode is 60% or more of the width dimension of the laminate.

Description

TECHNICAL FIELD [0001] The present invention relates to a multilayer ceramic capacitor, a multilayer ceramic capacitor mounting structure, and a taping continuous electronic component. [0001] The present invention relates to a multilayer ceramic capacitor,

The present invention relates to a multilayer ceramic capacitor, a mounting structure of a multilayer ceramic capacitor, and a taping continuous electronic component.

2. Description of the Related Art In recent years, miniaturization of electronic equipment has also demanded a multilayer ceramic capacitor used in electronic equipment.

In addition, in electronic equipment such as a PA (power amplifier) module, higher frequency of operation frequency is being advanced, and even in a multilayer ceramic capacitor to be used, loss in the high frequency region is small, ESR (Equivalent Series Resistance) A high Q value is required. The high frequency range is from 100 MHz to 100 GHz.

A multilayer ceramic capacitor that realizes a high Q value in a high frequency region is disclosed in Japanese Patent Application Laid-Open No. 2000-306762.

In the multilayer ceramic capacitor disclosed in Japanese Patent Application Laid-Open No. 2000-306762, the internal resistance of the internal electrode is lowered and the Q value is increased by increasing the thickness of the internal electrode. Japanese Patent Application Laid-Open No. 2000-306762, for example, when Pd is used as the main component of the internal electrode, a large Q value can be obtained by making the thickness of the internal electrode 12 mu m or more. When Ag or Cu is used as the main component of the internal electrode, a large Q value can be obtained by making the thickness of the internal electrode 9 mu m or more.

The multilayer ceramic capacitor disclosed in Japanese Patent Application Laid-Open No. 2000-306762 has a large internal electrode thickness (since the main component of the internal electrode is 12 占 퐉 or more in the case of Pd and 9 占 퐉 or more in the case of Ag and Cu) It has not been possible to meet the demand for miniaturization required for multilayer ceramic capacitors.

In the multilayer ceramic capacitor disclosed in Japanese Patent Application Laid-Open No. 2000-306762, since the thickness of the internal electrode is large, a difference in shrinkage between the internal electrode and the dielectric ceramic layer at the time of firing There is a risk of peeling.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described conventional problems. A multilayer ceramic capacitor based on the first aspect of the present invention includes a first main surface and a second major surface which face each other in a stacking direction and a plurality of internal electrodes, And a first end face and a second end face opposing each other in a longitudinal direction orthogonal to each of the lamination direction and the width direction and a first side face and a second end face opposing each other in the lamination direction and the width direction, And a pair of external electrodes formed on the first and second cross sections. The internal electrode is connected to the external electrode at least on each of the first end face and the second end face. In the laminate, the dimension between the first end face and the second end face is defined as the length dimension, the dimension between the first side face and the second side face is defined as the width dimension, and the dimension between the first main face and the second main face is In the case of a thickness dimension, the width dimension is larger than the thickness dimension. The length dimension is 0.4 mm or less. The width dimension is not less than 0.15 mm and not more than 0.35 mm. The thickness dimension is 0.2 mm or less. The internal electrode is made mainly of Cu or Ag. The width dimension of the internal electrode is 60% or more of the width dimension of the laminate.

It is preferable that the thickness dimension of the internal electrode is 1.2 m or more and 2.4 m or less. When the thickness dimension of the internal electrode is smaller than 1.2 占 퐉, the Q value becomes low, which is not preferable. If the thickness of the internal electrode is larger than 2.4 占 퐉, there is a fear that peeling may occur at the interface between the internal electrode and the dielectric ceramic layer due to the difference in shrinkage between the internal electrode and the dielectric ceramic layer during firing.

It is preferable that the dimension of the width gap without the internal electrode between the internal electrode and the first side or the second side of the laminate is 25 mu m or more. If the dimension of the width gap is smaller than 25 占 퐉, moisture intrudes from the side surface of the multilayer body and reaches the internal electrode, making it difficult to ensure humidity resistance.

Wherein a plurality of internal electrodes continuously adjacent to each other in the stacking direction are connected to one external electrode and an internal electrode which is not connected to one of the plurality of internal electrodes continuously adjacent in the stacking direction is connected to the other It is preferable that the external electrode is connected to the external electrode. In this case, even if the thickness dimension of one internal electrode is small, comprehensive conductivity can be ensured by a plurality of internal electrodes, so that a decrease in the Q value can be suppressed.

In this case, two adjacent internal electrodes continuously in the stacking direction are connected to one external electrode, and are not connected to one of the two internal electrodes successively adjacent in the stacking direction It is more preferable that the internal electrode is connected to the other external electrode. When the number of internal electrodes connected to one or the other external electrodes continuously in the stacking direction is three or more, it is difficult to secure the number of internal electrodes required for forming the capacitors within the thickness dimension of the limited stacked body .

It is preferable that an auxiliary electrode is further formed inside the laminate. In this case, the connection between the external electrode and the internal electrode is improved, and the connection resistance between the external electrode and the internal electrode can be reduced.

A multilayer ceramic capacitor mounting structure based on the second aspect of the present invention is a multilayer ceramic capacitor in which external electrodes of multilayer ceramic capacitors based on the first aspect of the present invention described above are bonded to a land electrode formed on a substrate by solder Respectively. The normal direction of the internal electrodes of the multilayer ceramic capacitor and the normal direction of the substrate are perpendicular to each other. In this case, since the internal electrodes are perpendicular to the substrate, a current flows uniformly through each of the elements constituted by one dielectric ceramic layer and two internal electrodes sandwiching the dielectric ceramic layer, and Q The higher the value.

The multilayer ceramic capacitor mounting structure based on the third aspect of the present invention is a laminated ceramic capacitor in which external electrodes of multilayer ceramic capacitors based on the first aspect of the present invention described above are bonded to the land electrodes formed on the substrate by solder Respectively. The laminate is arranged so that the first side or the second side of the laminate is opposed to the substrate. In this case as well, since the internal electrodes are perpendicular to the substrate, a current flows uniformly through each element composed of one dielectric ceramic layer and two internal electrodes sandwiching the dielectric ceramic layer, The higher the value.

The taping continuous electronic component based on the fourth aspect of the present invention includes a long carrier tape on which a plurality of recesses are formed and a long cover tape covering the recess of the carrier tape. The multilayer ceramic capacitor according to the first aspect of the present invention described above is accommodated in the concave portion and the normal direction of the internal electrode of the multilayer ceramic capacitor and the normal direction of the bottom surface of the concave portion are perpendicular to each other. In this case, when the cover tape is peeled off from the carrier tape, the first side surface or the second side surface of the laminated body of the multilayer ceramic capacitor is located at the opening portion of the concave portion, and this side surface is, for example, The multilayer ceramic capacitor mounting structure based on the second or third aspect of the present invention described above can be easily realized.

The taping continuous electronic component based on the fifth aspect of the present invention includes a long-length carrier tape on which a plurality of recesses are formed and a long-top cover tape covering the recess of the carrier tape. The multilayer ceramic capacitor according to the first aspect of the present invention described above is accommodated in the concave portion and the first side or the second side of the laminated body of the multilayer ceramic capacitor faces the bottom surface of the concave portion. Also in this case, when the cover tape is peeled off from the carrier tape, the first side surface or the second side surface of the multilayer ceramic capacitor multilayer body is located at the opening portion of the recess, and this side surface is, for example, The multilayer ceramic capacitor mounting structure based on the second or third aspect of the present invention described above can be easily realized.

According to the multilayer ceramic capacitor based on the first aspect of the present invention, the Q value in the high frequency range can be increased. Further, according to the multilayer ceramic capacitor mounting structure based on the second and third aspects of the present invention, the Q value in the high frequency region can be increased. According to the taping continuous electronic component based on the fourth or fifth aspect of the present invention, the mounting structure of the multilayer ceramic capacitor based on the second and third aspects of the present invention can be easily realized.

These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.

1 is a perspective view showing a multilayer ceramic capacitor according to Embodiment 1 of the present invention.
2 is a cross-sectional view of the multilayer ceramic capacitor according to Embodiment 1 of the present invention, and is a view seen from the direction of the arrow in FIG. 1.
3 is a cross-sectional view of the multilayer ceramic capacitor according to Embodiment 1 of the present invention, and is a view seen from the direction of arrow YY in Figs. 1 and 2. Fig.
4 is a cross-sectional view of a multilayer ceramic capacitor according to Embodiment 1 of the present invention, and is a view seen from the ZZ line arrow direction in Figs. 1 to 3. Fig.
5 is a sectional view of the multilayer ceramic capacitor taken along the line II in FIG.
6 is a partial cross-sectional view showing an observation image by SEM.
7 is a WT cross-sectional view of a multilayer ceramic capacitor viewed from its end face.
8A is a cross-sectional view showing a mounting structure of a multilayer ceramic capacitor according to Embodiment 1 of the present invention.
8 (B) is a cross-sectional view showing the mounting structure of the multilayer ceramic capacitor according to the first embodiment of the present invention, and is a view seen from the direction of arrow RR in Fig. 8 (A).
FIG. 9A is a plan view showing the configuration of a taping continuous electronic component containing a multilayer ceramic capacitor according to Embodiment 1 of the present invention. FIG.
FIG. 9B is a cross-sectional view showing the configuration of a taping continuous electronic component containing a multilayer ceramic capacitor according to Embodiment 1 of the present invention, and is a view seen from the SS line arrow direction in FIG. 9A.
10 is a cross-sectional view showing the configuration of a multilayer ceramic capacitor according to Embodiment 2 of the present invention.
11 is a graph showing the Q value at a frequency of 1 GHz for each of the embodiment and the comparative example.

Hereinafter, the multilayer ceramic capacitor, the multilayer ceramic capacitor mounting structure, and the taping continuous electronic component according to each embodiment of the present invention will be described.

[Embodiment 1]

1 is a perspective view showing a multilayer ceramic capacitor according to Embodiment 1 of the present invention. 2 is a cross-sectional view of the multilayer ceramic capacitor according to Embodiment 1 of the present invention, and is a view seen from the direction of the arrow X-X in Fig. 3 is a cross-sectional view of a multilayer ceramic capacitor according to Embodiment 1 of the present invention, and is a view seen from the Y-Y line arrow direction in Figs. 4 is a cross-sectional view of the multilayer ceramic capacitor according to Embodiment 1 of the present invention, and is a view seen from the Z-Z line arrow direction in Figs. 1 to 3. Fig.

As shown in Figs. 1 to 4, the multilayer ceramic capacitor 100 includes the multilayer body 1. The laminate 1 has a first end face 1a and a second end face 1b, a first side face 1c and a second side face 1d, a first main face 1e and a second main face 1f And has a rectangular parallelepiped shape.

In the multilayer ceramic capacitor 100, the dimension between the first end face 1a and the second end face 1b is defined by the length dimension L and the dimension between the first side face 1c and the second side face 1d And the dimension between the first major surface 1e and the second major surface 1f is the thickness dimension T, the respective dimensions satisfy the following conditions.

In the multilayer ceramic capacitor 100, the length dimension L is 0.4 mm or less, the width dimension W is 0.35 mm or less, and the thickness dimension T is 0.2 mm or less. That is, the multilayer ceramic capacitor 100 is made compact by reducing the length L, the width W, and the thickness T of the multilayer body 1 as described above.

However, the width W of the layered product 1 is 0.15 mm or more. In the multilayer ceramic capacitor 100, the width dimension W e of the internal electrodes 4a to 4h to be described later relative to the width dimension W of the multilayer body 1 is relatively increased, . Therefore, the lower limit value is provided to the width dimension W of the layered product 1. On the other hand, in the layered product (1), the width dimension (W) is larger than the thickness dimension (T).

In the layered product 1, corner portions and ridge lines may have a rounded shape with a predetermined radius of curvature or less. In the present embodiment, the corner portions and the ridgeline of the layered product 1 are rounded by barrel polishing.

A pair of external electrodes 2a and 2b are formed at both ends of the layered body 1. [ The external electrode 2a is formed so as to cover the first side face 1c, the second side face 1d, the first main face 1e and the second main face 1f from the first end face 1a of the multilayer body 1 And is formed to have a cap shape. The external electrode 2b is formed so as to cover the first side face 1c, the second side face 1d, the first main face 1e and the second main face 1f from the second end face 1b of the multilayer body 1 And is formed to have a cap shape.

Each of the pair of external electrodes 2a and 2b is preferably composed of a ground layer and a plating layer formed on the ground layer, and is also configured in this embodiment. However, in the cross-sectional views of Figs. 2 and 3, external electrodes 2a and 2b are shown as a single layer for the sake of easy understanding.

On the other hand, the ground layer of the external electrodes 2a and 2b is not essential, and the plating layer may be formed directly on the laminate 1. [

For example, a metal mainly composed of Cu, Ni, Ag, Pd, an Ag-Pd alloy, Au, or the like can be used for each of the ground layers of the pair of external electrodes 2a and 2b. However, in the contact properties with the internal electrodes 4a to 4h to be described later, a metal containing Cu as a main component is excellent. On the other hand, the ground layer may be formed by co-firing co-fired with the internal electrodes 4a to 4h, or may be formed by a post-firing method in which a conductive paste is applied and baked .

On the other hand, when forming the ground layers of each of the pair of external electrodes 2a and 2b, it is preferable that the thickness of the ground layer is 12 μm or more and 20 μm or less. If the thickness of the ground layer is less than 12 占 퐉, the unfavorable effect due to the external electrode is undesirable. If the thickness of the ground layer is larger than 20 占 퐉, ESR becomes high, which is not preferable.

For example, a metal mainly composed of Cu, Ni, Ag, Pd, Ag-Pd alloy, Au or the like can be used for each of the plating layers of the pair of external electrodes 2a and 2b.

Each of the plating layers of the pair of external electrodes 2a and 2b may be formed in a plurality of layers. For example, each of the plating layers of the pair of external electrodes 2a and 2b can be composed of two layers of a Ni plating layer and a Sn plating layer formed on the Ni plating layer. On the other hand, the thickness of one layer of the plating layer is preferably about 1 to 10 mu m.

The laminate 1 includes a plurality of laminated dielectric ceramic layers 3a to 3i and a plurality of internal electrodes 4a to 4h. 2 to 4, the number of the dielectric ceramic layers 3a to 3i is nine, and the number of the internal electrodes 4a to 4h is eight. The number of the dielectric ceramic layers 3a to 3i The number of layers and the number of internal electrodes 4a to 4h are arbitrary and determined in accordance with the required capacitance of the multilayer ceramic capacitor 100. [ However, in order to reduce the thickness dimension T of the multilayer ceramic capacitor 100, the number of internal electrodes 4a to 4h is preferably 30 or less.

The dielectric ceramic layers (3a ~ 3i) can be, for example, formed of the dielectric ceramic as a main component, such as CaZrO 3. Alternatively, the dielectric ceramic layers (3a ~ 3i) may be a dielectric ceramic with addition of additives such as a Mn compound, Si compound, Sr compound of the main component, such as CaZrO 3. On the other hand, in the case of using a metal mainly composed of Cu in the electrode (4a ~ 4h), Cu is sintered, since the temperature is low, the low temperature sintering a dielectric ceramic glass (B 2 O 3, CaO, Li 2 O or SiO 2, etc. ) May be added to lower the sintering temperature of the dielectric ceramic.

The internal electrodes 4a to 4h are made of a metal material containing Cu or Ag as a main component. The internal electrodes 4a to 4h have a length dimension L E in the longitudinal direction of the laminated body 1, a width dimension W E in the width direction of the laminated body 1, Shaped film having a thickness dimension (T E ).

The length dimension L E of the internal electrodes 4a to 4h can be set within the range of the length dimension L of the multilayer body 1 in consideration of the required capacitance and the like of the multilayer ceramic capacitor 100. [ It is preferable that the thickness dimension T E of the internal electrodes 4a to 4h is 1.2 占 퐉 or more and 2.4 占 퐉 or less. If the thickness dimension T E of the internal electrodes 4a to 4h is smaller than 1.2 占 퐉, the Q value becomes low, which is not preferable. When the thickness T E of the internal electrodes 4a to 4h is larger than 2.4 占 퐉, the internal electrodes 4a to 4h and the internal electrodes 4a to 4h are formed by the difference in shrinkage between the internal electrodes 4a to 4h and the dielectric ceramic layer, There is a fear that peeling may occur at the interface with the dielectric ceramic layers 3a to 3i.

On the other hand, the thickness dimension T E of the internal electrodes 4a to 4h is generally larger at the end in the width direction than at the center in the width direction. The thickness dimension T E of the internal electrodes 4a to 4h is the thickness dimension of the central portion in the width direction.

Here, a method of measuring the thickness dimension (T E ) of the internal electrode will be described with reference to FIGS. 5 and 6. FIG. 5 is a sectional view of the multilayer ceramic capacitor taken along the line II in FIG. 6 is a partial cross-sectional view showing an observation image by a scanning electron microscope (hereinafter referred to as " SEM "). 5 and 6 show a general multilayer ceramic capacitor. The multilayer body 11 is different from the multilayer body 1 of the multilayer ceramic capacitor 100 according to the present embodiment in details such as the connection structure of the internal electrodes different.

In the present specification, the thickness dimension (T E ) of the internal electrode means an average thickness calculated by measuring the thickness of a plurality of internal electrodes.

In the measurement, first, the surface is polished from the side surface of the layered product 11 to a position half of the width of the layered product 11 to expose the LT cross section shown in Fig. If necessary, the exposed end surface of the LT is subjected to an etching treatment, and the internal electrodes stretched by polishing are removed.

Next, as shown in Fig. 5, of the exposed LT cross-sections, three portions of the upper portion (U), the central portion (M) and the lower portion (D) in the lamination direction are observed with SEM as the center in the longitudinal direction. The magnification to be observed is a magnification that can be observed by the dielectric ceramic layers of the five layers and the inner electrodes of the six layers, and the magnification is such that the dielectric ceramic layers and the internal electrodes can be clearly distinguished from each other.

When measuring the thickness of the internal electrodes of the multilayer ceramic capacitor, first, as shown in Fig. 6, five straight lines (La to Le) extending in the stacking direction of the multilayer body 11 in an enlarged cross section of the multilayer ceramic capacitor (Pitch (S)). The pitch S may be set to about 5 to 10 times the thickness of the internal electrode to be measured. For example, when the internal electrode having a thickness of about 1 占 퐉 is measured, the pitch S is set to 5 占 퐉. Next, the thickness of the internal electrode is measured on each straight line of the straight lines La to Le. However, when the internal electrodes are broken on the straight lines La to Le and the dielectric ceramic layers sandwiching the internal electrodes are connected to each other, or when the enlarged image of the measurement position is unclear, A new straight line is drawn, and the thickness of the internal electrode on the straight line is measured.

Specifically, as shown in Fig. 6, the thickness d1 on the straight line La, the thickness d2 on the straight line Lb, the thickness d3 on the straight line Lc, the thickness dimension on the straight line Ld, the thickness d4 on the straight line Le and the thickness d5 on the straight line Le are measured and the average value thereof is taken as the thickness dimension of the internal electrode. On the other hand, when measuring the thickness of the internal electrode at the position of the upper portion (U) or the lower portion (D) of the LT section, the outermost internal electrode in the stacking direction is excluded from the measurement target.

When calculating the thickness dimension (T E ) of the plurality of internal electrodes, the thicknesses of the upper, lower, middle, and lower inner electrodes are measured for each of the upper, lower, , And the average value is defined as the thickness dimension (T E ) of the plurality of internal electrodes. On the other hand, when the number of stacked internal electrodes is less than five, the thickness is measured for all the internal electrodes by the above-described method, and the average value is defined as the thickness dimension (T E ) of the plurality of internal electrodes.

Or higher, the internal electrode thickness (T E) describes the measurement method, but, the thickness in a line (La) in the six dimensions (D1), the thickness on the thickness (D2), a straight line (Lc) in a line (Lb) of The thickness of the dielectric ceramic layer can be measured by measuring the dimension D3, the thickness dimension D4 on the straight line Ld and the thickness dimension D5 on the straight line Le.

The description of the multilayer ceramic capacitor 100 according to the first embodiment will be described again.

The width dimension W E of the internal electrodes 4a to 4h is set to 60% or more of the width dimension W of the laminate 1. [ Thus, even when the thickness dimension T E of the internal electrodes 4a to 4h is small, the electric resistance value of the internal electrodes 4a to 4h can be kept small and the Q value in the high frequency region can be increased.

From this viewpoint, it is preferable that the width dimension W E of the internal electrodes 4a to 4h is as large as possible. However, the dimensions of the width gaps where the internal electrodes 4a to 4h and the internal electrodes 4a to 4h between the first side face 1c and the second side face 1d of the multilayer body 1 are not formed Wg) is preferably 25 占 퐉 or more. When the width Wg of the width gap is smaller than 25 占 퐉, moisture enters from the first side face 1c or the second side face 1d and reaches the internal electrodes 4a to 4h, making it difficult to ensure moisture resistance .

Here, a method of measuring the width dimension W E of the internal electrode and the dimension W g of the width gap will be described with reference to FIG. 7 is a WT cross-sectional view of the multilayer ceramic capacitor viewed from its end face.

In the present specification, the width dimension (W E ) of the internal electrode means an average width calculated by measuring the widths of the plurality of internal electrodes. The dimension Wg of the width gap means an average dimension of the width gap calculated by measuring a plurality of width gaps.

In the measurement, first, the end face of the layered product 11 is polished to a position 1/2 of the length of the layered product 11, and the WT end face shown in Fig. 7 is exposed. If necessary, the exposed WT cross section is subjected to an etching treatment, and the internal electrodes stretched by polishing are removed.

Next, as shown in Fig. 7, three portions of the upper (U), the central portion (M) and the lower portion (D) in the lamination direction among the exposed WT cross sections were imaged in an optical microscope, . Further, a line segment parallel to the W direction from the end portion of the internal electrode is drawn toward the side surface of the multilayer body 11, and the dimension of the width gap is measured from the length of each line segment. The average value is calculated for each of the upper portion U, the central portion M and the lower portion D with respect to the dimension of the width and the width gap of the internal electrode. Furthermore, by making the dimensions of the upper (U), middle (M) and lower (D) calculated, the internal width W E and the width Wg of the internal electrode are obtained.

On the other hand, the width dimension W E of the internal electrode can be obtained by reducing the dimension Wg of the width gap on both sides of the internal electrode from the width dimension W of the laminated body 11. That is, the relationship W E = W-2Wg is established.

The description of the multilayer ceramic capacitor 100 according to the first embodiment will be described again.

In the multilayer ceramic capacitor 100 according to the present embodiment, two internal electrodes 4a and 4b successively adjacent in the stacking direction are connected to one external electrode 2a, and two adjacent internal electrodes 4a and 4b The two internal electrodes 4e and 4f continuously connected in the stacking direction are connected to one external electrode 2a while the internal electrodes 4c and 4d of the long electrode are connected to the other external electrode 2b, , And the two internal electrodes 4g and 4h, which are continuously adjacent in the stacking direction, are connected to the other external electrode 2b.

In the multilayer ceramic capacitor 100, a set of internal electrodes 4a and 4b, a set of internal electrodes 4c and 4d, a set of internal electrodes 4e and 4f, and a set of internal electrodes 4g and 4f, 4h are connected to the external electrode 2a or the external electrode 2b, it is possible to ensure a large overall conductivity even if the thickness dimension T E per one of the internal electrodes 4a to 4h is small, The Q value can be suppressed from being lowered.

On the other hand, the number of the plurality of internal electrodes 4a to 4h to be one set is arbitrary, but it is preferable that the number of the internal electrodes 4a to 4h is two as in this embodiment. When the number of internal electrodes 4a to 4h as a set becomes three or more, the number of the internal electrodes 4a to 4h necessary for formation of capacitance within the thickness dimension T of the limited stacked body 1 It becomes difficult to secure the number of copies.

In the multilayer ceramic capacitor 100 according to the present embodiment, the auxiliary electrode 5a is provided between the dielectric ceramic layer 3a and the dielectric ceramic layer 3b so as to face the internal electrode 4a with a gap therebetween, Respectively. The dimension of the length gap which is the distance between the internal electrode 4a and the auxiliary electrode 5a in the longitudinal direction of the layered product 1 is Lg. The auxiliary electrode 5a is connected to the external electrode 2b.

The auxiliary electrode 5d is formed so as to face the internal electrode 4d such that the auxiliary electrode 5c faces the internal electrode 4c so as to face the internal electrode 4b so as to face the internal electrode 4b, The auxiliary electrode 5g is opposed to the internal electrode 4h such that the auxiliary electrode 5e faces the internal electrode 4g such that the auxiliary electrode 5e faces the internal electrode 4f so as to face the internal electrode 4h And an auxiliary electrode 5h are formed.

By forming the auxiliary electrodes 5a to 5h, the connection property between the external electrode and the internal electrode can be improved and the connection resistance can be lowered.

The length Lg of the length gap between the internal electrodes 4a to 4h and the auxiliary electrodes 5a to 5h is preferably 60 占 퐉 or more. If the dimension Lg of the length gap is less than 60 占 퐉, the internal electrodes 4a to 4h and the auxiliary electrodes 5a to 5h may be short-circuited at the portion of the length gap. When the length Lg of the length gap is 60 m or more, the difference between the thickness of the internal electrodes 4a to 4h and the thickness of the dielectric ceramic layers 3a to 3i can be absorbed, .

The multilayer ceramic capacitor 100 according to the present embodiment having the above structure can be manufactured, for example, by the following method.

First, a plurality of ceramic green sheets, conductive pastes for internal electrodes, and conductive pastes for external electrodes are prepared. The ceramic green sheet and various conductive pastes include a binder and a solvent, but known organic binders and organic solvents can be used.

Next, the internal electrode conductive paste is printed on a part of the ceramic green sheet in a predetermined pattern, for example, by screen printing to form the internal electrode pattern. On the other hand, the internal electrode pattern is not formed on the remaining part of the ceramic green sheets.

Next, a predetermined number of ceramic green sheets for outer layers, on which no internal electrode pattern is formed, are laminated, a ceramic green sheet on which an internal electrode pattern is formed is laminated in order, and an outer layer ceramic A predetermined number of green sheets are laminated to produce a mother laminate.

Next, the mother laminates are pressed in the laminating direction by means of an hydrostatic press or the like.

Next, the mother laminator is cut into a predetermined size to obtain a laminate 1 'having an unfavorable appearance. Then, the unfabricated laminate 1 'may be subjected to barrel polishing or the like so that each corner and corner of the unfabricated laminate 1' have a round shape.

Next, the unbaked laminate 1 'is fired. The firing temperature differs depending on the material of the dielectric ceramic and the internal electrode, but it is preferably about 900 DEG C or more and 1300 DEG C or less. As a result, a laminate 1 having a rectangular parallelepiped shape in which a plurality of dielectric ceramic layers 3a to 3i and a plurality of internal electrodes 4a to 4h are laminated is manufactured.

Next, an outer electrode conductive paste is applied to both end surfaces of the laminate 1 and baked to form respective ground layers of the pair of outer electrodes 2a and 2b. The baking temperature is preferably 700 deg. C or more and 900 deg. C or less.

Next, the surface of each base layer of each of the pair of external electrodes 2a and 2b is plated, if necessary. For example, a Ni plating layer is formed as the first layer and a Sn plating layer is formed as the second layer by electrolytic plating. Thus, the multilayer ceramic capacitor 100 according to the present embodiment is completed.

Next, a preferable example of the mounting structure of the multilayer ceramic capacitor 100 will be described. 8A is a cross-sectional view showing a mounting structure of a multilayer ceramic capacitor according to Embodiment (1) of the present invention. Fig. 8B is a cross-sectional view showing a mounting structure of the multilayer ceramic capacitor according to the embodiment (1) of the present invention, and is a view seen from the R-R line arrow direction in Fig. 8A.

As shown in Figs. 8 (A) and 8 (B), the mounting structure includes a substrate 50. Fig. On the surface of the substrate 50, land electrodes 51a and 51b are formed. The external electrode 2a of the multilayer ceramic capacitor 100 is bonded to the land electrode 51a by the solder 52. [ The external electrode 2b of the multilayer ceramic capacitor 100 is bonded to the land electrode 51b by the solder 52. [

In the mounting structure, the normal direction of the internal electrodes 4a to 4h of the multilayer ceramic capacitor 100 and the normal direction of the substrate 50 are perpendicular to each other.

The first side face 1c or the second side face 1d of the multilayer body 1 of the multilayer ceramic capacitor 100 shown in Fig. 1 is disposed so as to face the substrate 50 in the mounting structure.

In the mounting structure, since the internal electrodes 4a to 4h are perpendicular to the substrate 50, the current distribution of each element composed of one dielectric ceramic layer and two internal electrodes sandwiching the dielectric ceramic layer And the Q value in the high frequency range can be increased. For example, the element constituted by the dielectric ceramic layer 3c and the internal electrodes 4b and 4c and the element constituted by the dielectric ceramic layer 3g and the internal electrodes 4f and 4g are stacked in the laminate 1 But the current distribution of both is uniform, and the Q value in the high frequency region is increased.

On the other hand, in the mounting structure, it is preferable that the highest portion Fh of the fille formed by the solder 52 overlaps with the internal electrodes 4a to 4h in the width direction of the laminated body 1. [ The Q value can be further increased by overlapping the highest portion Fh of the fillet with the internal electrodes 4a to 4h.

Next, a preferred example of the taping continuous electronic component in which the multilayer ceramic capacitor 100 is housed will be described. FIG. 9A is a plan view showing the configuration of a taping continuous electronic component containing a multilayer ceramic capacitor according to Embodiment (1) of the present invention. FIG. Fig. 9B is a cross-sectional view showing the configuration of a taping continuous electronic component containing a multilayer ceramic capacitor according to a first embodiment of the present invention, and is a view seen from the S-S line arrow direction in Fig. 9A.

As shown in Figs. 9 (A) and 9 (B), the taping continuous electronic component includes a carrier tape 60 and a cover tape 61. Fig. The carrier tape 60 is made of resin or paper, and is a long film. In the carrier tape 60, a plurality of recesses 60a are formed at intervals in the longitudinal direction. The cover tape 61 is made of resin or paper, and is of a long length.

The concave portion 60a of the carrier tape 60 is sealed by the cover tape 61 while the multilayer ceramic capacitor 100 is housed in each concave portion 60a of the carrier tape 60. [ In the taping continuous electronic component, the normal direction of the internal electrodes 4a to 4h of the multilayer ceramic capacitor 100 and the normal direction of the bottom surface of the concave portion 60a of the carrier tape 60 are perpendicular to each other.

The first side surface 1c or the second side surface 1d of the multilayer body 1 of the multilayer ceramic capacitor 100 shown in Fig. 1 corresponds to the concave portion 60a of the carrier tape 60, As shown in Fig.

The first side face 1c of the multilayer ceramic body 100 of the multilayer ceramic capacitor 100 is formed in the opening portion of the concave portion 60a by peeling off the cover tape 61 from the carrier tape 60. [ Or the second side surface 1d. When the first side face 1c or the second side face 1d is sucked by a mounting machine by vacuum adsorption and mounted on a substrate, the multilayer ceramic capacitor 100 (100) shown in Figs. 8 (A) and 8 Can be easily realized.

[Embodiment 2]

Hereinafter, the multilayer ceramic capacitor 200 according to the second embodiment of the present invention will be described. 10 is a cross-sectional view showing a configuration of a multilayer ceramic capacitor according to Embodiment (2) of the present invention.

In the multilayer ceramic capacitor 100 according to the first embodiment shown in Figs. 1 to 4, two adjacent inner electrodes 4a and 4b are connected to one outer electrode 2a, and two adjacent inner electrodes 4c And 4d are connected to the other external electrode 2b and the adjacent two internal electrodes 4e and 4f are connected to one external electrode 2a and the two adjacent internal electrodes 4g and 4h Is connected to the other external electrode 2b. In the multilayer ceramic capacitor 200 according to the second embodiment of the present invention, the inner electrodes 14a (4a to 4h) are connected to the outer electrode 2a or the outer electrode 2b, To 14h are alternately connected to the external electrode 2a and the external electrode 2b one by one. The formation positions of the auxiliary electrodes 15a to 15h are also the same as those of the multilayer ceramic capacitor according to the first embodiment 100) have been changed.

The other configuration of the multilayer ceramic capacitor 200 according to the second embodiment of the present invention is the same as that of the multilayer ceramic capacitor 100 according to the first embodiment, and therefore description thereof will not be repeated.

10, the number of the dielectric ceramic layers 3a to 3i is nine and the number of the internal electrodes 14a to 14h is eight. The number of the dielectric ceramic layers 3a to 3i and the number of the internal electrodes 14a To 14h is arbitrary and determined in accordance with the required capacitance of the multilayer ceramic capacitor 200. [

Thus, in the multilayer ceramic capacitor 200 according to the second embodiment of the present invention, the internal electrodes 14a to 14h can be alternately connected to the external electrode 2a and the external electrode 2b one by one.

As described above, the structure of the multilayer ceramic capacitor 100 according to the first embodiment, an example of the manufacturing method, an example of the mounting structure, an example of the taping continuous electronic component accommodating the multilayer ceramic capacitor 100, the multilayer ceramic capacitor 100 according to the second embodiment The structure of the display device 200 has been described. However, the present invention is not limited to the above-mentioned contents, and various modifications can be made according to the purpose of the invention. It is also possible to extract components from the embodiments and combine them.

For example, in the multilayer ceramic capacitors 100 and 200, the auxiliary electrodes 5a to 5h and 15a to 15h are not essential, and they may not necessarily be provided.

The number of ceramic layers constituting the layered product 1 and the number of internal electrodes are arbitrary and can be determined in accordance with the required electrostatic capacity of the multilayer ceramic capacitors 100 and 200.

Furthermore, the structure and number of layers of the external electrode 2a and the external electrode 2b are arbitrary, and are not limited to the above description.

[ Experimental Example ]

In order to confirm the effectiveness of the present invention, the following experimental simulations were carried out.

First, as an example, five types of multilayer ceramic capacitors having capacitances of 0.7 kV, 1.0 kV, 1.5 kV, 2.0 kV, or 3.0 kV were constructed with the structure of the multilayer ceramic capacitor 100 according to the first embodiment .

In the embodiment, the length L, the width W and the thickness T of the laminate 1 are 0.4 mm, 0.3 mm and 0.2 mm, respectively.

In the embodiment, the width WE of the internal electrodes 14a to 14h is set to about 0.2 mm, which is 68% of the width W of the stack 1. The thickness dimension T E of the internal electrodes 14a to 14h was set to 1.5 mu m. However, the number of the internal electrodes 14a to 14h was set in accordance with the required capacitance value.

On the other hand, in the comparative example, the length L, the width W, and the thickness T of the laminate were 0.4 mm, 0.2 mm and 0.2 mm, respectively.

In addition, in the comparative example, the width dimension W E of the internal electrode was set to about 0.09 mm which is 45% of the width dimension W of the laminate. The thickness dimension (T E ) of the internal electrode was set to 1.5 탆. However, the number of internal electrodes was set in accordance with the required capacitance value.

11 is a graph showing the Q value at a frequency of 1 GHz for each of the embodiment and the comparative example. The example clearly shows a high Q value for the comparative example, and the effectiveness of the present invention can be confirmed.

Having described embodiments of the present invention, it should be understood that the disclosed embodiments are illustrative and non-restrictive in all respects. It is intended that the scope of the invention be represented by the claims, and all changes that come within the meaning and range of equivalency of the claims are intended to be embraced therein.

Claims (10)

1. A multilayer ceramic capacitor mounting structure in which external electrodes of a multilayer ceramic capacitor are bonded to land electrodes formed on a substrate by solder,
In the multilayer ceramic capacitor,
A first side face and a second side face opposing each other in a width direction orthogonal to the stacking direction and a first main face and a second main face opposing each other in the stacking direction and including a plurality of stacked dielectric layers and a plurality of internal electrodes, A laminate body having a first end face and a second end face opposite to each other in the longitudinal direction orthogonal to each of the lamination direction and the width direction; and a pair of first and second end faces formed on the first end face and the second end face of the laminate And an external electrode,
The internal electrode is connected to the external electrode at least in each of the first end face and the second end face,
Wherein the dimension between the first end face and the second end face is a length dimension, the dimension between the first side face and the second side face is a width dimension, and the first main face and the second main face In the case where the dimension between the main surface and the main surface is the thickness dimension,
Wherein the width dimension is larger than the thickness dimension,
The length dimension is 0.4 mm or less,
The width dimension is not less than 0.15 mm and not more than 0.35 mm,
The thickness dimension is 0.2 mm or less,
Wherein the internal electrode comprises Cu or Ag as a main component,
The width dimension of the internal electrode is 60% or more of the width dimension of the laminate,
Wherein a normal direction of the internal electrode of the multilayer ceramic capacitor and a normal direction of the substrate are perpendicular to each other,
The highest part of the fillet formed by the solder overlaps with the internal electrode in the width direction,
Wherein a dimension of a width gap in which the internal electrode is not formed between the internal electrode and the first side surface or the second side surface of the multilayer body is 25 mu m or more. The method according to claim 1,
Wherein a thickness dimension of the internal electrode is not less than 1.2 占 퐉 and not more than 2.4 占 퐉. delete The method according to claim 1,
A plurality of internal electrodes successively adjacent to each other in the stacking direction are connected to one of the external electrodes and connected to one of the plurality of internal electrodes successively adjacent in the stacking direction, And the external electrode is connected to the other external electrode. 5. The method of claim 4,
Wherein two internal electrodes continuously adjacent to each other in the stacking direction are connected to one of the external electrodes and connected to one of the two internal electrodes continuously adjacent in the stacking direction, And the external electrode is connected to the other external electrode. The method according to claim 1,
And an auxiliary electrode is further formed inside the laminated body. delete delete delete delete
KR1020160008615A 2015-01-31 2016-01-25 Multilayer ceramic capacitor, mounting structure of multilayer ceramic capacitor, and taping electronic component array KR101871281B1 (en)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP2015018010 2015-01-31
JPJP-P-2015-018010 2015-01-31
JPJP-P-2015-223539 2015-11-14
JP2015223539A JP2016146469A (en) 2015-01-31 2015-11-14 Multilayer ceramic capacitor, mounting structure of multilayer ceramic capacitor, and taping electronic component series

Publications (2)

Publication Number Publication Date
KR20160094854A KR20160094854A (en) 2016-08-10
KR101871281B1 true KR101871281B1 (en) 2018-06-27

Family

ID=56686451

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020160008615A KR101871281B1 (en) 2015-01-31 2016-01-25 Multilayer ceramic capacitor, mounting structure of multilayer ceramic capacitor, and taping electronic component array

Country Status (2)

Country Link
JP (1) JP2016146469A (en)
KR (1) KR101871281B1 (en)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6699471B2 (en) * 2016-09-13 2020-05-27 株式会社村田製作所 Monolithic ceramic capacitors
JP6996867B2 (en) * 2017-05-16 2022-01-17 太陽誘電株式会社 Multilayer ceramic capacitors and their manufacturing methods
KR102122927B1 (en) * 2018-08-01 2020-06-15 삼성전기주식회사 Multilayered capacitor
KR102391579B1 (en) * 2018-08-01 2022-04-28 삼성전기주식회사 Multilayered capacitor
JP7302218B2 (en) * 2019-03-25 2023-07-04 Tdk株式会社 electronic components
US11705280B2 (en) * 2019-04-25 2023-07-18 KYOCERA AVX Components Corporation Multilayer capacitor having open mode electrode configuration and flexible terminations
JP7192737B2 (en) * 2019-10-07 2022-12-20 株式会社村田製作所 Base tape and electronics
JP2021075315A (en) * 2019-11-12 2021-05-20 株式会社村田製作所 Base tape and electronic component series

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002305127A (en) * 2001-04-09 2002-10-18 Tdk Corp Monolithic ceramic electronic component and method of manufacturing the same
JP2012256758A (en) * 2011-06-09 2012-12-27 Tdk Corp Electronic component and manufacturing method of the same

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101101530B1 (en) * 2010-06-24 2012-01-04 삼성전기주식회사 Multi layered capacitor
JP5246215B2 (en) * 2010-07-21 2013-07-24 株式会社村田製作所 Ceramic electronic components and wiring boards
KR101452067B1 (en) * 2012-12-14 2014-10-16 삼성전기주식회사 Multi-layered ceramic capacitor and board for mounting the same
KR20140038871A (en) * 2013-07-11 2014-03-31 삼성전기주식회사 Multi-layered ceramic capacitor and board for mounting the same

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002305127A (en) * 2001-04-09 2002-10-18 Tdk Corp Monolithic ceramic electronic component and method of manufacturing the same
JP2012256758A (en) * 2011-06-09 2012-12-27 Tdk Corp Electronic component and manufacturing method of the same

Also Published As

Publication number Publication date
KR20160094854A (en) 2016-08-10
JP2016146469A (en) 2016-08-12

Similar Documents

Publication Publication Date Title
KR101871281B1 (en) Multilayer ceramic capacitor, mounting structure of multilayer ceramic capacitor, and taping electronic component array
KR101141402B1 (en) A multilayer ceramic capacitor and a method for manufactuaring the same
JP5632046B2 (en) Multilayer ceramic capacitor and manufacturing method thereof
JP5420619B2 (en) Multilayer ceramic capacitor and manufacturing method thereof
JP5653886B2 (en) Multilayer ceramic capacitor and manufacturing method thereof
KR101486979B1 (en) Method for manufacturing monolithic ceramic electronic components
US10117333B2 (en) Multilayer ceramic capacitor, mounting structure of multilayer ceramic capacitor, and taped electronic component array
KR101565651B1 (en) Multi-layered ceramic capacitor and board for mounting the same
KR20140121726A (en) A multilayer ceramic capacitor and a method for manufactuaring the same
KR20190011219A (en) Multilayer ceramic capacitor
CN113140405B (en) Multilayer ceramic capacitor
KR101141369B1 (en) A multi-layerd ceramic condenser and fabricating method using thereof
JP2021034648A (en) Multilayer ceramic capacitor
JP2020057738A (en) Electronic component, circuit board, and mounting method of electronic component onto circuit board
KR20120076391A (en) Laminated ceramic capacitor
KR101925286B1 (en) Laminated ceramic electronic component
KR20130093034A (en) Method of manufacturing multilayer ceramic capacitor and multilayer ceramic capacitor
KR101939083B1 (en) Multi-layered capacitor and method for manufacturing the same
JP6699471B2 (en) Monolithic ceramic capacitors
JP2020053577A (en) Electronic component
US20200312568A1 (en) Multilayer ceramic capacitor
CN111180208A (en) Multilayer ceramic capacitor and method for manufacturing multilayer ceramic capacitor
KR101950715B1 (en) Multilayer ceramic capacitor
JP3264037B2 (en) Capacitor array
KR101141489B1 (en) The multi-layerd ceramic condenser and fabricating method using thereof

Legal Events

Date Code Title Description
A201 Request for examination
E90F Notification of reason for final refusal
E701 Decision to grant or registration of patent right
GRNT Written decision to grant