JPH05175425A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To prevent the malfunction of an inner circuit by alleviating the noises on a power supply voltage with a substrate--potential stabilizing diode with regard to a semiconductor integrated circuit device having a step-up circuit for stepping up the power supply voltage supplied from the outside. CONSTITUTION:A +10V generating circuit 7 steps up a power supply voltage 5V to 10V and outputs the voltage through a voltage outputting pad 35. A -10V generating circuit 8 generates -10V based on the output of the +10V generating circuit 7 and the power supply voltage 0V and outputs the voltage. A substrate-potential stabilizing diode 41 is provided between the +10V generating circuit 7 and an inner circuit 8. A substrate-potential stabilizing diode 42 is provided between the -10V generating circuit 8 and the inner circuit 9. The output voltage of the +10V generating circuit 7 and the output voltage of the -10V generating circuit 8 are supplied into the inner circuit 9 through the substrate-potential stabilizing diodes 41 and 42, respectively.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device having a booster circuit for boosting a power supply voltage supplied from the outside.

RS-23 is used in recent semiconductor integrated circuit devices.
There is a demand for a one-chip interface circuit such as 2C and a lower power supply voltage. For this reason, a one-chip semiconductor integrated circuit device has a built-in booster circuit.

[0003]

2. Description of the Related Art A package I incorporating a conventional booster circuit
C is shown in FIG. External pins 2c and 3 of package IC1
5b and 0 volt (hereinafter, volt is represented by V) is supplied to b as an operating power supply. External pins 2a, 2c
Capacitors 4a and 4b are externally attached between the terminals and 2b and 2d, and capacitors 5a and 5b are externally attached between the external pins 3a and 3c and between 3b and 3d.

A semiconductor integrated circuit device 6 consisting of one chip is housed in the package IC 1, and +1 is placed on the device 6.
0V generation circuit 7, -10V generation circuit 8, and internal circuit 9
Are formed.

The + 10V generating circuit 7 is connected to the external pins 2a to 2d of the package IC1, and the circuit 7 generates 5V between both ends of the capacitor 4a and the external pin 2a receives 10V.
Is generated. The -10V generation circuit 8 is connected to the external pins 3a to 3d of the package IC1 and is supplied with the output voltage 10V of the + 10V generation circuit 7. Then, the -10V generation circuit 8 is connected to the capacitor 5
10V is generated between both ends of b, and -10 is applied to the external pin 3d.
V is generated.

In the internal circuit 9, 10V generated by the + 10V generation circuit 7 and −10V generated by the −10V generation circuit are provided.
10V is supplied as an operating power source. FIG. 6 shows a sectional structure of the semiconductor integrated circuit device 6 configured as described above.

FIG. 6A shows a case where the substrate is an N-type semiconductor substrate 11, and the + 10V generation circuit 7 is composed of PMOS and NMOS transistors 12 and 13 and operates at 5V on the high voltage side and 0V on the low voltage side. It is configured to include a CMOS inverter circuit. The internal circuit 9 is a PMO
CMOS composed of S and NMOS transistors 14 and 15 and operating at 10V on the high voltage side and -10V on the low voltage side
It is configured to include an inverter circuit.

The P-type well diffusion regions 16 of the NMOS transistors 13 and 15 are formed separately, and the P-type well diffusion regions 16 are respectively formed into P ⁺ -type diffusion regions 17 and 18.
Since it is fixed at 0V and -10V via the
The S transistors 13 and 15 can be operated normally. In addition, the N ⁺ type diffusion region 19 is formed on the N type semiconductor substrate 11.
Is formed, the potential of the N-type semiconductor substrate 11 is fixed at 10 V by applying 10 V (boosted voltage) applied to the source of the PMOS transistor 14 to the N ⁺ -type diffusion region 19.

FIG. 6B shows a case where the substrate is a P-type semiconductor substrate 21, and the + 10V generation circuit 7 is composed of PMOS and NMOS transistors 22 and 23 and operates at 5V on the high voltage side and 0V on the low voltage side. It is configured to include a CMOS inverter circuit. The internal circuit 9 is a PMO
CMOS composed of S and NMOS transistors 24 and 25, operating on the high voltage side of 10V and on the low voltage side of -10V
It is configured to include an inverter circuit.

The N-type well diffusion regions 26 of the PMOS transistors 22 and 24 are formed separately, and the N-type well diffusion regions 26 are respectively formed into the N ⁺ -type diffusion regions 27 and 28.
Since it is fixed at 5V and 10V via the
The transistors 22 and 24 can operate normally. Further, a P ⁺ type diffusion region 29 is formed on the P type semiconductor substrate 21, and -10 V (boosted voltage) applied to the source of the NMOS transistor 25 is applied to the P ⁺ type diffusion region 29, whereby the P type semiconductor is formed. The potential of the substrate 21 is -10V
It is fixed to.

As described above, the N-type semiconductor substrate 11 is set to 10V.
Or in the case of a semiconductor chip of the type in which the P-type semiconductor substrate 21 is fixed to −10V, the potential of the substrate is unstable from the time the power is turned on until the + 10V generation circuit 7 or −10V generation circuit 8 operates normally. Therefore, a problem such as latch-up may occur. For this reason, the substrate potential stabilizing diodes 31 and 32 shown in FIG. 7A or 7B are inserted to prevent the occurrence of problems such as latch-up.

The substrate potential stabilizing diode 31 shown in FIG. 7 (a) is a P ⁺ type anode 31a and an N ⁺ type cathode 3 on an N type semiconductor substrate 11 (or N type well diffusion region).
1b is formed, 5V applied from the outside is applied to the anode 31a, and the output voltage of the + 10V generation circuit 7 is applied to the cathode 31b. Therefore,
When the power is turned on, the substrate potential stabilizing diode 31 is forward biased until the + 10V generation circuit 7 operates normally, that is, when the output voltage is 5V or less, the potential of the N-type semiconductor substrate 11 is 5V. It cannot be less than Further, when the output voltage of the + 10V generation circuit 7 becomes 5V or more, the substrate potential stabilizing diode 31 is reverse biased, and the potential of the N-type semiconductor substrate 11 is fixed to the potential of the output voltage.

The substrate potential stabilizing diode 32 shown in FIG. 7B has a P ⁺ type anode 32a and an N ⁺ type cathode 32b formed on the P type semiconductor substrate 21 (or N type well diffusion region). Externally applied 0V is applied to the cathode 32b, and the output voltage of the −10V generation circuit 8 is applied to the anode 32a. Therefore,
When the power is turned on, the substrate potential stabilizing diode 32 becomes a forward bias until the −10 V generation circuit 8 operates normally, that is, when the output voltage is, for example, 0 V or more, so the potential of the P-type semiconductor substrate 21. Never exceeds 0V. When the output voltage of the −10 V generation circuit 8 is 0 V or less, the substrate potential stabilizing diode 32 is reverse biased and the potential of the P-type semiconductor substrate 21 is fixed to the output voltage potential.

When the substrate potential stabilizing diodes 31 and 32 are provided on the semiconductor integrated circuit device 6 shown in FIG. 5, the power supply wiring 33 connecting the + 10V generating circuit 7 and the internal circuit 9 and the substrate are connected. Or between the substrate and the power supply wiring 34 that connects between the −10 V generation circuit 8 and the internal circuit 9.

FIG. 8 shows an example of the layout of the substrate potential stabilizing diode 31 when the semiconductor integrated circuit device 6 is composed of the N-type semiconductor substrate 11. The voltage output pad 35 of the + 10V generation circuit 7 is the external pin 2a (see FIG. 5).
Voltage), and the voltage input pads 36 and 37 are connected to the external pins 2b and 2c, respectively. A substrate potential stabilizing diode 31, a −10V generation circuit 8 and an internal circuit 9 are connected in parallel to a power supply wiring 33 extending from the voltage output pad 35 in an inverted L shape.

[0016]

However, since the voltage output pad 35 of the + 10V generation circuit 7 shown in FIG. 8 is connected to the external pin 2a, the voltage 5V supplied from the outside is 5V.
When there is noise, a large noise is generated in the boosted voltage of the + 10V generation circuit 7, and this noise gets on the power supply wiring 33 via the voltage output pad 35. The power supply wiring 33 includes a substrate potential stabilizing diode 31, a −10 V generation circuit 8 and an internal circuit 9.
Are connected in parallel. Therefore, in the substrate potential stabilizing diode 31, the large noise of the boosted voltage applied via the power supply wiring 33 is alleviated and the substrate potential becomes equal to the power supply voltage. However, the noise with large boost voltage is -10
Since the signal is directly propagated to the V generation circuit 8 and the internal circuit 9, there is a problem that these circuits do not operate normally.

The present invention has been made in order to solve the above-mentioned problems, and alleviates noise carried on a power supply voltage supplied from the outside by a substrate potential stabilizing diode to prevent malfunction of an internal circuit. The purpose is to be able to.

[0018]

To achieve the above object, the present invention provides a booster circuit for boosting a power supply voltage supplied from the outside, an internal circuit to which the boosted voltage of the booster circuit is supplied as an operating power supply, and a booster circuit. A semiconductor integrated circuit in which a substrate potential stabilizing diode that is reverse biased between a boost voltage and a power supply voltage during normal operation of the circuit is formed on the same semiconductor substrate, and the boost voltage of the boost circuit is applied to this semiconductor substrate. In the circuit device, a substrate potential stabilizing diode is provided between the booster circuit and the internal circuit, and the boosted voltage of the booster circuit is supplied to the internal circuit via the substrate potential stabilizing diode.

[0019]

According to the present invention, the substrate potential stabilizing diode is provided between the booster circuit and the internal circuit, and the boosted voltage of the booster circuit is supplied to the internal circuit via the substrate potential stabilizing diode. Therefore, when a large amount of noise is added to the boosted voltage of the booster circuit due to noise on the power supply voltage and the substrate potential stabilizing diode is in the forward bias state,
Since the voltage supplied to the internal circuit becomes the power supply voltage, malfunction of the internal circuit is prevented.

[0020]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment embodying the present invention will now be described with reference to FIGS.
It will be described with reference to FIG. For convenience of explanation, FIGS.
The same reference numerals are given to the same configurations as those and the description thereof is partially omitted.

FIG. 1 shows a part of the semiconductor integrated circuit device 6 of the present embodiment housed in the package IC 1. The semiconductor integrated circuit device 6 is composed of an N-type semiconductor substrate 40. The substrate potential stabilizing diode 41 is provided between the + 10V generation circuit 7 as a booster circuit and the internal circuit 9, and the diode 41 is connected to the voltage output pad 35 of the + 10V generation circuit 7 via the power supply wiring 33a. In addition, it is connected to the internal circuit 9 via the power supply wiring 33b. Therefore, the boosted voltage of the +10 V generation circuit 7 is supplied to the internal circuit 9 via the substrate potential stabilizing diode 41.

A -10V generating circuit 8 as a booster circuit is connected to the power supply wiring 33b in parallel with the internal circuit 9. The substrate potential stabilizing diode 42 is provided between the −10 V generation circuit 8 and the internal circuit 9, and the diode 42 is connected to the −10 V generation circuit 8 via the power supply wiring 43 a and the power supply wiring 43 b is connected. Through internal circuit 9
It is connected to the. Therefore, the boosted voltage of the −10 V generation circuit 8 is supplied to the internal circuit 9 via the substrate potential stabilizing diode 42.

FIG. 2 shows a part of the layout of the semiconductor integrated circuit device 6 of this embodiment. The substrate potential stabilizing diode 41 includes a planar rectangular P ⁺ -type anode 44 and an N ⁺ -type cathode 45 that is provided in a rectangular frame shape with a part cut away and is provided so as to surround the anode 44. Wiring 4 connected to the external pin 2c on the anode 44
6 is formed, and the power supply wiring 33a is formed on the cathode 45.
And 33b, a power supply wiring 33c is formed.

FIG. 3 shows a sectional structure of a main part of the semiconductor integrated circuit device 6 of this embodiment. On the N-type semiconductor substrate 40, the PMOS and NMOS transistors 14 and 15 forming the internal circuit 9 are formed. The boosted voltage of the + 10V generation circuit 7 is applied to the N ⁺ type diffusion region 19 formed on the N type semiconductor substrate 40 via the power supply wirings 33b, 33c and 33a. Therefore, the potential of the N-type semiconductor substrate 40 is 1 during the normal operation of the + 10V generation circuit 7.
It is fixed at 0V.

A P-type well diffusion region 47 is formed on the N-type semiconductor substrate 40, and the substrate potential stabilizing diode 42 has a P ⁺ -type anode 48 formed in the P-type well diffusion region 47 and an N ^+. Mold cathode 49. The anode 48 of the substrate potential stabilizing diode 42 is formed in a planar rectangular shape like the anode 44, and the cathode 49 also has a rectangular frame shape with a part cut out like the cathode 45 so as to surround the anode 48. It is provided.

The boosted voltage of the -10V generation circuit 8 is applied to the anode 48 of the substrate potential stabilizing diode 42 from the voltage output pad 50 via the power supply wiring 43a, and the power supply voltage 0V is applied to the cathode 49. .. And
P ⁺ type diffusion region 1 formed in P type well diffusion region 16
8 is connected to the power supply wiring 43b through a -10V generation circuit 8
Is applied. Therefore, the potential of the P-type well diffusion region 16 is − during normal operation of the −10V generation circuit 8.
It is fixed at 10V.

In the semiconductor integrated circuit device 6 of this embodiment, the substrate potential stabilizing diode 41 is provided between the + 10V generation circuit 7 and the internal circuit 9 and the -10V generation circuit 8 and the internal circuit 9 are provided. Substrate potential stabilizing diode 42
Is provided. Then, the boosted voltages 10V and -10V of the + 10V and -10V generation circuits 7 and 8 are supplied to the internal circuit 9 via the substrate potential stabilizing diodes 41 and 42.

Therefore, the power supply voltage 5 V supplied from the outside
When the noise in the negative direction is instantaneously applied to, a large noise in the negative direction is generated in the boosted voltage (positive) of the + 10V generation circuit 7 connected to the external pin 2a, and the noise is applied to the power supply wiring 33a.
When the boosted voltage becomes equal to or lower than the power supply voltage due to this noise, the substrate potential stabilizing diode 41 is in a forward bias state and the voltage of the power supply wiring 33a becomes equal to the power supply voltage, which is supplied to the internal circuit 9. Therefore, the malfunction of the internal circuit 9 can be prevented.

Similarly, a power supply voltage 0 V supplied from the outside
When noise in the positive direction is instantaneously applied to, a large noise in the positive direction is generated in the boosted voltage (negative) of the −10V generation circuit 8.
Get on the power supply wiring 43a. When the boosted voltage becomes equal to or higher than the power supply voltage due to this noise, the substrate potential stabilizing diode 42 is in a forward bias state and the voltage of the power supply wiring 43a becomes equal to the power supply voltage, which is supplied to the internal circuit 9. Therefore, the malfunction of the internal circuit 9 can be prevented.

Further, since the substrate potential stabilizing diode 41 is provided between the + 10V generation circuit 7 and the internal circuit 9 in this embodiment, when a negative static electricity is applied to the power supply voltage 5V, the internal static electricity is generated by this static electricity. Damage to the circuit 9 can be reduced. Similarly, since the substrate potential stabilizing diode 42 is provided between the −10 V generation circuit 8 and the internal circuit 9, when static electricity in the positive direction is applied to the power supply voltage of 0 V, the internal circuit 9 is damaged by this static electricity. Can be relaxed.

FIG. 4 shows another embodiment in which the substrate potential stabilizing diode 41 is replaced by a PMOS transistor 51.
And the N ⁺ type diffusion region 54 are formed close to each other. PM
The P ⁺ type source 52 and the drain 53 forming the OS transistor 51 are PMOS used in the internal circuit 9.
It is formed larger than the source / drain of the transistor 14. In this example, the drain 53 of the PMOS transistor 51 and the N ⁺ type diffusion region 54 form a diode.

Although the semiconductor integrated circuit device in which the substrate is the N-type semiconductor substrate 40 has been described in each of the above embodiments, it may be embodied in a semiconductor integrated circuit device in which the substrate is a P-type semiconductor substrate.

[0033]

As described above in detail, according to the present invention, it is possible to alleviate the noise on the power supply voltage supplied from the outside by the substrate potential stabilizing diode and prevent the malfunction of the internal circuit. There is an effect.

[Brief description of drawings]

FIG. 1 is a block circuit diagram showing a main part of one embodiment.

FIG. 2 is a layout diagram showing a main part of one embodiment.

FIG. 3 is a cross-sectional view showing a main part of one embodiment.

FIG. 4 is a cross-sectional view showing the main parts of another embodiment.

FIG. 5 is a schematic diagram showing a part of an example package IC.

FIG. 6 is a cross-sectional view showing a part of a conventional example.

FIG. 7 is a cross-sectional view showing an example of a conventional substrate potential stabilizing diode.

FIG. 8 is a block circuit diagram showing a part of a conventional example.

[Explanation of symbols]

 7 + 10V generation circuit as a booster circuit-8 -10V generation circuit as a booster circuit 9 Internal circuit 40 (N type) semiconductor substrate 41, 42 Substrate potential stabilizing diode

Claims (1)

[Claims] 1. A booster circuit (7, 8) for boosting a power supply voltage supplied from the outside, an internal circuit (9) to which the boosted voltage of the booster circuit (7, 8) is supplied as an operating power supply, and a booster circuit. Substrate potential stabilizing diodes (41, 42) that are reverse-biased between the boosted voltage and the power supply voltage in the normal operation of (7, 8) are formed on the same semiconductor substrate (40), and the semiconductor substrate is also formed. In a semiconductor integrated circuit device in which the boosted voltage of the booster circuit (7, 8) is applied to (40), a substrate potential stabilizing diode (41, 42) is provided between the booster circuit (7, 8) and the internal circuit (9). ) Is provided, and the boosted voltage of the booster circuit (7, 8) is supplied to the internal circuit (9) via the substrate potential stabilizing diode (41, 42). ..