JP3173030B2 - Semiconductor integrated circuit device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device capable of eliminating voltage fluctuation caused by resistance of an internal power supply line.

[0002]

2. Description of the Related Art In recent years, semiconductor integrated circuit devices, that is, super LS
As for I, the degree of integration is increasing. As a result, the size of elements in an integrated circuit, for example, the gate length of a MOS transistor, has become increasingly smaller. Therefore, in order to ensure the reliability of the entire semiconductor integrated circuit device,
The voltage applied to the internal circuit has been reduced by using an internal voltage down converter. FIG. 6 shows a configuration diagram of a main part of a conventional integrated circuit device in this case.

In a conventional integrated circuit device, an external power line 11
Is input to the internal voltage down converter 14, the output of which becomes the internal power supply line 12 and supplies a current to the semiconductor integrated circuit main body 15. Reference numeral 13 denotes an internal ground line.

FIG. 7 shows an actual configuration of a semiconductor chip 17 in a conventional semiconductor integrated circuit. Reference numerals 14 and 16 denote an internal step-down circuit and an integrated circuit block disposed in the chip 17, respectively. 12 is an internal power supply line, and 11 is an external power supply line.

[0005]

In such a conventional system, the length of the internal power supply line 12 must be increased, and as a result, the resistance of the metal wiring layer of the internal power supply line 12 is reduced. Therefore, there is a problem that the fluctuation of the power supply line potential, that is, the potential fluctuation due to the voltage drop caused by the current flowing through the internal power supply line 12 is large. There is a problem that such a voltage fluctuation of the internal power supply line causes a malfunction of the whole semiconductor integrated circuit.

An object of the present invention is to provide a semiconductor integrated circuit which can eliminate a voltage fluctuation caused by a resistance of an internal power supply line.

[0007]

According to the present invention , an external power supply is connected.
Global power lines and
And global ground lines, and multiple
And the plurality of unit circuit blocks
And receives a current supply from the global power supply line.
Supply the local power supply line potential in the unit circuit block.
Local power supply potential generating circuit and the plurality of unit circuits
Provided for each block, the current from the global ground line
And the local ground in the unit circuit block
And a local ground potential generating circuit for applying a line potential .

[0008]

[0009]

[0010]

According to the present invention, the local power supply potential generating circuit or the local ground potential generating circuit functions as a potential conversion circuit by the above configuration, so that the conventional internal step-down circuit is not required. Also, a local power supply line or a local ground line can be arranged in the unit circuit block, and the internal power supply line length of the local power supply line or the local ground line after passing through the potential conversion circuit can be effectively shortened. . As a result, it is possible to suppress a voltage fluctuation caused by a voltage drop caused by a current flowing through the internal power supply line due to the resistance of the internal power supply line wiring. Therefore, malfunction of the entire semiconductor integrated circuit can be suppressed.

[0011]

(Embodiment 1) An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a diagram showing a configuration of a main part in an embodiment of the present invention. In FIG. 1, reference numeral 1 denotes a global power supply line extending over the entire chip to which an external power supply is directly connected, and 2 denotes a local power supply in each unit circuit block 3 after receiving a current from the global power supply line 1 and performing voltage conversion. This is a local power supply potential generation circuit that supplies a power supply current to the power supply line 8. Similarly, 5 is a global ground line which is directly connected to an external ground line and extends over the entire chip. 6 is a local ground in each unit circuit block 3 after receiving a current from the global ground line 5 and performing voltage conversion. Ground wire 7
Is a local ground potential generating circuit for supplying a ground current to the circuit. That is, the local power supply potential generation circuit 2 and the local ground potential generation circuit 6 function as a potential conversion circuit.

According to the configuration of the present invention, the local power supply potential generation circuit 2 or the local ground potential generation circuit 6 functions as a potential conversion circuit, so that a conventional internal voltage down converter is not required. Also, a local power line 8 and a local ground line 7
Need only supply a current to each unit circuit block 3, and its length is also the length of each unit block (from several μm to several 1 μm).
0 μm). For this reason, voltage fluctuations generated in the local power supply line 8 and the local ground line 7 due to the resistance of the power supply line become extremely small. Further, the local power supply potential generating circuit 2 shields the area between the global power supply line 1 and the local power supply line 8, and the local ground potential generating circuit 6 shields the space between the global ground line 5 and the local ground line 7 so that noise is reduced in each unit block. Does not flow out to the global power line 8 and the global ground line 5. Thereby, a stable operation of the whole semiconductor integrated circuit device can be further realized.

In this embodiment, both the local power supply potential generating circuit and the local ground potential generating circuit are used. However, using either one of them has a certain effect.
In this case, there is an advantage that the configuration is simplified as compared with the first embodiment. FIGS. 2 and 3 show the configuration of the main part in this case.

Next, an example of the configuration of a local power supply potential generating circuit and a local ground potential generating circuit used in configuring an embodiment of the present invention will be described. FIG. 4 shows a main part configuration diagram in that case.

As can be seen from this figure, in this embodiment,
As the local power supply circuit 2, an N-type MOS transistor having a gate electrode connected to the global power supply line 1 is used. As the local ground potential generating circuit 6, a P-type MOS transistor having a gate electrode connected to the global ground line 7 is used.

The operation in this case will be briefly described. In FIG. 4, a local power supply line 8 is a source electrode for an N-type MOS transistor used as a local power supply potential generation circuit 2, and a local ground line 7 is a P-type MOS transistor used as a local ground potential generation circuit 6. Is the source electrode. As a result, the potential of local power supply line 8 is set lower than the potential of global power supply line 1 by the threshold voltage Vtn of the N-type MOS transistor, and the potential of local ground line 7 is similarly set to the potential of global ground line 5. The voltage is set higher than the threshold voltage Vtp of the P-type MOS transistor. That is, the power supply voltage in each unit circuit block 3 can be set lower than the external power supply voltage by Vtn + Vtp. As a result, the voltage applied to the transistors in each unit block decreases, and reliability can be ensured. In addition, the signal amplitude in each unit block is also small, and low current consumption can be realized.

(Embodiment 2) Next, FIG. 5 shows a configuration of a main part of an example of an actual mask layout in the circuit configuration of FIG.

In FIG. 5, NMOS 1 and PMOS 1
Reference numeral 2 corresponds to the local power supply potential generation circuit 2 and the local ground potential generation circuit 5 in FIG. In this layout, the unit circuit block 3 has a so-called standard cell scale. The feature of this layout is that, as shown in FIG. 5, an NMO (local power supply potential generating circuit) 2 is arranged in parallel with global power supply line 1 and global ground line 5.
The gate electrode of S1 and the gate electrode of PMOS2, which is the local ground potential generating circuit 6, are arranged at the same time. This makes it possible to automatically provide the power generation capability according to the size of the unit circuit block 3.

Further, the threshold voltage of the N-type MOS transistor and the threshold voltage of the P-type MOS transistor used in the unit circuit block 3 and the N-type MOS transistor used as the local power supply potential generating circuit 2 By setting the threshold voltage of the NMOS 1 and the threshold voltage of the PMOS transistor PMOS2 used as the local ground potential generating circuit 6 to different values, the voltage applied to the transistors in the unit circuit block 3 is set. Can be adjusted, and both high speed and high reliability of the entire semiconductor integrated circuit can be achieved. As a method of realizing such different threshold voltages, for example, a method of changing an impurity implantation amount for setting a threshold voltage, a method of changing a material of a gate electrode between corresponding transistors, and a method of changing a work function. There are various methods, such as a method of realizing the same by changing the thickness of a gate oxide film in a corresponding transistor portion.

[0021]

According to the structure of the present invention, since the local power supply potential generating circuit or the local ground potential generating circuit functions as a potential conversion circuit, a conventional internal voltage down converter is not required. The local power supply line or the local ground line only needs to supply a current to each unit circuit block, and the length may be the length of each unit block (several μm to several tens μm). For this reason, voltage fluctuations generated in the local power supply line and the local ground line due to the resistance of the power supply line are extremely small. In addition, the local power supply circuit shields between the global power supply line and the local power supply line, and the local ground potential generation circuit shields the space between the global ground line and the local ground line. Noise is reduced from each unit block to the global power supply line and the global ground line. Do not leak to Thereby, a stable operation of the whole semiconductor integrated circuit device can be further realized.

[Brief description of the drawings]

FIG. 1 is a main part configuration diagram of a semiconductor integrated circuit device according to a first embodiment of the present invention.

FIG. 2 is a main part configuration diagram of an embodiment having only a local ground potential generating circuit.

FIG. 3 is a main part configuration diagram of an embodiment having only a local power supply potential generation circuit.

FIG. 4 is a main part configuration diagram of an embodiment including a local power supply potential generation circuit and a local ground potential generation circuit of the present invention.

FIG. 5 is a layout diagram of a semiconductor integrated circuit device according to a second embodiment of the present invention.

FIG. 6 is a configuration diagram of a main part of a conventional semiconductor integrated circuit device.

FIG. 7 is a configuration diagram of a semiconductor chip in a conventional semiconductor integrated circuit device.

[Explanation of symbols]

 Reference Signs List 1 global power supply line 2 local power supply potential generating circuit 3 unit circuit block 4 signal wiring between unit circuits 5 local ground potential generating circuit 6 local ground line 8 local power supply line

Claims (5)

(57) [Claims] A global power supply line and a global ground line connected to an external power supply and extending over the entire chip; a plurality of unit circuit blocks disposed inside the chip; and a plurality of unit circuit blocks provided for each of the plurality of unit circuit blocks. A local power supply potential generating circuit that receives supply of current from the global power supply line and supplies a local power supply line potential in the unit circuit block; and a local power supply potential generation circuit that is provided for each of the plurality of unit circuit blocks and supplies current from the global ground line. receiving, a semiconductor integrated circuit device characterized by comprising a local ground potential generating circuit for providing a local ground line potential of the unit circuit block. As wherein prior Symbol local power source potential generating circuit, using the N-type MOS transistor having a gate electrode connected to the global power line, as the local ground potential generating circuit, P-type and a gate electrode connected to the global ground line MO
According to claim 1, characterized by using the S transistor
The semiconductor integrated circuit device. 3. A-threshold voltage-threshold voltage and the P-type MOS transistor of the N-type MOS transistor used in the units of the circuit blocks, Suresh of N-type MOS transistor used as a local power source potential generating circuit 3. The semiconductor integrated circuit device according to claim 2, wherein at least one of a hold voltage and a threshold voltage of a P-type MOS transistor used as a local ground potential generating circuit is set to different values. 4. A global power supply line, a global ground line, a local power supply potential generating circuit for receiving a current from the global power supply line and supplying a local power supply line potential in a unit circuit block using standard cells, and the global power supply line. A local ground potential generating circuit for receiving a current supplied from a ground line and providing a ground potential in the unit circuit block; and an N-type local gate potential circuit having a gate electrode connected to the global power line as the local power potential generating circuit. A P-type MOS transistor having a gate electrode connected to the global ground line is used as the local ground potential generating circuit, and a gate electrode of an N-type MOS transistor used as the local power supply potential generating circuit is connected to the global ground potential generating circuit. Place it parallel to the power line, and A gate electrode of a P-type MOS transistor used as a ground potential generating circuit is arranged in parallel with the global ground wiring. 5. A-threshold voltage-threshold voltage and the P-type MOS transistor of the N-type MOS transistor used in the units of the circuit blocks, Suresh of N-type MOS transistor used as a local power source potential generating circuit 5. The layout of the semiconductor integrated circuit device according to claim 4, wherein at least one of the hold voltage and the threshold voltage of the P-type MOS transistor used as the local ground potential generating circuit is set to different values.