JPH05166803A - Compound semiconductor device - Google Patents

Abstract

PURPOSE:To obtain a compound semiconductor device having a surface protection film capable of preventing the generation of defects, such as film peeling. CONSTITUTION:The wiring of each device is installed in a specified portion of a base insulation film by an Au wiring 2. There are laminated consecutively an SiON layer 3 which is excellent in adhesive properties with the Au and a SiN layer 4 which is excellent in moisture resistance. There is also provided a contact hole 6, which is used for a multi-layer wiring, on the SiON layer 3 and the SiN layer 4 on the Au wiring 2. This construction makes it possible to provide a compound semiconductor device having a surface protection film which is excellent in adhesive properties with the Au wiring 2, maintaining moisture resistance to a satisfactory extent.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a compound semiconductor device in which gold is used as a wiring metal.

[0002]

2. Description of the Related Art Generally, a structure in which two layers of a PSG (phosphorus-containing SiO ₂ ) layer and a silicon nitride layer are laminated is often used as a surface protection film of a semiconductor device. The lower PSG layer has a function of trapping an alkali such as Na (sodium), and the upper silicon nitride layer has a function of preventing water from entering from the outside. Therefore, it is extremely effective in ensuring the reliability of the integrated circuit when the plastic package is used. Furthermore, the PSG layer and the silicon nitride layer often have a combination in which the respective stresses are reversed and cancel each other, and also have a function of preventing stress migration and film cracking.

This technique is disclosed in Japanese Patent Laid-Open No. 59-
The details are described in JP-A-80936 and JP-A-59-80937.

[0004]

However, when the above-mentioned surface protective film is applied to a compound semiconductor IC device such as GaAs (gallium arsenide) in which gold is used as a wiring metal, gold and PSG or silicon oxide is used. Adhesion to the object is poor, film peeling occurs, and PSG on the gold wiring
However, there is a problem in that it cannot be directly deposited.

An object of the present invention is to obtain a compound semiconductor device which solves the above problems.

[0006]

According to the present invention, in a compound semiconductor device in which gold is used as a wiring metal, the surface protection film has a lower layer made of silicon oxide nitride and an upper layer made of silicon nitride. It is characterized by having a layered structure.

[0007]

According to the present invention, the use of silicon nitride as the upper layer of the surface protective film ensures sufficient moisture resistance of the compound semiconductor device. Furthermore, the use of silicon oxide nitride in the lower layer improves the adhesion between the surface protective film and the wiring material gold.

Since the stresses of the silicon nitride layer and the silicon oxide nitride layer are opposite to each other, the stresses are offset by controlling the film thicknesses thereof, and no cracks occur.

[0009]

EXAMPLES Examples of the present invention will be described below.

FIG. 1 is a view showing a sectional structure of a surface protective film of a compound semiconductor device according to an embodiment of the present invention. Wiring of each element is formed by a wiring layer (hereinafter referred to as Au wiring) 2 made of gold (Au) on a predetermined portion of the base insulating film 1 on the substrate on which the semiconductor element is formed. This Au
On the base insulating film 2 including the wiring 2, a silicon oxide nitride (hereinafter referred to as SiON) having excellent adhesion with Au.
Layer 3 and silicon nitride (hereinafter,
Layers 4 (referred to as SiN) are sequentially stacked. Further, the contact hole 6 used for multi-layer wiring is the Au wiring 2.
It is provided on the upper SiON layer 3 and SiN layer 4.

According to this structure, it is possible to obtain a surface protective film having good adhesion to the Au wiring 2 while ensuring sufficient moisture resistance. Further, since the stresses in the SiON layer 3 and the SiN layer 4 are in opposite directions, the stress can be offset by controlling the thickness of each layer, and the generation of cracks can be prevented.

FIG. 2 is a diagram showing a step of forming the above-mentioned surface protective film. The forming method performed by the present inventor will be specifically described.

First, an Au wiring 2 was formed by an ion milling method on a predetermined portion of a base insulating film 1 on a substrate on which a semiconductor element was formed (shown in FIG. 2A). After that, the SiON film 3 was laminated on the base insulating film 1 on which the Au wiring 2 was formed by a plasma CVD method (shown in FIG. 2B). The film forming conditions at this time are SiH ₄ flow rate 3
The flow rate was 00 sccM, NH ₃ flow rate 800 SCCM, N ₂ O flow rate 500 SCCM, radio frequency (RF) power 200 W, temperature 280 ° C., and pressure 1 Torr. The SiON film 3 formed under these conditions has a refractive index of 1.95, a film thickness of 2000 Å, and a stress of 3.0 × 10 ⁸ N.
/ M ² .

Next, the SiN film 4 was laminated by the plasma CVD method (shown in FIG. 3C). The film forming conditions at this time are as follows: SiH ₄ flow rate 300 SCCM, NH ₃ flow rate 500 S
CCM, RF power 150W, temperature 300 ° C, pressure 1T
It was orr. The formed SiN film 4 has a refractive index of 2.0, a film thickness of 1000 Å, and a stress of −.
It was 6.0 × 10 ⁸ N / m ² .

Next, a mask pattern 5 having an opening in a contact hole forming region was formed by using a photoresist by a usual lithography technique (shown in FIG. 3D). Subsequently, reactive ion etching (RIE) is performed through the mask pattern 5 to remove S on the Au wiring 2.
An opening was formed in the iON film 3 and the SiN film 4. The conditions at this time are as follows: SF ₆ flow rate 50 SCCM, RF power 200
It was W and the pressure was 70 mTorr.

After that, the mask pattern 5 was removed and a surface protective film was formed (shown in FIG. 2E).

A semiconductor device having a surface protective film formed by the above method was subjected to a high temperature and high humidity accelerated test using a plastic mold package.
This plastic mold package is heated to 130 ℃,
As a result of storing in an atmosphere with a humidity of 85%, it was confirmed that the complete failure-free time was 360 hours and the average life was 700 hours. Further, since the stress on the SiON film 3 and the stress on the SiN film 4 are opposite to each other, the stress can be offset by stacking them.

The above-mentioned film forming conditions are merely examples, and the conditions such as the film thickness can be changed depending on the material.

[0019]

As described above, according to the compound semiconductor device of the present invention, since the surface protective film which is excellent in moisture resistance and adhesion to the Au wiring and does not cause cracks or the like is used, Improves reliability.

[Brief description of drawings]

FIG. 1 is a cross-sectional view of a surface protective film according to an example of the present invention.

FIG. 2 is a diagram showing a process of forming a surface protective film according to an example.

[Explanation of symbols]

1 ... Base insulating film, 2 ... Au wiring, 3 ... SiON layer, 4 ...
SiN layer, 5 ... Mask pattern.

Claims (1)

[Claims] 1. A compound semiconductor device in which gold is used as a wiring metal has a surface protective film having a two-layer structure including a lower layer made of silicon oxide nitride and an upper layer made of silicon nitride. And a compound semiconductor device.