JP3246348B2 - Protective film structure of semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a structure of a protective film formed on a surface of a semiconductor device.
The present invention relates to a structure of a protective film formed by laminating an iON layer and a Si ₃ N ₄ layer.

[0002]

2. Description of the Related Art On a surface of a semiconductor device using a substrate made of GaAs or the like, a plurality of insulating thin films are laminated for various purposes to constitute a protection (passivation) film. With respect to such a protective film, conventional techniques of interest to the present invention include, for example, Japanese Patent Publication No. 2-8455, Japanese Patent Application Laid-Open No. 3-225828, and Japanese Patent Application Laid-open No. Hei 3-225828.
No. 268430.

In Japanese Patent Publication No. 2-8455, GaAs is used.
A structure of a protective film formed by laminating a plurality of Si ₃ N ₄ layers on a substrate is disclosed (first related art). JP-A-3-
Japanese Patent No. 225828 discloses that a plurality of S
A structure of a protective film formed by laminating iON layers is disclosed (second prior art). JP-A-3-268430 discloses a structure in which a SiON layer is used for a first layer or a first layer closest to a GaAs substrate and a second layer next to the GaAs substrate, and a Si ₃ N ₄ layer is used for an outer layer portion. (Third prior art).

[0004]

However, each of the first to third prior arts has the following problems to be solved. First, in the first prior art, the moisture resistance is sufficient because the Si ₃ N ₄ layer that does not allow moisture to pass through is laminated, but the adhesion strength between GaAs and Si ₃ N ₄ is relatively low, so that the thermal resistance is low. Problems such as floating of the protective film during the environmental test that causes the cycle and peeling of the protective film during the wire bonding step may occur. Therefore, sufficient reliability has not been obtained for a protective film having a laminated structure using a Si ₃ N ₄ layer.

Next, in the second prior art, the SiON G
Since the adhesive strength to aAs is high and a stress-free protective film is easily obtained, the above-mentioned problems such as floating and peeling are solved. However, the protective film having a laminated structure using an SiON layer has insufficient moisture resistance due to the property of high water permeability inherent to SiON, and sufficient reliability has been obtained in this regard. Hard to say.

From the above considerations, in a protective film having a laminated structure, a SiON layer having excellent adhesion to GaAs is formed at the lowermost layer portion such as the first layer closest to the GaAs substrate, and an outer layer above it is formed. A third conventional technique, such as forming a Si ₃ N ₄ layer having good moisture resistance in a portion, is conceived. However, simply changing the configuration of the protective film as in the third conventional technique does not provide sufficient performance and has many process restrictions. This will be described below.

First, if an SiON layer is formed in the lowermost layer portion closest to the GaAs substrate, the adhesion to GaAs is improved. For example, when an IC is formed, usually, such an ICN is formed on the SiON layer. Since a thin film resistor is formed, etching for forming a resistance pattern is frequently used. In this case, it is necessary to go through a wet or dry etching step using SiON as a base, but SiON is Si ₃ N for almost all etching species including fluorine.
_It has a higher etching rate than that of ₄ , increases the amount of over-etching of the base, and increases restrictions on process selection.

Second, when the SiON layer is used for both the first layer and the next second layer closest to the GaAs substrate,
Similarly, although the adhesion strength with GaAs is improved, for example, when forming an IC, SiON of the second layer is used as a MIM capacitor material indispensable for the IC. At this time, while the relative dielectric constant of Si ₃ N ₄ is 7 or more,
Since the relative dielectric constant of iON is usually 5 or less, the area of the capacitor electrode increases to obtain the same capacitance,
As a result, there is a disadvantage that the cost is increased.
It is also conceivable to increase the capacity by reducing the thickness of the SiON layer, but this is not preferable in terms of reliability. From such a disadvantage, there is a process restriction that it is difficult to use the second SiON layer as an MIM capacitor.

Third, assuming that the above-mentioned restriction can be avoided.
Also pay close attention to layout patterns and film thickness settings
Otherwise, the desired performance cannot be obtained. That is, SiON
Is inherently inferior in moisture resistance, so at least
The outermost layer is Si_ThreeN _FourLayered configuration
And avoid a configuration in which even the edge of the SiON layer is exposed.
There must be. Even in this case, trust in moisture resistance
In consideration of the properties, it is desirable that the SiON layer be as thin as possible.
Preferably, in the third prior art structure, the SiON layer is thick.
There is a disadvantage that it is too much.

An object of the present invention is to provide a protective film structure of a semiconductor device which can solve the above-mentioned problems.

[0011]

SUMMARY OF THE INVENTION The present invention is directed to a protective film having a laminated structure of a SiON layer and a Si ₃ N ₄ layer formed on a surface of a semiconductor device. In order to solve the technical problem described above, the following features are provided. That is, the protective film, a layer other than the outermost layer, the layer in contact with the surface of the semiconductor substrate is composed of SiON layers, the upper of the protective film
Outermost predicate is composed of Si ₃ N ₄ layer, further, the Si ₃ N ₄ layer constituting the outermost layer, is characterized in that it includes a portion that contacts the semiconductor substrate.

A semiconductor device to which the present invention is applied is protected
Bonding pad formed by etching away film
Parts, preferably the outermost layer
_ThreeN _FourThe layer is a layer that defines this bond pad
The opening edge of the protective film is covered.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIGS. 1 to 9 are for explaining an embodiment of the present invention, and are implemented for manufacturing a semiconductor device including a field effect transistor (FET) using GaAs. The steps are shown sequentially. First, as shown in FIG. 1, a GaAs substrate 2 having an active layer 1 formed in a desired region by an ion implantation method is prepared.

Next, as shown in FIG. 2, a SiON layer 4 as a first insulating layer 3 and a Si ₃ layer are formed on the entire surface of the GaAs substrate 2 by using a plasma CVD method.
An N ₄ layer 5 is formed. At this time, for example, the temperature of the substrate 2 is set to 300 ° C., and the atmospheric pressure is set to 0.5 Torr.
(= 66.5 Pa), the switching from the formation of the SiON layer 4 to the formation of the Si ₃ N ₄ layer 5 is performed for the SiON layer 4 by SiH ₄ : 20 SCCM and NH ₃ : 50 SC
CM, N ₂ O: 40 SCCM, N ₂ : 200 SCCM,
Then, for the Si ₃ N ₄ layer 5, SiH ₄ : 30S
CCM, NH ₃ : 80 SCCM, N ₂ : 200 SCC
M, for example, by switching the flow rate of the source gas.

Next, as shown in FIG. 3, in order to remove the insulating layer 3 in the region where the FET is to be formed, a resist pattern is formed and etching is performed. Then, FIG.
As shown in FIG. 5, ohmic electrodes 6 and 7 serving as a drain electrode and a source electrode having a laminated structure of Au: Ge / Ni / Au are formed, and as shown in FIG. 5, a laminated structure of Ti / Pt / Au is formed. Is formed. Thus, the basic part of the FET is completed.

Next, in the same manner as the first insulating layer 3,
As shown in FIG. 6, over the entire surface of the GaAs substrate 2,
An SiON layer 10 as a second insulating layer 9 and subsequently a Si ₃ N ₄ layer 11 are formed. This second insulating layer 9
Has a thickness of, for example, 2000 mm. The second insulating layer 9 has a laminated structure of the SiON layer 10 and the Si ₃ N ₄ layer 11, and has the SiON layer 1 near the gate electrode 8.
0 is in contact with the GaAs substrate 2.

Thereafter, as shown in FIG. 7, a contact portion with an upper electrode (not shown), for example, an ohmic electrode 6 is formed.
The second insulating layer 9 is etched away at the bonding pad portion 12 and the scribe line 13 indicated by a dashed line. Next, as shown in FIG. 8, a Si ₃ N ₄ layer 14 as a _third insulating layer serving as an outermost layer is
It is formed over the entire surface of the aAs substrate 2. This Si ₃
The thickness of N ₄ layer 14 is, for example, 5000 °.

Thereafter, as shown in FIG. 9, a Si ₃ N ₄ layer 14 as a _third insulating layer is formed in a contact portion with the upper layer electrode including the above-mentioned bonding pad portion 12, a scribe line 13, and the like. Is etched away. For this etching removal, after forming a pattern with a photoresist, for example, a reactive ion etching method using CHF ₃ or O ₂ gas is applied.

Thus, the protective film of the illustrated semiconductor device is composed of the first insulating layer 3 composed of the SiON layer 4 and the Si ₃ N ₄ layer 5, the SiON layer 10 and the Si ₃ N ₄ layer 11.
, And a laminated structure including a Si ₃ N ₄ layer 14 as a _third insulating layer. Si ₃ N ₄ constituting the outermost layer as a third insulating layer
The layer 14 has a portion in contact with the GaAs substrate 2 as seen near the scribe line 13.
As a result, the Si ₃ N ₄ layer 14 becomes the SiON layer 10 and the Si ₃ N ₄ layer 1 included in the second insulating layer 9 thereunder.
1 are completely covered up to their edges.

When attention is paid to the bonding pad portion 12, the opening edge of the protective film that defines the bonding pad portion 12 is formed of the Si ₃ N ₄ layer 1 constituting the outermost layer.
4 is covered. That is, as well shown in FIG. 10, the opening 15 formed in the Si ₃ N ₄ layer 14 in the step of FIG. 9 is different from the opening 16 formed in the second insulating layer 9 in the step of FIG. Be reduced. For example, opening 15
Is made 3 μm smaller than the opening 16. In this way, the Si ₃ N ₄ layer 14 is formed in the opening 1 of the SiON layer 10 and the Si ₃ N ₄ layer 11 included in the second insulating layer 9 thereunder.
6 covering the edge.

According to the above embodiment, since the SiON layer 4 or 10 included in the protective film is brought into contact with the GaAs substrate 2, the adhesion strength of the protective film to the GaAs substrate 2 can be increased. it can. This means
For example, in a scratch test, SiON was Si ₃
With about twice the adhesion strength of the N _4, from the experimental result that,
Moreover, when GaAs is heated in the atmosphere, even if an oxide of Ga or As is produced, its nitride is never produced, which is supported.

Also, the first and second insulating layers 3 and 9
In either case, the outer layer side _ThreeN_FourLayer 5 or 1
1 and the third insulating layer is made of Si_ThreeN_Four
It is constituted by the layer 14. Such Si_ThreeN_Four
Have a low etching rate, and_ThreeN_Four
Etch on any of layers 5, 11 and 14
Metal thin-film resistors that require patterning
It becomes easy to do.

The first and second insulating layers 3 and 9
In case of using any of the MIM capacitor of the IC also, by reducing the SiON layer 4 or 10 in the SiON / Si ₃ N ₄ structure, reduction of the capacitance value is not a few problems. Thus, the SiON layers 4 and 1
Making the value of 0 thinner is not a problem at all from the gist of the present invention, but is rather preferable.

In the semiconductor device including the GaAs substrate 2, the outermost layer of the protective film is composed of the Si ₃ N ₄ layer 14 so that the Si device having high reliability with respect to moisture resistance as a whole is obtained.
In a state of covered with ₃ N ₄ layer 14. Therefore, the effect of preventing moisture from entering the semiconductor device can be improved. Also, in the opening of the bonding pad portion 12, the second insulating layer 9 having the laminated structure of the SiON layer 10 and the Si ₃ N ₄ layer 11 is completely covered with the Si ₃ N ₄ layer 14 without being exposed. It has a broken structure. Therefore, even Si ₃ intrusion of water from the opening
This can be prevented by the N ₄ layer 14, and the reliability of the semiconductor device can be further improved.

In the above-described embodiment, the GaAs substrate 2 is used as the semiconductor substrate. However, the present invention is not limited to this, and the present invention is applied to a semiconductor device having a semiconductor substrate made of another material. be able to. The present invention also provides a GaAs ME used as an active device for a communication device in a microwave or quasi-microwave band, for example.
It is advantageously applied to chip-shaped semiconductor devices such as SFETs and MMICs.
The present invention is not limited to such an FET and the like, and may be another active element.

[0026]

As it is evident from the foregoing description, according to the present invention, since the most part in contact with the semiconductor substrate is made of a SiON obtained a high adhesion strength of the protective film, the adhesion strength of the protective film to the semiconductor substrate Therefore, it is possible to suppress occurrence of defects such as floating when subjected to a thermal cycle and peeling during wire bonding on the protective film, and a highly reliable semiconductor device can be obtained.

The outermost layer of the protective film is made of Si ₃ N ₄
Since the Si ₃ N ₄ layer constituting the outermost layer has a portion in contact with the semiconductor substrate , the semiconductor device as a whole has a high reliability with respect to moisture resistance.
₃ N covered are thus _four layers. As a result, this Si ₃
The N ₄ layer can enhance the effect of preventing moisture from entering the semiconductor device.

As described above, according to the present invention, Si
By skillfully combining the ON layer and the Si ₃ N ₄ layer, both the increase in the adhesion strength between the semiconductor substrate and the protective film and the improvement in the moisture resistance are achieved. When introducing the MIM capacitor or the MIM capacitor, there is no restriction on the process. Therefore, the present invention can provide advantages also in manufacturing a semiconductor device.

In the present invention, the semiconductor device has a bonding pad portion formed by etching and removing the protective film, and the Si ₃ N ₄ layer forming the outermost layer defines the protective film defining the bonding pad portion. Is covered, the SiON layer is not exposed even at the edge, so that intrusion of moisture from the edge of the opening of the protective film is prevented by the high moisture resistant Si ₃ N. _This can be prevented with _four layers, and the reliability of the semiconductor device can be further improved.

[Brief description of the drawings]

FIG. 1 is an illustrative sectional view showing a first step performed for manufacturing a semiconductor device according to an embodiment of the present invention;

FIG. 2 is an illustrative sectional view showing a second step performed for manufacturing the semiconductor device according to one embodiment of the present invention;

FIG. 3 is an illustrative sectional view showing a third step performed for manufacturing the semiconductor device according to the embodiment of the present invention;

FIG. 4 is an illustrative sectional view showing a fourth step performed for manufacturing the semiconductor device according to the embodiment of the present invention;

FIG. 5 is an illustrative sectional view showing a fifth step performed for manufacturing the semiconductor device according to the embodiment of the present invention;

FIG. 6 is an illustrative sectional view showing a sixth step performed for manufacturing the semiconductor device according to the embodiment of the present invention;

FIG. 7 is an illustrative sectional view showing a seventh step performed for manufacturing the semiconductor device according to the embodiment of the present invention;

FIG. 8 is an illustrative sectional view showing an eighth step performed for manufacturing the semiconductor device according to the embodiment of the present invention;

FIG. 9 is an illustrative sectional view showing a ninth step performed for manufacturing the semiconductor device according to the embodiment of the present invention, showing a state where a desired protective film is formed;

10 is an illustrative plan view showing the relationship between the size of an opening 15 of the Si ₃ N ₄ layer 14 and the size of the opening 16 of the second insulating layer 9 in the state shown in FIG. 9;

[Explanation of symbols]

2 GaAs substrate 3 first insulating layer 4, 10 SiON layer 5, 11 Si ₃ N ₄ layer 6, 7 ohmic electrode 8 gate electrode 9 second insulating layer 12 bonding pad portion 13 scribe line 14 Si constituting the outermost layer ₃ N ₄ layer 15, 16 opening

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 21/318

Claims (2)

(57) [Claims] 1. A structure of a protective film formed on the surface of the semiconductor device, wherein the protective film has a laminated structure of a SiON layer and the Si ₃ N ₄ layer, in the protective layer, the outermost layer a layer other than the layer in contact with the surface of the semiconductor substrate is composed of the SiON layer, the outermost layer of the protective film, the Si ₃ consists of N ₄ layer, Si ₃ N constituting the outermost layer A protective film structure for a semiconductor device, wherein the _four layers include a portion that contacts a semiconductor substrate. 2. The semiconductor device includes a bonding pad portion formed by etching and removing the protective film, and a Si ₃ N ₄ layer forming the outermost layer has a bonding pad portion that defines the bonding pad portion. Covering the opening edge,
A protective film structure for the semiconductor device according to claim 1.