JPH05161114A - Emphasis circuit - Google Patents

Abstract

PURPOSE:To reduce the memory capacity by connecting a 4-phase time inversion circuit in parallel with the post-stage of an HPF composed of a digital filter, applying high pass processing to a time inversion signal obtained from them, applying time base inversion to the resulting signal and adding the signal to a current input signal. CONSTITUTION:An input signal (a) is fed to 4-phase time base inversion circuits 52-55 via an HPF 51. The signal is given to the circuits 52-55 and read from them while time is deviated by the time corresponding to the impulse response converging time. Then the output signal is supplied selectively to HPFs 58, 59 with changeover switches 56, 57, in which high pass processing is applied and a synthesis output signal (g) is obtained via a changeover switch 60. Then the signal (g) is subjected to time base inversion by a time inversion circuit 61 and the signal is added to the signal (a) via a limiter 27 and a horizontal nonlinear emphasizing output signal (i) is obtained. Thus, the memory capacity used for the time base inversion circuit is reduced and the circuit scale is decreased.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an emphasis circuit suitable for being applied to a VTR for analog high-definition signals.

[0002]

2. Description of the Related Art A plurality of emphasis circuits are used in a recording / reproducing system of a video device for recording / reproducing a video signal, for example, a VTR (HDVTR) for recording / reproducing a high-definition signal as an analog signal.

FIG. 8 is a system diagram showing an example thereof. The recording signal Y and the pair of color difference signals PB and PR are converted into digital signals (component signals) by A / D converters 11, 12 and 13, respectively. After that, the encoder 14
And is subjected to various kinds of signal processing. Various signal processes include a data distribution process, a shuffling process, etc., including a mapping process performed in a digital VTR or the like.

The encoder 14 has a time-division multiplexing processing function in addition to these signal processings. For example, two-channel recording signals S1 (Y, PB) time-division multiplexed by this function.
No. time-division multiplexed signal) and S2 (Y, PR time-division multiplexed signal) are formed.

The recording signals S1 and S2 are supplied to the vertical emphasis circuits 15 and 18 to be subjected to vertical emphasis processing and then to the horizontal non-linear emphasis circuit 1.
6 and 19 to provide the emphasis characteristic in the horizontal direction, especially the non-linear emphasis characteristic.
The non-linear characteristic in the horizontal direction is to limit a particularly large amplitude component.

Thereafter, the D / A converters 17 and 20 convert the signals back into analog signals, which are then supplied to the analog signal processing circuit 21 to be converted into a signal form suitable for recording and recorded by the corresponding recording heads Ha and Hb. It The reproduction system is the reverse process of the recording system.

As the horizontal nonlinear emphasis circuit 16 (19 is omitted) used in the recording system 10 shown in FIG. 8, a circuit as shown in FIG. 9 is used.

In the figure, the recording signal S1 supplied to the input terminal 25 is supplied to a high-pass filter 26 to extract a signal (high-pass output signal) corresponding to the contour of the recorded image, and the extracted high-pass output signal is limited. After the high frequency band is limited at 27, a predetermined gain K is applied by the amplifier 28. This limiter output signal is the adder 2
At 9, the recording signal S1 is added to the current recording signal S1 to obtain the recording signal S1 with the emphasis characteristic at the terminal 30.

Horizontal non-linear emphasis circuit 16, 1
Since 9 is a digital signal processing system, a digital filter as shown in FIG. 10 is often used as the high-pass filter 26 used therein.

As the digital filter shown in FIG. 10, an IIR type filter is shown. In the figure, 31 is an input terminal, 32 and 35 are adders, 33 is a unit delay element,
Reference numeral 34 is a coefficient unit. With such a configuration, a signal to which a desired high-pass filter characteristic is added is output to the output terminal 36 as is well known.

By the way, it is known that the phase characteristic of the horizontal non-linear emphasis circuit 16 shown in FIG. 9 is a non-linear characteristic. On the other hand, it is also known that if the horizontal non-linear emphasis circuit 16 is configured as shown in FIG. 11, its phase characteristic can be made linear.

First, the configuration and operation of FIG. 11 will be described. The high-pass filter 26 has the first and second high-pass filters 26 as shown in FIG.
And high-pass filters 40 and 42 and first and second time inverting circuits 41 and 43. As the high-pass filters 40 and 42, IIR type digital filters are used.

A delay circuit 44 is provided between the current input signal a and the adder 29. This is to compensate for the time delay due to the use of the two time inversion circuits 41 and 43.

The emphasis characteristic of this figure will be described with reference to FIG. 12. Considering a rectangular wave input signal a as the recording signal S1 as shown in FIG. 12A, the first high-pass output signal b of FIG. It is obtained, and this is output by the time inverting circuit 41 with its time axis inverted. Time inversion circuit 4
As No. 1, a FILO (First In Lost Out) type line memory can be used.

As a result, the first time-inverted signal c shown in FIG. 6C is output, and the second high-pass filter 42 obtains the second high-pass output signal d shown in FIG. The second high-pass output signal d is output again with its time axis inverted by the second time inversion circuit 43, so that the second time inversion signal e shown in FIG. A predetermined limiter is applied, and the limiter output signal and the current input signal a are added to obtain an emphasis output signal f as shown in FIG.

Even when the high-pass filter 26 including the time-axis inversion processing system is used in this way, a predetermined emphasis characteristic can be imparted, but its phase characteristic will be compared with FIG. When FIG. 9 is expressed by a transfer function on the z plane, the transfer function H (z) of the high-pass filter 26 is H (z) = (1-z ⁻¹ ) / (1-k 1 · z ⁻¹ ) ... .. Since it can be expressed as (1), the emphasis characteristic Emp1 in FIG.
Is, Emp1 = 1 + k2 {( 1-z -1) / (1-k1 · z -1)} becomes ... (2). Substituting z = exp (jωτ) (τ is the impulse response convergence time of the high-pass filter 26) into Equation 2,
Since the imaginary term remains in Expression 2, it can be seen from this that the phase characteristic is non-linear in the configuration of FIG.

[0017] On the contrary, emphasis characteristic EMP2 shown in FIG. 11, Emp2 = 1 + k2 · H (z) · H (z -1) = 1 + k2 [{(2- (z + z -1)} / {1 + k1 2 - k1 (z + z ⁻¹ )}] ... (3) When z = exp (jωτ) is substituted into Equation 3, as in Equation 2, Equation 3 becomes as follows: Emp2 (exp (exp ( jωτ)) = 1 + k2 { 2 (1-cosωτ) / (1 + k 2 -2k1 · cosωτ)} ···· (4) next, it is understood that the imaginary term is canceled. in other words,
When performing the high-pass processing while including the time inversion processing as shown in FIG. 11, the horizontal non-linear emphasis circuit 16 can have a linear phase characteristic. Since it is desirable that the phase characteristics be linear in a recording / reproducing system such as a VTR, it is expected that the configuration of FIG. 11 will be frequently used.

[0018]

Although it has been shown that the time inverting circuit as described above may be used to make the phase characteristic linear, the time inverting circuits 41 and 43 are shown in FIG. 13, for example. A pair of memories 4 having such a FILO configuration
It is conceivable to use 5,46. These memory 4
Reference numerals 5 and 46 can output a signal input thereto by performing a write operation and a read operation such that the first written data is read last, by inverting (reversing) its time axis. .. Because of this time axis inversion processing, as shown in the figure, the input and output changeover switches 47, which are switched in conjunction with the pair of memories 45, 46,
48 is required. Each is a 1H line memory, and writing and reading are alternately performed for each 1H.

As described above, the time inversion circuits 41 and 43 require at least two line memories, and the delay circuit 4
No. 4 uses a pair of 2H line memories selectively, so that a total of eight line memories are required in the configuration shown in FIG. Since the recording / reproduction is performed in two channels, 8 × 4 = 32 line memory is eventually required, and there is a drawback that the circuit scale increases.

Therefore, the present invention solves such a conventional problem, and proposes an emphasis circuit using a time inverting circuit which can reduce the memory capacity as much as possible.

[0021]

In order to solve the above-mentioned problems, according to the present invention, an emphasis circuit which performs time reversal processing to obtain an emphasis output signal having a linear phase characteristic is constituted by a digital filter. A high-pass filter, a four-phase time inverting circuit connected in parallel to the subsequent stage of the high-pass filter and using a memory corresponding to the impulse response convergence time of the high-pass filter, and high-pass processing the time-inverted signals obtained from each A high pass filter, a time inverting circuit for inverting the high pass output signal in time, and an adder for adding the output signal to the current input signal.

[0022]

As shown in FIGS. 1, 4 and 5, the input signal a is high-pass processed by the first high-pass filter 51, and the first high-pass output signal b is four-phase period time inversion circuits 52-55. Is supplied to. Time inversion circuit 52-
55 is sequentially shifted by a time τ corresponding to the impulse response convergence time, and its writing and reading are performed in units of 2τ.

Then, the first time-reversed signal c is obtained from the first changeover switch 56, and the second time-inverted signal d is obtained from the second changeover switch 57. These high-pass output signals e and f are combined by the third changeover switch 60 to obtain a combined output signal g, which is further subjected to time inversion processing to obtain a third time inversion signal h.
The third time inversion signal h is added to the current input signal a after the high amplitude level is limited by the limiter 27. As a result, a horizontal non-linear emphasis output signal i is obtained.

The above-mentioned time inverting circuits 52 to 55 and 6
In each case 1, the memory having the memory capacity for the time corresponding to the impulse response convergence time is used.
The memory capacity can be significantly reduced compared to the conventional one.

[0025]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, a case where an example of the emphasis circuit according to the present invention is applied to the horizontal non-linear emphasis circuit of the above-mentioned analog high definition VTR will be described in detail with reference to the drawings.

FIG. 1 shows a concrete example of a horizontal non-linear emphasis circuit 16 (19 is omitted) to which the present invention is applied. Since the basic structure is the same as that of FIG. As the time inverting circuit 41 to be provided in the filter 26, four-phase time inverting circuits 52 to 54 are used as shown in the figure. In this example, two high pass filters 58 and 59 are used as the ones equivalent to the high pass filter 42 of FIG.

Each of the time inversion circuits 52 to 55 uses a memory capable of accumulating data for a time corresponding to the impulse response convergence time τ of the high pass filter 51 (corresponding to the high pass filter 40 in FIG. 11).

In this example, the memory capacity of at least 2τ is designed so that the filter processing can be performed without losing the data. FIG. 2 shows a concrete example of the time inversion circuit 52. A FILO (First In Lost Out) type memory is used as a memory for performing the time inversion process, and a pair of memories 63 and 64 are used.
Are used, and changeover switches 65 and 66 are provided before and after the memories 63 and 64, respectively, so that writing and reading can be performed alternately.

Since the time inverting circuits 52 to 55 of the parallel configuration carry out the write processing in a state of being sequentially shifted by the time τ, and the unit of writing and reading is 2τ as described above, the time inverting circuits 52 to 55 of the time inverting circuits 52 to 55 respectively. The writing process and the reading process are as shown in FIG.

In this example, since approximately 10 samples of the input signal a correspond to 1τ, they are processed in units of 1τ. For example, when the input signals A and B are written in the time inversion circuit 52, these are time inverted at the next timing. Read out. The time-inverted input signal is shown with "-1 power". The writing process and the reading process in which the time axis is inverted are alternately executed. Other time inversion circuit 53
The same applies to ~ 55.

In the embodiment, the time axis-inverted output signal is finally selected so as to have the same time series as the input signal a, so that the combined output of the time axis inversion signals is shown in FIG. Like However, since this combined output has been described for the sake of convenience, the output signals of the time inversion circuits 52 to 55 are not combined into a time series signal as shown in FIG.

In this example, a pair of high-pass filters 58 and 59 are provided so as to obtain a time-series output signal as shown in FIG.
Of the output signals of the time inverting circuits 52 and 54, an output signal in units of τ is selectively supplied by the changeover switch 56 to perform high-pass processing. Similarly, the output signals of the time inversion circuits 53 and 55 are selected by the changeover switch 57 and high pass processing is performed.

The second and third high-pass output signals e and f are supplied again to the third changeover switch 60, and the third changeover switch 60 shown in FIG.
A combined output signal g having a time series as shown in (6) is obtained. Second and third high pass filters 58, 59
In both cases, an IIR type digital filter is used.

The time inversion circuit 61 to which the combined output signal g is supplied is also constructed as shown in FIG. 2 and its explanation is omitted.

The delay circuit 62 is configured by using two 2τ memories, which is for delaying the current input signal a by the same time as the time delay of the emphasis output signal h. Therefore, as its configuration, the memory of 2τ is used as the memory of FIG.

Now, the emphasis processing operation of the horizontal non-linear emphasis circuit 16 thus constructed will be described with reference to FIG.
And it demonstrates in detail with reference to FIG.

Also in this example, the recording signal S1 to be used is the rectangular-wave-shaped input signal a as shown in FIG. 4A.

The input signal a is the first high-pass filter 51.
Is subjected to high-pass processing, and the first high-pass output signal b (B in the figure) is supplied to the time inverting circuit 52 of the first phase for time-axis inverting processing. The waveforms of the write signal and the read signal in the time inversion circuit 52 are shown in FIG.

If the processing start time point is t1, the time axis is inverted at this time point t2 and the reading is performed.
The first high-pass output signal b1 is the write signal c as it is.
The value becomes 1, and the read signal c2 is obtained by inverting the time axis. Thereafter, similar writing and reading processes are performed, and this is performed for each phase. As a result, the write signal and the read signal of the time inversion circuits 53 to 55 are as shown in D to F of FIG.

The time-reversed signal c selected by the first changeover switch 56 is as shown in FIG. 9G, and the time-reversed signal d selected by the second changeover switch 57 is shown in FIG.
Then, these are high pass processed. Then, the second and third high-pass output signals e and f shown in FIGS.

Second and third high pass output signals e, f
Are combined by the third changeover switch 60, the combined output signal g at that time is as shown in FIG. 5L, and a high-pass output that is the same as the time series of the input signal a and in which only the time axis is inverted is obtained. This combined output signal g is the time reversal circuit 61.
As a result of performing the time-axis inversion processing again with, a third time-inversion signal h as shown in FIG. 7M is obtained, which is limiter-processed by the limiter 27 and then added with the current input signal a by the adder 29. To be done. Therefore, the emphasis output signal i having the horizontal non-linear characteristic as shown in FIG. 5N is obtained at the terminal 30. The phase characteristic of the emphasis output signal i is the same as that in FIG.

FIG. 6 shows another example of the present invention. The memory used for the time inversion circuit 52 and the like in the embodiment of FIG. 1 is an example in which a so-called 1-port memory is used after writing 2τ worth of data and reading the same data. When this 1-port memory is used, the time inverting circuit must have a 4-phase configuration as shown in FIG.

However, when a so-called 2-port memory is used as the memory for inverting the time axis, the reading process can be performed simultaneously with writing in one memory. Therefore, when the 2-port memory is used, With the two-phase configuration, the same processing as described above can be achieved.

FIG. 6 shows a specific example of the horizontal nonlinear emphasis circuit 16 when the 2-port memory is applied to the time inverting circuit. In this case, since the time axis inversion processing can be performed in the two-phase configuration as described above, the two-phase time inversion circuits 65 and 66 are used and the time inversion signals j and k obtained from them are used in the high-pass filter. It is supplied to 58 and 59 for high-pass processing. The high-pass output signals l and m obtained from the respective signals are combined in time series by the changeover switch 60.

For both the time inverting circuit 61 and the delay circuit 62 in the subsequent stage, a 2-port memory having a capacity of 2τ is used as the memory. Therefore, the delay circuit 62 has 2
Two τ 2-port memories will be used.

The operation of this configuration will be described with reference to FIG. 7. The time inversion circuit 65 outputs the first high-pass output signal b shown in FIG.
A time-reversed signal j of is obtained. That is, since the time-axis reverse reading (in the α direction) is performed from time t1, and the time-axis reverse reading is performed from time t2,
The time-reversed signal j is as shown in FIG.

Similarly, the time inversion circuit 66 outputs the second time inversion signal k shown in FIG. This is because the reverse reading is performed with reference to the time point t1 ', and then the reverse reading is performed from the time point t2'.

As a result, the high-pass filters 58 and 59 output the second and third high-pass output signals 1 and m shown in E and F of FIG. The combined output signal n
Is the same as in the same figure G, and the third time-inverted signal p shown in FIG. 7H is output by inverting this in the time axis. Therefore, the third time-inverted signal p subjected to the non-linear processing by the limiter 27 is currently input. When added to the signal a, the emphasis output signal q subjected to the nonlinear processing in the horizontal direction as shown in I of FIG. 5 is obtained as in the case of FIG.

The above-described embodiment is a case where the present invention is applied to a horizontal non-linear emphasis circuit, but it is an emphasis circuit using a high-pass filter such as a horizontal emphasis circuit, a vertical emphasis circuit, a vertical non-linear emphasis circuit, and has phase characteristics. The present invention can be applied to an emphasis circuit that needs to be linear.

[0050]

As described above, the emphasis circuit according to the present invention can realize an emphasis circuit having a linear phase characteristic by skillfully combining the time inversion circuits.

According to this, since it is possible to use the memory capable of storing the data corresponding to the impulse response convergence time, the memory capacity used for the time inversion circuit can be remarkably reduced as compared with the conventional case. Therefore, the entire circuit scale can be significantly reduced as compared with the conventional one.
It is extremely suitable when applied to a signal processing system such as TR.

[Brief description of drawings]

FIG. 1 is a system diagram showing an example in which an emphasis circuit according to the present invention is applied to a horizontal non-linear emphasis circuit.

FIG. 2 is a system diagram showing a specific example of a time inversion circuit.

FIG. 3 is an explanatory diagram of a horizontal non-linear emphasis operation.

FIG. 4 is a waveform diagram for explaining a horizontal non-linear emphasis operation.

FIG. 5 is a waveform diagram for explaining a horizontal non-linear emphasis operation.

FIG. 6 is a system diagram showing another example of a horizontal nonlinear emphasis circuit.

FIG. 7 is a waveform diagram for explaining the operation.

FIG. 8 is a system diagram showing a recording system of an analog high definition VTR.

FIG. 9 is a system diagram of a horizontal nonlinear emphasis circuit.

FIG. 10 is a system diagram showing an example of a high-pass filter.

FIG. 11 is a system diagram showing an example of a horizontal nonlinear emphasis circuit in consideration of phase characteristics.

FIG. 12 is a waveform diagram for explaining the operation.

FIG. 13 is a system diagram showing an example of a time inversion circuit.

[Explanation of symbols]

 10 recording system 14 encoder 15 and 18 vertical emphasis circuit 16 and 19 horizontal non-linear emphasis circuit Ha and Hb magnetic head 26 high-pass filter 27 limiter 51, 58 and 59 IIR type digital filter 52 to 55, 61 time inversion circuit 45 and 46 FILO type Line memory 63, 64 FILO type memory

Claims (2)

[Claims] 1. An emphasis circuit in which time-inversion processing is performed to obtain an emphasis output signal having a linear phase characteristic. In the emphasis circuit, a high-pass filter composed of a digital filter and a high-pass filter connected in parallel to the latter stage of the high-pass filter are provided. A four-phase time inversion circuit using a memory equivalent to the impulse response convergence time of the filter, a high-pass filter for high-pass processing the time-inversion signal obtained from each, and a time inversion circuit for time-inversion of this high-pass output signal, An emphasis circuit comprising an adder for adding the output signal to the current input signal. 2. When using a 2-port memory as the memory used for the time inverting circuit, a two-phase time inverting circuit is used as the time inverting circuit connected to the subsequent stage of the high-pass filter. Claim 1
Emphasis circuit described.