JPS60143481A - Reproducing method of sound signal - Google Patents

Abstract

PURPOSE:To reproduce a sound signal even at the time of reproduction of a variable speed of a VTR by storing once a reproduction sound digital signal, and reading the signal from the memory while the reading address counter of the memory is reset compulsively. CONSTITUTION:When a RAM(A)12 operates writing, a RAM(B)13 operaters reading. On the other hand, when the RAM13 operates writing, the RAM12 operates reading. By delaying the clock signal of a reading address counter 20 from an input terminal 22 more than that of a writing address counter 19 from an input terminal 21 at this time, read-out of the signal from the RAM(A)12 or the RAM(B)13 is delayed, and the extension of a reproduction sound digital signal is executed. By executing the switching by a switching signal 18 so as to read the signal from the other RAM when read-out of the signal from one RAM terminates, the sound digital signal which is recorded by compression is extended, and is inputted to a DA converter 14 as the original sound digital signal.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method for reproducing an audio signal in an apparatus for recording and reproducing a video signal and a digitized audio signal.

Conventional Structures and Problems The method of converting an analog audio signal into a digital signal and recording and reproducing it produces high quality audio signals. By converting analog audio signals to digital signals,
Because signals can be easily compressed, expanded, divided, and merged, video tape recorders (
By using a VTR (hereinafter abbreviated as VTR), it becomes possible to record and reproduce audio digital signals along with video signals using a video head.

VTRs that are currently widely used use two heads to alternately record and reproduce video signals one field at a time. When one of the two heads is recording or reproducing a video signal, the other head is not recording or reproducing a video signal. By recording or reproducing the audio digital signal using this head that is not performing recording or reproducing, it is possible to efficiently record and reproduce the video signal and the audio digital signal. To achieve this,
As shown in FIG. 1, the first head 3 and the second head 4 on the cylinder 2 may be brought into contact with the co-pregnancy tape 1 for a period necessary to record and reproduce the audio digital signal. At this time, the signals to each head are as shown in FIG. 2, and the recording state on the tape is as shown in FIG. 3. Here ■1. V2 is a one-field video signal from the heads 3 and 4, respectively, and Dl and D2 are audio digital signals. That is, an audio signal corresponding to a period of one field of the video signal is compressed as a digital signal and recorded before one field of the video signal.

Object of the Invention An object of the present invention is to provide a method for reproducing the audio digital signal even during variable speed reproduction of a VTR and converting it into an analog audio signal. By storing the signal in one memory and reading the signal from the memory while forcibly resetting the read address counter of the memory, it is possible to reproduce the audio signal even during variable speed reproduction of a VTR.

Description of examples A block diagram of one embodiment of the present invention is shown in FIG.

11 is an input terminal for the audio digital signal reproduced from the VTR, and 12.13 is a RAM (Random Access BM) for storing the reproduced audio digital signal.
14 is a DA converter that converts a digital signal into an analog signal, 15 is an analog audio signal output terminal, 16.17 is a RAM address signal changeover switch, and 1st is a changeover switch 16.17. 19 is a counter that generates a RAM write address, 20 is a counter that generates a RAM read address, 21 is an input terminal for the clock signal of the write address counter, and 22 is a clock signal for the read address counter. The input terminal 23 is an input terminal for a reset signal of the read address counter.

Next, its operation will be explained. The timing relationship of each signal is shown in FIG.
The data is alternately written one field at a time into the RAM (b) 13 and read out again alternately, converted into an analog signal by the DA converter 14, and outputted to the output terminal 16 as an audio signal. That is, when RAM (C) 12 is performing a write operation, RAM (B) 13 is performing a read operation, and conversely, when RAM (B) 13 is performing a write operation,
This means that the RAM (to) 12 is performing a read operation.

At this time, switching between the write address and the read address is performed by the changeover switch 16, 1, using the changeover signal 18 from the readout address counter 20. Furthermore, at this time, by making the clock signal of the read address counter 2o from the input terminal 22 slower than the clock signal of the write address counter 19 from the input terminal 21, the In in the RAM (75:) 12 is
From AM (B) 13 (D signal reading is delayed, and the reproduced audio digital signal is expanded. Then, one of the R
When the reading of the signal from the AM is completed, the switching signal 18 is used to read the signal from the other RAM, and the audio digital signal that was compressed and recorded is expanded and restored to its original state. Become a voice digital. In this way, the audio digital signal is reproduced during steady running. Note that the reset signal from the input terminal 23 is not used in this case.

Next, when playing a VTR at variable speed, Figure 6 shows 3.
The trajectory of the head on the tape when played back at double speed is shown.

Since the tape speed during playback is three times that of recording, the head does not pass over the recorded signal, but instead scans the location shown by the dotted line, and the audio digital signal is played back every second field, As shown in the figure, the audio digital signal input to the DA converter 14 also becomes a signal in which two fields are missing. However, the signal input to the DA converter 14 is the same in frequency as during steady running,
Although there is a loss of two fields in the converted analog audio signal, it is fully possible to recognize it as an audio signal.

However, in an actual VTR, if the rotational speed of the head is the same, the scanning distance of the video signal is
Compared to , when playing back, it is shorter as y. By increasing the speed, the time axis of the video signal is made to be the same as when driving. As a result, as shown in Fig. 8, the time axis of the reproduced audio digital signal at 3x speed is faster than the reproduced audio digital signal during normal running, corresponding to the faster rotational speed of the head, and the cutting timing is faster. The timing with the switching signal will gradually shift, causing an inconvenience.

Therefore, as shown in FIG. 9, a reset signal is created from a head switching signal synchronized with the reproduced audio digital signal at 3x speed, and is input to the input terminal 23 to forcefully reset the read address counter 20. Then, a switching signal 18 is generated. As a result, the audio digital signal read out from the RAM is transferred to the other R before being read out to the end.
Although it will be switched to AM, it is possible to synchronize with the reproduced audio digital signal, making it possible to reproduce the audio signal at 3x speed. Also, there will be some missing parts in the reproduced audio digital signal from the RAM, but this is only the rate at which the rotational speed of the head has changed, that is, the ratio of the travel distances X and y of the head, so it may be very small.
Since the reproduced audio digital signal is originally missing two fields at a time, there is no effect due to the omission of the reproduced audio digital signal in the RAM.

Although the explanation has been given above regarding the case of triple-speed playback, it is obvious that the audio signal can be reproduced in the same manner during other double-speed playbacks.

Next, in the case of low-speed reproduction, the rotational speed of the head is conversely slowed down, so as shown in FIG. 10, the time axis is longer than during steady running. However, by creating the switching signal 18 in synchronization with the reset signal in the same way at double speed, there is a slight interval between when all the audio digital signals are read out from the RAM and when switching to the other RAM. Since it is synchronized with the reproduced audio digital signal, it is possible to reproduce the audio signal.

Effects of the Invention The present invention uses a simple method of forcibly resetting the read address generation circuit of the memory to reproduce the audio signal during variable speed reproduction of the VTR by changing the frequency of the clock signal of the reproduction circuit, etc. This can be achieved without changing the circuit, and its practical effects are great.

[Brief explanation of the drawing]

Fig. 1 is a diagram showing the relationship between the head of a video tape recorder and the tape, Fig. 2 is a signal format diagram corresponding to Fig. 1, Fig. 3 is a recording state diagram showing the audio state recorded on the tape, Figure 4 is a block diagram of a playback device that implements the audio signal playback method of the present invention, Figure 5 is a timing chart of signals corresponding to Figure 4, and Figure 6 shows signal playback on tape at 3 times the same speed. The state diagrams, FIG. 7, FIG. 8, and FIG. 9 are signal timing charts for triple speed playback, and FIG. 10 is a signal timing chart for low speed playback. 11...Input terminal, 12...RAM,
13...RAM, 14...AD converter, 16...output terminal, 16.17...
Changeover switch, 19...Write address counter, 2o...Mountain/read address counter, 21,2
2, 23... Input terminal. Name of agent: Patent attorney Toshio Nakao and 1 other person 2nd
Fig. 1J31!1 Fig. 4 Fig. 5 Fig. → 5 No. DA friend λ force fξ Fig. 6 Tape running direction G-11 Fig. 7 B Fig. 9 RAM (B) opening

Claims (1)

[Claims] A memory circuit that stores an audio digital signal during playback, a circuit that generates a write address for this memory circuit,
By forcibly resetting the circuit that generates the read address,
A method for reproducing an audio signal, characterized in that the audio signal can be reproduced even during variable speed reproduction.