JPS6242303A - Pitch expanding device for magnetic recording signal - Google Patents

Abstract

PURPOSE:To reduce noise produced at signal connection by using an analog shift register so as to make the clock frequency at write/read equal to the ratio of a reproducing tape speed to a recording tape speed thereby applying pitch expansion of a reproducing signal. CONSTITUTION:Two clocks being in opposite phase to each other are required to drive semiconductor delay elements BBDs 10, 20 as analog shift registers. For example, 1024-stage of BBDs are used, to which 512-pulse read clocks CR are applied during the read period and 512-pulse write clocks CW are required naturally at the write period. The write/read are executed by the same clock frequency at the same time and the pitch expansion processing is applied finally as to the information by the 512-pulse of the write clocks CW just before the start of read. Signals (a), (b) written in the BBDs 10, 20 by using the write clocks CW are read by the read clocks CR and the pitch is kept equal to that at the recording even in the high speed reproduction.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention provides a method for reproducing signals recorded on a magnetic tape at a tape speed faster than at the time of recording, by keeping the pitch of the reproduced signal equal to that at the time of recording and only changing the time axis. This invention relates to a compressing pitch expansion device.

2. Description of the Related Art In general, when reproducing a signal recorded on a tape recorder or the like, it may be necessary to reproduce the signal at a faster speed than when it was recorded. For example, when you want to quickly understand the contents of a long meeting or quickly find a necessary location on a tape.

In response to these demands, simply increasing the tape speed during playback will change the pitch of the playback signal, resulting in a decrease in clarity and a very difficult to hear playback sound. Needs to be compressed.

Conventional techniques related to this include the following methods, as introduced in the July 26, 1976 issue of Nikkei Electronics J published by Nikkei McGraw-Hill.The first method is (1. There is a method that uses a random access memory (RAM) that can write and read signals in an area, and converts the pitch based on the ratio of the address change speed when writing to and reading from the RAM. There is a method of converting the pitch by using a BBD, which is an analog shift register, and linearly changing the delay time of the BBD.

Problems to be Solved by the Invention However, in the above two systems, for example, in the first system, due to its structure, AD and DA converters are used.

There is a problem in that the device is expensive because it requires RAM and the like. In addition, in the second method, since the BBD is used as a variable delay line, it is necessary to change the clock frequency non-linearly with respect to time, which has the problem of complicating the circuit configuration and requiring troublesome adjustments. Ta. Furthermore, since the signal is divided into segments for processing, a harsh noise is generated at the joints of the segments, which significantly impairs the intelligibility.

In view of the above-mentioned problems, the present invention provides a pitch expansion device for an 8-key recording signal that can compress the time axis in an inexpensive and simple manner without impairing clarity.

Means for Solving the Problem In order to achieve this object, the pitch expansion device for the calm signal of the present invention sets the read clock pulse to a frequency proportional to the ratio of the recording tape speed to the playback tape speed. The reproduction signals are written alternately to the two analog shift registers using the write clock pulses, and the read signals are sequentially read from both analog shift registers by the read clock pulses so as to overlap for -mOM, and the read reproduction signals are During the overlapping period, one side: - gradually attenuates, and the other side gradually recovers, and the attenuation 2
The recovery characteristic also has a frequency characteristic, and the reproduced signal after the attenuation and recovery processing in the overlapping period is mixed and 1.1
The purpose is to obtain the playback signal of the channel.

In the present invention, the read periods in the two analog shift registers are set so that they overlap each other, with the start end being near the other end and the end end being near the start end of the other. The pitch-expanded signals obtained from the analog shift registers are each gradually and frequency-attenuated for the superimposition period, and
By combining the two, noise during signal connection is reduced, making it possible to obtain a reproduced signal that is more natural and has higher clarity.

EXAMPLE Hereinafter, an example of the present invention will be described with reference to the drawings.
I will clarify. FIG. 1 shows the basic configuration of a pitch expansion device for magnetic recording signals in an embodiment ζτ of the present invention. In FIG. 1, 10.20 is a semiconductor delay element BBD as an analog shift register, and in this embodiment, a BBD with 1024 delay stages is used. Since two clocks with opposite phases are required to drive the BBD, 1
To record information on all 024 stages, 612 pulses are required for the cock signal on one side.

30 is the fixed cylinder wave number f. This is an oscillation circuit that generates

Here, the value of f, , is the variable write clock frequency f
, and the fixed read clock frequency fR. In this embodiment, the playback speed is discontinuously variable, and for example, the write clock frequency 9 is set to 1.5f, 2.0f to a fixed readout clock frequency fR.
Since it can be set to 2x, 2.5x, and 3.0x, it is necessary to
0 is at least 30 times fR. 40 is a fixed frequency f. This is a minute circuit that divides the signal of , and generates a write clock Cw and a read clock CR having the required frequencies f, , fR. 50.60 is the write clock CW and read, and the clock CR is switched to BBDl.
This is a switch circuit that supplies signals to the terminals o and 20. 70 inputs the readout 17 soku CR obtained from the frequency dividing circuit 4o and inputs 1.
, taking advantage of the switching time of the switch circuits 5O and 60,
The decoding circuit 100, which will be described later, also receives an ijl control signal.
Supply-t',"w11]1.l control circuit.

80.90d Soti, Zene's B B D 10, 2
This is an attenuation circuit that attenuates the volume of the output of 0 according to the frequency. Is 100 the signal from the control circuit To? , Takumi,
A plurality of analog switches in the attenuation circuits 80 and 90 are sequentially opened and closed. +10 is attenuation circuit 80.9
This is a mixing circuit that synthesizes 0 outputs. 120 is a low-pass filter that smoothes the combined output from the mixing circuit 110.

The operation of the 8K recording signal pitch expansion device configured as described above will be described below. The aforementioned control circuit T
The switch control signals of the switch circuit 60 and 60 obtained from O are A and B in FIG.

In these switch control signals A and H, the signal LI H
The period of the tqhT+ level corresponds to a read period in which the read L7 cross clock OR is selected, and the "Low" level corresponds to a write period in which the write clock CW is selected. In this example, since a 1024-stage BBD is used, during the read period, the read clock OR of 812 pulses is used.
[The write clock Cw is set so that the clock signal Cw is supplied with 512 pulses during the write period. Therefore, for example, the aging period during double-speed playback is 1j) j full 1 time and 91: half of the time is fine, but the 2nd page's sui nobu 4 is the same as the second one.

BK small size, "L (TIF'" 1...During the bell period, if you always supply one sho lΔ micro,..., riCW, BBD
All 7 pieces of information in 1024 columns! - Write - 1'h, after that, 1 writing and reading are performed simultaneously at the same 11 times l'] 1, and finally the writing clock just before the start of reading, /7Cw 512 pulses Pitch expansion processing is performed on the information for the minute. In other words, regarding the playback speed, how many times is the playback speed? 1. It is sufficient to always supply the write clock C during a certain interference period 1. Waveforms a and b in Figure 2 are BBI) 1o and 20 respectively : indicates h, I, \-j signals, and with this method, 4-gauge 8
Deletion of the number F+-1tJ1 would result in T, but fortunately the audio number t' is redundant! : It is generally known that deleting part of the signal has little effect on its intelligibility. With the write clock CW, the signals a, b (t, poet output 15. Taro I and C9 are written to 13'BD1Q, l and 20).
) As shown in Figure 2, α and β, in order to obtain a waveform with a partially extended pitch, even during accelerated playback, The pitch can be kept the same as when recording.C Also, as mentioned earlier, when splicing BBD output signals, the problem is how to process the joint.This is because the pitch of the two BBDs is Since the phases of the output signals coincide with each other by chance, it is possible that the phases of the output signals coincide with each other. This is because the output signals of the two BBDs have harmonic components.In this example, one of the output signals of the two BBDs is sequentially attenuated (11) and the other is sequentially restored (2) during the period in which they overlap, and the high frequency region is attenuated. By providing frequency characteristics that perform recovery, the problematic noise at the seams is significantly reduced and clarity is improved.

Here, a specific circuit configuration of the control circuit To is shown in FIG.

The read clock signal CR of frequency fR obtained from the frequency dividing circuit 4o is divided into 1/64 by the first counter 71, and this is further input to the second counter 72, where the frequency is divided by 1/8.

Here, the output terminals O9, 0, 0, of the second counter 72
In other words, at the moment when all three outputs become "High," the second counter 7
When a pulse is applied to the reset terminal R of the second counter 72, the second counter 72 operates as a hexadecimal counter.
1. o Find the logical product of the signals obtained from 7 h. Therefore, the period of t High n shown in A in Fig. 4 is exactly 2 BBI) 10.20 output signal (α in Fig. 2, β
) to obtain a waveform corresponding to the pattern bone period. The waveform of the person in Figure 4 is converted to J- using a frequency divider γ3 such as a flip-flop.
If the frequency is divided by 2, the duty cycle is 60% and the first
The waveform obtained by dividing the output of the counter 71 by 1/(Fig. 4B)
) can be obtained. This signal B in Fig. 4 and the fourth
By calculating the logical sum and logical product of the signals shown in FIG.
1Iil control signals, that is, C and D in FIG. 4 (corresponding to A and B in FIG. 2) are obtained. For example, A and B in Figure 4
Taking the logical sum of 'H' in C of Figure 4 means
igh “Reveno L: Akira Dawachi, -71-out,
Considering the period between Jtl1 and 72, if the second counter 72 is used as a normal octal counter, it is completely different from the 'Htgh' level period of the 7-frequency divided waveform of the read clock OR obtained at the flip-flop output terminal at J-. In other words, it is clear that 612 pulses of the read clock 8 are included during the read period in C and D of FIG.

In this way, the required switch control signal can be obtained.

In addition, the person in FIG. 4 corresponds to "puff" when the second counter 72 is used as an octal counter, and therefore the superimposition period shown in A in FIG. 4 is % of the readout period. , in the end, out of 512 nodes during the read period, there are 64 times from the start and end of the read period.This superimposition period,
Using an AND gate or the like, the first counter 71 inputs 16 pulses obtained by dividing the read clock CR into % to the third counter 74.
Counts from "0" to 15" and decodes the circuit 10.
16 levels of attenuation are determined by 0.

Therefore, the attenuation amount changes by one step every four read clocks. Here, the attenuation is set in stages such that the attenuation is maximum during each of the four pulse periods from the start and end of the read period, and the attenuation is zero during the 61st to 64th pulse sections from the start and end, respectively. Furthermore, during the period when no pulse is input to the third counter 4, the value immediately before is held, so that the attenuation amount is maximum during the readout period excluding the superimposition period, and the attenuation circuits 80 and 90 act as switches to control the output of the BBD. It turns out that it is also working.

FIG. 5 shows the specific structure of the attenuation circuits 80 and 90. The attenuation circuit 80.90 has 16 analog switch output terminals connected to one end of the resistor, arranged in parallel, and inputs the output signal of the BBD to the commonly connected analog switch input terminal, and also connects the output terminal of the analog switch to one end of the resistor. One end is also common and further grounded through a capacitor O. Here, the control terminals of the analog switches are each connected to a decoding circuit 100, and the analog switches are opened and closed at appropriate timings according to control signals from the decoding circuit 100, and eventually one of the resistors R1 to R46 and the capacitor C are connected to each other. The voltage is divided to obtain the desired amount of attenuation.

In this embodiment, the maximum attenuation amount is 40 dB and the minimum attenuation amount OdB, and 16 levels of attenuation are set by selecting appropriate values for the resistors R1 to R16.

If you do not use the method of superimposing attenuated waveforms as in this example, but simply make the volume of the connection part gradually approach the zero value and connect each other near the zero value, the output waveform obtained at this time will be an envelope-shaped waveform. It has been confirmed through experiments that if you listen to this a lot, the sound has the disadvantage that it sounds like a tremolo.

On the other hand, in this example, the above-mentioned symptoms are greatly alleviated by superimposing waveforms whose attenuation amounts are gradually increased and decreased. Furthermore, since the attenuation characteristics also have frequency characteristics, it is possible to remove unnecessary harmonic components that are the cause of noise generated at signal joints, suppressing noise from this point as well, resulting in more natural clarity. It became possible to obtain a high output signal.

Further, all signal processing in this embodiment is performed digitally using C-MOS gates, etc., so the configuration is simple and no adjustment parts are required. For example, as introduced in the conventional example, BBD
In a method in which the delay time of BBD is linearly varied, when attempting to superimpose using a plurality of BBDs, the setting of the superimposition period requires troublesome adjustment and is unstable.

In contrast, in this embodiment, the length of the superimposition period, the amount of attenuation, etc. can be easily determined by digital processing, and no adjustment is required, which is very advantageous in terms of circuit configuration.

Effects of the Invention As described above, the present invention uses an analog shift register such as a BBD to expand the pitch of a reproduced signal by making the clock frequency during writing and reading equal to the ratio of the reproduction tape speed and the recording tape speed. In addition, by attenuating the frequency of the BBD output signal and superimposing it, it is possible to reduce the noise generated during signal connection, and to realize a pitch expansion device that is inexpensive, simple, and has high clarity, and its practical effects are great. be.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a pitch expansion device of a Haki recording and reproducing device according to an embodiment of the present invention, FIG. 2 is a diagram showing the time relationship of signal processing according to the same embodiment, and FIG. FIG. 4 is a diagram showing the time relationship of part of the signal processing process according to the same embodiment, and FIG. 5 is a specific circuit diagram of other main parts in the same embodiment. 10.20...Analog shift register, 80
゜90... Attenuation circuit, 110... Bexing circuit, 120... Low pass filter. Name of agent: Patent attorney Toshio Nakao and 1 other person
1 Figure 2 Figure T...Further tightening

Claims (1)

[Claims] A playback signal reproduced at a tape speed faster than the tape speed during recording is transmitted to the first clock pulse by a first clock pulse set at a frequency proportional to the ratio of the recording tape speed to the playback tape speed with respect to the second clock pulse. and a second analog shift register alternately and selectively, and the written reproduction signal is caused to overlap with the reproduction signal read out from both the analog shift registers for a part of the period by the second clock pulse. One of the read out reproduction signals is gradually attenuated during the overlapping period, and the other is gradually recovered, and the attenuation,
A pitch expansion device for a magnetic recording signal, characterized in that the recovery characteristic also has a frequency characteristic, and the reproduction signal after attenuation and recovery processing in the overlapping period is mixed to produce a one-channel reproduction signal.