JPH032795A - Audio signal reproducing device - Google Patents

Abstract

PURPOSE:To reproduce more recorded contents by setting a ratio of the total sum of sampling time length to that of reject time length of a reproduced audio signal in response to a function of the reproducing speed. CONSTITUTION:Reproducing means 102 and 103 which reproduce the audio signal recorded on a magnetic tape at a reproducing speed higher than the recording speed and a sampling means 27 which samples and rejects the reproduced audio signal in each prescribed operation cycle are provided. A ratio of the total sum of sampling time length of a first period, when sampling and reject are alternately repeated, to the total sum of time length of a second period, when the reproduced audio signal is rejected, and reject time length of the first period is set in response to the function of the reproducing speed. Thus, the reject time in the operation cycle is effectively distributed, and more recorded contents are reproduced.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention generally relates to an audio signal reproducing device, and more particularly to an audio signal reproducing device that reproduces an audio signal recorded on a magnetic tape at a reproduction speed that exceeds the recording speed. Regarding.

[Background technology] For example, in a conventional video tape recorder (referred to as a VTR), when an audio signal recorded on a magnetic tape is played back at a faster speed than when it was recorded, the frequency and content of the played audio signal are The progress speed increases in proportion to the playback speed. Therefore, the pitch of the reproduced sound becomes high, making it difficult to hear.

In order to solve this problem, VTRs employing pitch compensation circuits based on variable speech control (hereinafter referred to as VSC) have been developed, for example, "Quick Video's VS
Paper entitled "C Circuit" (Sharp Technical Report, 1986)
No. 36). In the VSC method, sampling and rejection are repeated alternately for each basic unit of the reproduced audio waveform, and the pitch is lowered by extending the sampled audio waveform temporally by the length of the rejection time. This makes it easier for the listener to understand.

[Problem to be solved by the invention] Therefore, in a VTR using the conventional VSC method,
Although it is possible to return the pitch of the reproduced audio to the pitch at the time of recording, there is a problem that the reproduced content, for example, the speed of speech, is proportional to the reproduction speed, making it difficult to hear the reproduced content.

In addition, in order to avoid this, the applicant has separately proposed that instead of losing the recorded content by increasing the length of the rejection time, the speed of the reproduced speech will also be the same as that at the time of recording. There is.

That is, in this proposal, after the reproduced audio signal is continuously sampled (sampling period), it is continuously rejected (rejection period). However, in order to understand the reproduced content, it is not necessary to sample and reproduce all the audio data of the reproduced audio signal during the sampling period. In other words, in this proposal, sampling is performed more than necessary during the sampling period, and therefore the number of reproduced audio signals that are rejected increases accordingly.

This invention was made to solve the above-mentioned problems, and in an audio signal reproducing device that reproduces at a reproduction speed that exceeds the recording speed, by effectively distributing the rejection time, recorded contents can be improved. The aim is to play it a lot.

[Means for Solving the Problems] An audio signal reproducing device according to the present invention includes a reproducing means for reproducing an audio signal recorded on a magnetic tape at a reproducing speed exceeding the recording speed, and a reproducing means for reproducing an audio signal recorded on a magnetic tape at a reproducing speed exceeding the recording speed; and sampling means for sampling and rejecting the recorded audio signal. A given operating cycle consists of a first cycle in which sampling and rejection of the reproduced audio signal are repeated alternately.
and a second period during which the reproduced audio signal is discarded. This audio signal reproducing device further includes ratio control means for controlling the ratio between the sampling time length of the first period and the rejection time length, and an expansion means for expanding the audio signal sampled by the sampling means over a predetermined operation cycle. including.

The time length of the second period is determined by the ratio of the time length plus the sum of the rejection time lengths of the first period to the sum of the sampling time lengths of the first period. Set in response to a function.

[Operation] The audio signal reproducing device according to the present invention is provided with a ratio control means, and by controlling the ratio between the sampling time length of the first period and the rejection time length, the rejection time in the operation cycle is effectively distributed. be able to. As a result, the second period during which the reproduced audio signal is continuously rejected is reduced by the sum of the dispersed rejection time lengths.

Therefore, more recorded content is reproduced.

[Embodiment of the Invention] FIG. 2 is a block diagram of an audio signal reproducing device provided in a VTR, showing an embodiment of the invention. Referring to FIG. 2, this audio signal reproducing device includes a magnetic tape 101
a reproducing head 10 for reproducing signals recorded on the
2, and an amplifier 10 for amplifying the reproduced audio signal.
3, a low-pass filter (LPF) 21 for removing harmonic components from the amplified audio signal, an A/D converter 22 for quantizing the audio signal, and storing the quantized digital audio signal. a processing section 24 that performs fade-in/fade-out processing of the digital audio signal output from the memory section 23; and a D/A converter 25 that performs D/A conversion of the processed digital audio signal. It includes a low-pass filter 26 that smoothes the D/A converted audio signal, and a memory control unit 200 that controls the memory unit 23. The memory control unit 200 includes a continuous write control unit 27 that supplies control signals for reading and writing to the memory unit 23, and generates a signal S4 that controls reading and writing in response to the value of a variable resistor 29. and a clock generator 20 that supplies a clock signal φ1 to the control section 27.

In operation, audio signals are recorded on the magnetic tape at a predetermined recording speed. A reproduced audio signal is obtained via the head 102 by running the magnetic tape 101 at a reproduction speed exceeding the recording speed. The reproduced audio signal is amplified by an amplifier 103 and then applied to a low-pass filter 21. The audio signal S20 band-limited by the low-pass filter 21 is quantized by the A/D converter 22, and then partially thinned out and written to the memory section 23. That is, this writing is performed by the memory control unit 20.
This is done under the control of 0 with partial rejection of the audio data. In the case of n-times speed reproduction, data written from the memory section 23 is continuously read out at a frequency of 1/n of the sampling frequency of the A/D converter 22.

The read audio data is subjected to fade-in fade-out processing in the processing section 24, and the processed data is
/A converter 25. The analog-converted signal is smoothed by a low-pass filter 26 and becomes an audio signal S3.
0 is obtained.

FIG. 1 is a circuit diagram showing an example of the memory control section 200 shown in FIG. 2. As shown in FIG. As mentioned above, this memory control section is
It includes a read/write controller 27 and a control waveform generator 28 .

The control waveform generator 28 includes an oscillator 31 that generates a sawtooth signal.
, a duty ratio determining variable resistor 29 and an oscillator 31
a comparator 32 that compares signals from the comparator 32; an integrator 33 that integrates the output signal of the comparator 32;
, and an AND gate 39 connected to receive the output signal S1 of the comparator 32 and the output signal S3 of the comparator 34.

The read/write control unit 27 includes an AND gate 40 connected to receive an output signal S4 from an AND gate 39 and a clock signal φ1 from a clock generator;
A write counter (WCNT) 35 driven by the output signal S5 of the ND gate 40, and a frequency divider 38 that divides the clock signal φ1 into a read clock signal φ2 by 1/n.
, a read counter (RCNT) 36 driven by the clock signal φ2, and a signal S5. Answer and counter 3
A multiplexer (M
UX) 37. The memory section 23 is supplied with an address signal AD from the multiplexer 37 and operates in response to a signal S5 as a write control signal and a signal φ2 as a read control signal. The carry signal terminal of read counter 36 is connected to the reset input of integrator 33 and write counter 35.

FIG. 3 is a timing diagram for explaining the operation of the memory control section shown in FIG. 1. The operation will now be described with reference to FIGS. 1 and 3. In the following explanation, a case of double speed playback (n-2) will be explained.

The oscillator 31 provides a sawtooth signal having a peak value Vcc to the comparator 32. The variable resistor 29 is set to O to V in advance.
A voltage set within the range of c c /2 is applied to the comparator 32 . Therefore, the comparator 32
A rectangular wave signal S1 as shown in the figure is output. The duty ratio of the signal S1 is 50% due to the setting of the variable resistor 29.
It can be set within a range of 100% to 100%. Integrator 33
outputs an integrated signal S2 in response to signal S1.

Comparator 34 compares signal S2 and reference voltage VB, and provides signal S3 to three AND gates.

Therefore, the signal S3 is at a high level until the signal S2 and the reference voltage VB become equal, and then changes to a low level. AND gate 39 provides AND gate 40 with signal S4 indicating the AND of signals S1 and S3.

AND gate 40 receives clock signal φ1 and signal S4.
A signal S5 indicating the logical product of is output. Write counter 35
is driven by this signal S5.

On the other hand, the read counter 36 is set to 1/n by the frequency divider 38.
It is driven by the frequency-divided clock signal φ2. The output signals of counters 35 and 36 are applied to multiplexer 37, and multiplexer 37 selectively outputs the applied signals in response to signal S5. The carry signal of the counter 36 is sent to the integrators 33 and 35 as a reset signal RS.
given to. Therefore, when the counter value by the read counter 36 completes one cycle, the integrators 33 and 35 are reset.

Signal S5 includes a pulse for driving counter 35 only when signal S4 is at a high level, as shown in FIG. The output signal of the counter 35 is sent to the multiplexer 3
7 to the memory unit 23 as the write address signal AD, the write address signal AD is increased in the memory unit 23 only while the signal S4 is at a high level, and the audio data is stored. . In other words, the signal S
Sampling of audio data is performed when signal S4 is at a high level, and rejection is performed when signal S4 is at a low level.

The read counter 36 supplies a read address signal AD that continuously increases in response to the clock signal φ2 to the memory section 23 via the multiplexer 37. Since the switching control of the multiplexer 37 is performed in response to the signal S5,
As shown in FIG. 3, the correspondence between the write address by the signal S5 and the read address by the signal φ2 is as shown by the dotted line. That is, in the memory section 23, there is a period T1 in which writing and successive output of audio data are performed in a time-division manner and a period T2 in which only reading is performed. In the period T1, as can be understood from the level change of the signal S4, there are short rejection times dispersed, and in the period T2, only the audio data is rejected.

When the read counter 36 completes one round of count values, it outputs a carry signal R3, so the integrator 33 and the write counter 35 are reset, and the same operation as described above is repeated again. The data signal delivered to the memory section 23 is the signal φ
2, the written audio data is read out at the cycle of the clock signal φ1, that is, at a cycle twice the write cycle.

FIG. 4 shows that the variable resistor 29 shown in FIG.
Signals S2 and S when changing the duty ratio of 1
FIG. (a) or C
) indicate cases where the duty ratio DR is set to 50.75% and 100%, respectively.

In the case of FIG. 4(a), since the duty ratio DR is 50%, the voltage reference voltage VB of the output signal S2 is reached immediately before the integrator 33 is reset. Therefore, in the operation cycle Tf, the comparator 34 shown in FIG. 1 always outputs a high level signal S3. Therefore, the AND gate 39 outputs a signal S4 having the same waveform as the signal S1.
is applied to the AND gate 40. Therefore, in this case, the period T2 as shown in FIG. 3 does not exist, and the short rejection times are distributed over the entire period of the operating cycle Tf. As a result, 50% of the audio data is discarded in such a short period that almost the same waveform is repeated, and although there is no missing part of the playback content (speech), the progress speed is twice as fast as when it was recorded. Become. That is, in this case, the conventional V
The same results as with the SC method can be obtained.

In the case of FIG. 4(b), the duty ratio DR of the signal S1 is
is 75%, the voltage level of signal S2 reaches voltage Va at time t1 earlier than in case (a). Therefore, in this case, periods T1 and T2 exist, and in period T1, sampling for a longer time and rejection for a shorter time than in the case (a) are repeatedly performed. Since the time length of period T2 is longer than in case (a), the continuously rejected audio data, that is, the rejected playback content (for example, speech content) is reduced. In this case, the voltage of the signal S2 reaches Va at time t1 when the total high level time of the signal S1 becomes Tf/2. Therefore, time t1 is TfX2/3 from the beginning of each operation cycle (Tfx2/3xO,75-
Tf/2).

Therefore, only 1/3 of the content of the speech is lost, but the speech speed is slower than in case (a), that is, about 1/2 of the recording speed.
．． Since the signal is multiplied by 3 times (-110.75 times), it becomes easier to hear.

In case (C), the duty ratio DR of the signal S4 is 10
It is set to 0%. Therefore, the signal S2 reaches VB at the time Tf/2 (time t2) from the beginning of each operation cycle. Therefore, even in this case, periods T1 and T2 exist, and audio data is continuously rejected during period T2 having a time length of Tf/2. During the period T1, periodic short periods of time are not discarded, so the speed of the reproduced story completely returns to that at the time of recording, but half of the reproduced content is periodically dropped.

In this manner, even if the duty ratio of the signal S1 changes, it is integrated by the integrator 33, so that the sum of the high-level and low-level time lengths of the signal S4 in the operation cycle Tf is kept constant. As a result, a certain amount of audio data can be written into the memory section 23 at any duty ratio DR.

In this way, in the case of double speed reproduction, the variable resistor 29 adjusts the duty ratio DR of the signal S1 from 5Q% to 100%.
% can be set continuously, and accordingly the speed of the playback content that is easy to hear and the amount of missing playback content depending on the speed can be selected. In any case, D/
Since A conversion is performed at one half of the sampling frequency of A/D conversion, it is possible to restore the pitch to the one at the time of recording and to reproduce it, regardless of the speed of the reproduction content (speech speed).

In the above explanation, the case of double-speed playback was taken as an example, but generally, even in n-times speed playback, the frequency division ratio of the frequency divider 38 shown in FIG. 1 is set to 1/n, and D/A conversion is performed. This is achieved by setting the sampling frequency of 1/n at the time of A/D conversion and further selecting an appropriate value for VB. In the case of n times speed playback, the duty ratio DR of the signal S1
may be set within the range of 100/n% to 100% using two variable resistors.

FIG. 5 is a circuit diagram showing another example of the memory control section 200 shown in FIG. 2. In this example, an SR flip-flop 61 is used instead of the integrator 33. Referring to FIG. 5, the SR flip-flop 61 is connected such that its set input S receives a carry signal S6 of the read counter 36, and its reset input R receives a carry signal S7 of the write counter 35. connected to. Further, the output Q of the SR flip-flop 61 is connected to one input of the AND gate 39. The other circuit configurations are the same as the circuit shown in FIG. 1, so explanations will be omitted.

FIG. 6 is a timing diagram for explaining the operation of the memory control section shown in FIG. 5. Next, the operation will be explained with reference to FIGS. 5 and 6.

The SR flip-flop 61 outputs a high level signal S3 in response to the carry signal S6 of the read counter 36,
In response to the carry signal S7 of the write counter 35, a low level signal S3 is output.

During the operation cycle Tf, the read clock signal φ
2 and the number of pulses of the signal S5 must be equal, so in this circuit, when the same number of pulses of the signal S5 as the number of pulses of the signal φ2 is given to the write counter 35, the pulses of the signal S5 are supplied. will be stopped. Since the bit lengths of counters 35 and 36 are equal, the number of input pulses required for each to output a carry signal once is equal. Therefore, when the carry signal S7 of the counter 35 is output, the flip-flop 61 is reset and provides a low level signal S3 to the AND gate 39.

Therefore, since the AND gate 39 outputs the low level signal S4, the supply of pulses by the signal S5 to the write counter 35 is stopped. When the read counter 36 outputs the carry signal S6, the flip-flop 61 is set and the high level signal S3 is output, so that the supply of pulses to the write counter 35 by the signal S5 is started.

If the counters 35 and 36 start counting from the count value 0 in the initial state, the count value of each counter 35 and 36 will be 0 when the carry signal S6 is output from the counter 36.

In the circuit shown in FIG. 1, since the integrator 33 is used, the time required for the signal S2 to rise may vary due to variations in circuit elements, but in the circuit shown in FIG. Therefore, the number of pulses of the signals φ2 and S5 can be exactly matched.

In the circuit shown in Fig. 5, n times speed playback (n
is not limited to an integer), the frequency divider 38
The frequency dividing ratio of 1/n may be changed, and the ratio of the sampling frequencies of A/D conversion and D/A conversion may be set to n21.

FIG. 7 is a waveform diagram showing the relationship between the output signal S30 obtained by the audio signal reproducing apparatus shown in FIG. 2, and the recorded audio signal SIO and the signal S20 obtained by double speed reproduction. As shown in FIG. 7, the reproduced audio signal S
20 are continuously discarded during period T2, and the remaining audio signal S20 is expanded within one operating cycle Tf. Although this figure corresponds to the case (c) shown in FIG. 4, the same waveform relationship can be obtained in the case (b) only by changing the time length of the rejection period T2. Incidentally, at the connection portion of each operation cycle, audio signal connection processing is performed by the fade-in fade-out processing section 24 shown in FIG.

[Effects of the Invention] As described above, according to the present invention, there is a first period in which sampling and rejection of the reproduced audio signal are alternately repeated in a predetermined operation cycle, and a second period in which the reproduced audio signal is rejected. 2 periods are provided, and the playback speed is the ratio of the time length of the second period plus the sum of the rejection time lengths of the first period and the sum of the sampling time lengths of the first period. Since the setting was made in response to the function of , an audio signal reproducing device capable of reproducing more recorded contents was obtained.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a circuit diagram showing an example of the memory control section shown in FIG. 2. FIG. 2 shows an embodiment of the present invention, V
FIG. 2 is a block diagram of an audio signal reproducing device provided in the TR. FIG. 3 is a timing diagram for explaining the operation of the memory control section shown in FIG. 1. FIG. 4 is a timing diagram of each signal when the duty ratio of signal S4 shown in FIG. 1 is changed. FIG. 5 is a circuit diagram showing another example of the memory control section shown in FIG. 2. FIG. 6 is a timing diagram for explaining the operation of the memory control section shown in FIG. 5. FIG. 7 is a waveform diagram showing the relationship between the output signal obtained by the audio signal reproducing apparatus shown in FIG. 2, the recorded audio signal, and the signal obtained by double speed reproduction. In the figure, 22 is an A/D converter, 23 is a memory section, 2
4 is a fade-in fade-out processing section, 25 is an A/D
Converter, 33 is an integrator, 61 is an SR flip-flop,
200 is a memory control unit.

Claims (1)

[Claims] An audio signal reproducing device that reproduces an audio signal recorded on a magnetic tape at a predetermined recording speed, the audio signal reproducing device reproducing the audio signal recorded on the magnetic tape at a reproduction speed that exceeds the recording speed. a reproducing means for reproducing the reproduced audio signal; and a sampling means for sampling and discarding the reproduced audio signal every predetermined operation cycle; and in the predetermined operation cycle, sampling and discarding the reproduced audio signal are alternately repeated. comprising a first period and a second period in which the reproduced audio signal is rejected; comprising ratio control means for controlling a ratio between the sampling time length of the first period and the rejection time length; The time length of the period is the ratio of the time length plus the sum of the rejection time lengths of the first period to the time length of the sum of the sampling time lengths of the first period. an audio signal reproducing device, the audio signal reproducing device comprising: a decompressing means set in response to a function of the reproducing speed and decompressing the audio signal sampled by the sampling means over the predetermined operation cycle;