JPH05160827A - Frame synchronization system - Google Patents

Abstract

PURPOSE:To prevent a cycle slip by preventing mis-operation of detection of a preamble bit change point by establishing frame synchronization with a clock whose phase is controlled after a preamble bit string is normally detected. CONSTITUTION:Reception signals 101 are configured of the same bit structure and have preamble, frame and data bits and a change point detection section 2 detects a change point of the signal from a preamble bit of the signal 101. A control section 3 controls an output clock of the control section 3 among n-sets of polyphase clocks generated in a detection timing of the detection section 2 so as to allow the output clock to take an optimum phase with respect to the phase of the signal 101. The detection section 1 detects a preamble bit string from the signal 101 inputted via an AND circuit 8. The output 103 opens an AND circuit 9 and a control section 4 controls a clock phase when the preamble bit string is normally detected. A frame counter 6 and a frame detection section 5 use an output 108 of the control section 4 to establish frame synchronization with respect to the signal 101.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frame synchronization circuit for an apparatus which handles burst signals having preamble information and frame information.

[0002]

2. Description of the Related Art As shown in FIG. 2, a conventional frame synchronization circuit for processing a burst signal includes a change point detecting section 21 for detecting a change point of data from a preamble bit included in a received signal 201 which is a burst signal. , Received signal 20
An oscillator 22 having an oscillation frequency (nf ₀ ) that is n times as large as 1; a clock phase control unit 23 that controls the f ₀ clock 202 to an optimum phase with respect to the received signal 201 by an output 206 of the change point detection unit 21; The output f of the unit 23
Frame counter 25 operated by ₀ clock 202
And a frame detection section 24 for detecting a frame from the received signal 201, the change point detection section 21 detects a change point of the data signal from the preamble bit, and the clock phase control section 23 is an output at this detection timing. The phase of the f ₀ clock 202 is controlled to the optimum phase with respect to the received signal 201, the frame detection unit 24 and the frame counter 25 establish frame synchronization of the received signal 201 by the f ₀ clock 202, and the frame counter 25 receives the frame pulse. When the frame pulse 203 and the frame position detected from the received signal 201 do not match, the frame detection unit 24 controls the frame counter 25 by the output 205.

[0003]

In such a conventional example, a digital timing extraction method is used and an optimum phase is selected from n multi-phase clocks in the preamble information. However, if the preamble information change point detection unit malfunctions due to noise or the like, there is a drawback in that a cycle slip occurs due to deviation from the optimum phase and frame synchronization is lost.

The present invention eliminates such drawbacks, and an object of the present invention is to provide a frame synchronization circuit having means for preventing the preamble bit from becoming a phase deviated from the optimum phase due to noise or the like.

[0005]

According to the present invention, there is provided a change point detecting section for detecting a change point of a received signal based on a preamble bit included in the received signal to generate a change point detection signal, and the change point detecting section. A clock phase control unit that generates a clock having an optimum phase for a received signal in accordance with the change point detection signal generated in step 1, and a frame counter that operates according to the clock having the optimum phase generated by the clock phase control unit. In a frame synchronization circuit that includes a frame detection unit that operates according to the clock of the optimum phase generated by the clock phase control unit and detects a frame from the reception signal, A preamble bit detector that detects a preamble bit string shorter than the preamble bit included in the signal, and this preamble bit Generated by the change point detection unit and a logical product circuit that permits the passage of the change point detection signal generated by the change point detection unit when the output unit detects the preamble bit string to the clock phase control unit. And a clock phase control unit for generating a clock having an optimum phase with respect to the received signal according to the change point detection signal and giving the clock to the preamble bit detection unit.

[0006] Here, a logical sum circuit which is provided with a signal which is generated at the frame detection section and becomes low level when frame synchronization is established and a signal which opens a high level window in the vicinity of the preamble bit of the received signal, and the logical sum circuit. It is desirable to provide a new logical product circuit for controlling passage of the reception signal given to the preamble bit detection unit by the output signal of the sum circuit.

[0007]

[Operation] When the change point detection unit detects a change in the received signal,
The clock phase control unit generates a clock with the optimum phase for the received signal at this detection timing, and the frame detection unit and the frame counter establish synchronization of the received signal with this clock. When it detects that the bit string is normal,
The new clock phase control unit controls the clock phase at the detection timing of the change point detection unit. As a result, it is possible to remedy the failure to generate the clock of the optimum phase due to the malfunction of the change point detection unit.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing the configuration of this embodiment. In this embodiment, a change point detection unit 2 for detecting a change portion of a preamble bit from a received signal 101 and an oscillator 7 having an oscillation frequency (nf ₀ ) n times that of the received signal 101.
When a clock phase control section 3 for outputting the f ₀ clock optimum phase for the received signal 101 at the timing of the signal 105, the clock phase of output f ₀ clock optimum phase with respect to the received signal 101 at the timing of the signal 109 Control section 4, preamble bit detection section 1 for detecting a preamble signal from received signal 101, and clock phase control section 4
The frame counter 6 which operates by the output clock 108, the frame detector 5, the logical product circuit 8, the logical product circuit 9, and the logical sum circuit 10.

That is, in this embodiment, as shown in FIG. 1, a change point detecting section for detecting a change point of the received signal 101 based on a preamble bit included in the received signal 101 and generating a change point detection signal 105. 2, a clock phase control unit 4 that generates a clock with an optimum phase for the received signal 101 according to the change point detection signal 105 generated by the change point detection unit 2, and a clock phase control unit 4 generated by this clock phase control unit 4. A frame counter 6 that operates according to the clock of the optimum phase and a frame detection unit 5 that operates according to the clock of the optimum phase generated by the clock phase control unit 4 to detect a frame from the received signal 101 are provided. As a feature of the present invention, a received clock 101 is used to generate a preamble shorter than a preamble bit included in the signal using a given clock. A preamble bit detection unit 1 for detecting a Nburubitto column, change point detection unit 2 when the preamble bit detection unit 1 detects the preamble bit sequence
AND circuit 9 which permits the passage of the change point detection signal 105 generated by
And the change point detection signal 105 generated by the change point detection unit 2
A clock phase controller 3 for generating a clock having an optimum phase for the received signal 101 and giving it to the preamble bit detector 1, and a signal 111 generated by the frame detector 5 which becomes a low level when frame synchronization is established. A logical sum circuit 10 to which a signal 110 for opening a high level window in the vicinity of the preamble bit of the received signal 101 is given, and the received signal 101 given to the preamble bit detector 1 by the output signal 104 of the logical sum circuit 10 passes. And a new AND circuit 8 for controlling

Next, the operation of this embodiment will be described. Figure 3
An example of the received signal 101 is shown in FIG. The received signals 101 all have the same bit configuration, and a preamble bit consisting of m bits at the beginning is followed by a frame bit and a data bit. The change point detection unit 2 detects the change point of the signal from the preamble bit of the received signal 101. The clock phase control unit 3 sets the output clock of the clock phase control unit 3 among the n multi-phase clocks generated by the oscillator 7 at the detection timing of the change point detection unit 2 to be the optimum phase for the received signal 101. Control. Preamble detection unit 1
Detects a preamble bit string from the received signal 101 input via the AND circuit 8. The length of the preamble bit string detected here is shorter than the number m of preamble bits in the received signal 101. When the preamble bit is detected, the output 103 outputs a high level to open the AND circuit 9. The clock phase control unit 4 controls the clock phase at the detection timing of the change point detection unit 2 when the preamble bit string is normally detected.
The frame counter 6 and the frame detection unit 5 operate by the output clock 108 of the clock phase control unit 4, and establish frame synchronization with the received signal 101.

When the frame synchronization is established, the output 111 of the frame detector 5 becomes low level. The frame counter 6 outputs a signal 110 for opening a high level window near the preamble bit of the received signal 101. With the OR circuit 10 and the AND circuit 8, the preamble detector 1 detects the preamble bit string for the bits near the preamble bit array position of the received signal 101 when the frame synchronization is established, and when the frame synchronization is lost, the preamble bit string is detected. The preamble bit string is detected over the bits.

[0012]

As described above, according to the present invention, the preamble bit sequence is established by the clock whose clock phase is controlled after the preamble bit sequence is normally detected by including the preamble bit detection unit. It is possible to prevent malfunction of change point detection of
This has the effect of suppressing the occurrence of unnecessary cycle slips.

Further, when the frame synchronization is established, a window is opened at the insertion position of the preamble bit to detect the preamble bit string, so that the clock phase control due to the erroneous recognition of the preamble bit string can be prevented.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

FIG. 2 is a block configuration diagram showing a configuration of a conventional example.

FIG. 3 is a diagram showing a configuration of a received signal included in FIGS. 1 and 2.

[Explanation of symbols]

 1 Preamble Bit Detection Unit 2, 21 Change Point Detection Unit 3, 4, 23 Clock Phase Control Unit 5, 24 Frame Detection Unit 6, 25 Frame Counter 7, 22 Oscillator 8, 9 AND Circuit 10 Logical Disjunction Circuit 10

Claims (2)

[Claims] 1. A change point detection unit that detects a change point of the received signal based on a preamble bit included in the received signal to generate a change point detection signal, and a change point detection signal generated by the change point detection unit. A clock phase control unit that generates a clock with an optimum phase for the received signal according to the above, a frame counter that operates according to the clock with the optimum phase generated by the clock phase control unit, and a clock phase control unit that generates the clock In a frame synchronization circuit equipped with a frame detection unit that operates according to the clock of the optimum phase and detects a frame from the received signal, using a given clock, the received signal is shorter than the preamble bit included in this signal. The preamble bit detection unit that detects the preamble bit string and the preamble bit detection unit AND circuit that allows the passage of the change point detection signal generated by the change point detection unit when the shift sequence is detected to the clock phase control unit, and the change generated by the change point detection unit. A frame synchronization circuit comprising: a clock phase control unit that generates a clock having an optimum phase with respect to a received signal according to a point detection signal and applies the clock to a preamble bit detection unit. 2. A logical sum circuit, which is provided with a signal which is generated at the frame detection section and becomes low level when frame synchronization is established, and a signal which opens a high level window in the vicinity of a preamble bit of a received signal, and the logical sum circuit. A new logical product circuit for controlling passage of a reception signal given to the preamble bit detector by an output signal of the circuit.
The frame synchronization circuit described.