JP2878012B2 - Frame synchronization circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frame synchronization circuit, and more particularly to a frame synchronization circuit for processing a burst signal having a preamble bit and a frame bit.

[0002]

2. Description of the Related Art FIG. 5 is a block diagram showing an example of a conventional frame synchronization circuit for detecting synchronization from a burst signal. In FIG. 5, a change point detection unit 21 detects a change point of a data signal from a preamble bit included in a received signal 25 which is a burst signal, and generates a change point detection pulse 28. The oscillator 22 generates a clock signal 26 having an oscillation frequency that is n times the received signal. In response to the clock signal 26 from the oscillator and the change point detection pulse 28 from the change point detection unit 21, the clock phase control unit 23 outputs an output clock signal 27 controlled to the optimum phase for the reception burst signal 25. The frame detector 24 detects a frame from the received signal 25 with the output clock signal 27 of the clock phase controller 23.

[0003]

In the conventional frame synchronization circuit, the optimum phase is selected by the n multi-phase clock signals in the preamble bit. For this reason, when the change point detection unit of the preamble information malfunctions due to noise or the like, there is a disadvantage that the phase deviates from the optimum phase.

Therefore, a technical problem of the present invention is to establish frame synchronization with a clock controlled to an optimum phase when a preamble bit sequence is normally detected, and thus to detect a change point of a preamble bit due to noise or the like. An object of the present invention is to provide a frame synchronization circuit capable of preventing a malfunction.

[0005]

In order to solve the above-mentioned problems, a frame synchronization circuit according to the present invention reads a reception signal having a preamble bit having a predetermined specific portion, detects a transition point, and detects a transition point detection signal. , An oscillator for generating a clock signal having an oscillation frequency n times the frequency of the received signal, and controlling the phase of the clock signal based on the clock signal and the change point detection signal. A clock phase control unit that outputs a phase-controlled output clock signal; and a frame detection unit that detects a frame of the received signal based on the output clock signal. Detect a specific part of the received signal,
A specific pattern detection unit that outputs a specific pattern detection signal indicating that the specific part has been detected, and a logic unit that outputs a coincidence pulse with the change point detection signal and the specific pattern detection signal to the clock phase control unit. Wherein said specific part comprises a pulse constituting said preamble bit.
Is characterized in that the duty ratio is 50%.

Further, in the frame synchronization circuit according to the present invention, the clock phase control unit includes a first clock phase control unit that outputs a preliminary phase clock signal based on an output from the logic unit, and the preliminary phase clock signal. And a second clock phase control which is controlled by the preamble bit detector and outputs the output clock signal to the frame detector. And a part.

Further, in the frame synchronization circuit according to the present invention, the change point detector reads the received signal at the timing of the clock signal.

[0008]

In the frame synchronization circuit according to the present invention, the change point detecting section reads the received signal at the timing of the clock signal from the oscillator, detects a change point in the received signal, and outputs a change point detection signal. The specific pattern detection unit detects a specific portion of the preamble bit of the received signal based on the clock signal from the oscillator, and outputs a specific pattern detection signal indicating that the specific portion has been detected. The logic means outputs a coincidence pulse with the change point detection signal and the specific pattern detection signal to the clock phase control unit.
The clock phase control unit includes: a first clock phase control unit;
It has a preamble bit detection unit and a second clock phase control unit. The first clock phase controller outputs a preliminary phase clock signal based on an output from the logic means. A preamble bit detector reads the received signal and detects a preamble bit based on the preliminary phase clock signal. The second clock phase control unit includes:
The output clock signal is controlled by the preamble bit detector and is output to a frame detector.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. In FIG. 1, the frame synchronization circuit according to the embodiment of the present invention includes a change point detection unit 1, an oscillator 2, a clock phase control unit 17, and a frame detection unit 8. The illustrated transition point detection unit 1 detects a transition point of a preamble bit of a received signal 9 which is a burst signal and generates a transition point detection pulse 11 as in the conventional example of FIG. Also, the oscillator 2 generates a clock signal 10 n times the oscillation frequency nf _o of the received signal 9 (f _o indicates a transmission speed).

The frame synchronization circuit of FIG. 1 differs from that of FIG. 5 in that it has a specific pattern detection circuit 3 and a NAND circuit 4 which is a logic means. The specific pattern detection circuit 3 generates a specific pattern detection pulse 12 when detecting a portion having a duty ratio of 50% in the preamble bits of the reception signal 9. The specific pattern detection pulse 12 is subjected to a NAND operation together with the change point detection pulse 11 by the NAND circuit 4, and the operation result is a coincidence pulse 13
Is output to the clock phase control unit 17.

The clock phase controller 17 shown in FIG.
Comprises a first clock phase control unit 5, a preamble bit detection unit 6, and a second clock phase control unit 7,
The first clock phase controller 5 reads the clock signal 10 having the frequency nf _o loaded by the coincidence pulse 13. The preamble bit detector 6 detects a preamble bit (for example, 101010101010101010) of the received signal 9 at the timing of the preliminary phase clock signal 14 output from the first clock phase controller 5, and outputs a preamble bit detection pulse 15. I do. The second clock phase control unit 7 outputs the preamble bit detection pulse 1
5, the output f _o which is the optimum phase for the received signal 9
Outputs a clock signal. The frame detection circuit 8 detects the frame in again read a received signal received signal 9 at the output f _o clock signal.

Next, the operation of the frame synchronization circuit shown in FIG. 1 will be described with reference to FIGS. FIG. 2 shows a burst signal. As shown, the burst signal is
They all have the same bit configuration, with a preamble bit 31 of m bits at the beginning, followed by a frame bit 32 and a data bit 33.

FIG. 3 shows a signal input to the change point detecting section. As shown in FIG. 3, the change point detector 1 detects a change point in the preamble bit from the received signal 9. FIG. 4 shows signals input to the specific pattern detection circuit 3.

As shown in FIG. 4, the specific pattern detection circuit 3 detects a portion where the duty ratio of the pulse of the preamble bit of the received signal is 50% based on the clock signal from the oscillator 2. The first clock phase controller 5 controls the phase of the clock signal at the timing when the outputs from the two detectors match. The preamble bit detector 6 detects m preamble bits from the received signal 9 based on the output of the first clock phase controller 5. When all the conditions of the three detection units, that is, the change point detection unit 1, the specific pattern detection unit 3, and the preamble bit detection unit 6, are satisfied, the second clock phase control unit 7 operates to output an output clock signal having an optimum phase. You. The frame detection unit 8 reads the received signal and detects the frame based on the output clock signal having the optimum phase.

[0016]

As described above, according to the present invention, by providing the preamble bit detector and the specific pattern detector, the output clock signal controlled to the optimum phase when the preamble bit sequence is normally detected is provided. Establish frame synchronization. Therefore, it is possible to provide a frame synchronization circuit that can prevent a malfunction in detecting a change point of a preamble bit due to noise or the like.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of the present invention.

FIG. 2 is a diagram illustrating an example of a burst signal.

FIG. 3 is a diagram illustrating an example of change point detection.

FIG. 4 is a diagram showing an example of specific pattern detection.

FIG. 5 is a configuration diagram of a conventional technique.

[Explanation of symbols]

 1, 21 change point detection unit 2, 22 oscillator 3 specific pattern detection unit 4 NAND circuit 5 first clock phase control unit 6 preamble bit detection unit 7 second clock phase control unit 8, 24 frame detection unit 9, 25 Received signal 10, 26 Clock signal 11, 28 Change point detection pulse 12 Pattern detection pulse 13 Match pulse 14 Preliminary phase clock signal 16, 27 Output clock signal 15 Preamble bit detection pulse 17, 23 Clock phase controller 31 Preamble bit ( m bits) 32 frame bits 33 data

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H04L 7/10 G06F 1/12

Claims (3)

(57) [Claims] 1. A change point detection section for reading a reception signal having a preamble bit having a predetermined specific portion, detecting a change point and outputting a change point detection signal, and an oscillation frequency n times the frequency of the reception signal An oscillator for generating a clock signal having: a clock phase control unit for controlling a phase of the clock signal based on the clock signal and the transition point detection signal to output a phase-controlled output clock signal; And a frame detecting circuit for detecting a frame of the received signal by detecting a specific portion of the received signal based on the clock signal and generating a specific pattern detection signal indicating that the specific portion has been detected. A specific pattern detection unit to be output, and a coincidence pulse between the change point detection signal and the specific pattern detection signal And a logic means for outputting to the clock phase control section, wherein the specific portion is a portion where a duty ratio of a pulse constituting the preamble bit is 50%. 2. The frame synchronization circuit according to claim 1, wherein
Thus, the clock phase control unit outputs from the logic means.
A first clock for outputting a preliminary phase clock signal based on the
A lock phase controller, based on the preliminary phase clock signal;
Read the received signal, and
A preamble bit detector for detecting the
The output clock signal is controlled by a pull bit detector.
Clock phase for outputting a signal to the frame detector
And a control unit.
Road. 3. The frame according to claim 1 or 2,
In the clock synchronization circuit, the change point detection unit
Read the received signal according to the timing of the clock signal
A frame synchronization circuit characterized in that: