JPH0744507B2 - Jitter absorption circuit - Google Patents

Description

The present invention relates to a frame synchronization circuit, and more particularly to a jitter absorption circuit used in the frame synchronization circuit.

[Prior Art] A jitter absorption circuit includes a line data signal in which one frame has a frame synchronization signal and data, a line clock signal,
An external frame signal, absorbs the jitter of the line data signal and outputs a jitter-free line data signal based on the external frame signal, and absorbs the jitter of the line clock signal to eliminate the jitter It outputs a signal.

Referring to FIG. 2, the conventional jitter absorbing circuit receives the line data signal a. The circuit data signals, as shown in FIG. 3 includes a frame synchronization signal F and the data D ₁ to D _n to 1 frame. This jitter absorbing circuit extracts the frame synchronization signal in the line data signal a by the line synchronization detection circuit 11 by the line data signal a and the line clock signal b supplied from the outside, and extracts the extracted frame synchronization signal. The line frame signal c is prepared and is input to the jitter absorption memory 2 together with the line data signal a and the line clock signal b. Further, the voltage controlled crystal oscillator (VCXO) 3 creates an internal clock signal d in which jitter is absorbed from the line clock signal b. The intermediate frame generation circuit 5 receives the line frame signal c, the external frame signal f supplied from the outside, and the internal clock signal d, and outputs the intermediate frame signal h that is not close to the line frame signal c or the external frame signal f. create. The jitter absorption memory 2 responds to the intermediate frame signal h, outputs the intermediate line data signal i, and supplies it to the frame correction memory 6. Then, the frame correction memory 6 outputs the line data signal e without jitter based on the external frame signal f.

Here, the reason why the intermediate frame signal h, the jitter absorption memory 2 and the frame correction memory 6 are necessary will be described.

The line frame signal c and the external frame signal f are not always close to each other. If, as shown in Figure 4,
When the line frame signal c and the external frame signal f are not close to each other, if there is either one of the jitter absorption memory 2 or the frame correction memory 6, the line data signal of the previous frame is set as the line data signal e. The line data signal e synchronized with the external frame signal f can be obtained without erroneously outputting, absorbing the jitter.

However, as shown in FIG. 5, when the line frame signal c and the external frame signal f are close to each other, the line frame signal c
May come immediately before or after the external frame signal f, so if either the jitter absorption memory 2 or the frame correction memory 6 is used, the line data signal of the previous frame is used as the line data signal e. There is a possibility to output it by mistake.

Therefore, as shown in FIG. 6, the intermediate frame signal h which is neither close to the line frame signal c nor the external frame signal f
Even if the line frame signal c and the external frame signal f are close to each other, the line data signal of the previous frame is not output as the line data signal e.

FIG. 7 shows the circuit of the intermediate frame forming circuit 5, and FIG. 8 shows its operation time chart. First, the intermediate frame creating counter 11 operates by the internal clock signal d, and outputs the counter value to the intermediate frame creating ROM 12. Then, the intermediate frame creating ROM 12 creates the counter clear signal n and the intermediate frame signal h. At this time, the counter clear signal n is output for several bits before the output of the intermediate frame signal h. When the line frame signal c or the external frame signal f is output during that time, the intermediate frame creating counter 11 is cleared, and the intermediate frame creating ROM 12 outputs the counter clear signal n as the intermediate frame signal h to a new location. Like When the counter clear signal n is output, the line frame signal c
Alternatively, when the external frame signal f is not output, the intermediate frame creating counter 11 is not cleared, and the counter clear signal n and the intermediate frame signal h are output at each predetermined cycle of one frame.

[Problems to be Solved by the Invention] As described above, the conventional jitter absorption circuit always requires two memories, the jitter absorption memory 2 and the frame correction memory 6, in order to perform a normal operation. Has the drawback of being complicated.

An object of the present invention is to provide a jitter absorption circuit having a simple structure.

[Means for Solving the Problems] According to the present invention, in response to a line data signal supplied from the outside and containing a frame synchronization signal and data in each frame, and a line clock signal supplied from the outside. ，
A line synchronization detection circuit that detects the frame synchronization signal and outputs the detected frame synchronization signal as a line frame signal, and responds to the line clock signal, absorbs the jitter of the line clock signal, and outputs a jitter absorption clock signal A voltage-controlled oscillator, the line data signal, the line clock signal, and the line frame signal. The frame synchronization included in each frame of the line data signal, having a jitter absorption memory that responds to the jitter absorption clock signal, absorbs the jitter of the line data signal, and outputs the jitter absorption data signal. In a jitter absorption circuit that outputs the jitter absorption data signal based on an external frame signal supplied from the outside at a cycle equal to the signal repetition cycle together with the jitter absorption clock signal as a circuit output signal, the line synchronization detection circuit Responsive to the line data signal and the line clock signal, detects every other frame synchronization signal and outputs the detected every other frame synchronization signal as the line frame signal. The memory has a memory capacity for storing two frames of the line data signal, and reads When the dress clear signal is received, the read address is returned to the initial value, and the jitter absorbing circuit further responds to the line frame signal and the external frame signal in response to the read address of the jitter absorbing memory. A jitter absorbing circuit is provided which has a frame position determining means for determining the position of the line frame signal which should be returned to the initial value and outputting the read address clear signal at that position.

[Embodiment] Next, an embodiment of the present invention will be described with reference to the drawings.

Referring to FIG. 1, a jitter absorption circuit according to an embodiment of the present invention includes a line synchronization detection circuit 1 for generating a line frame signal c from a line data signal a and a line clock signal b supplied from the outside, and a line clock. VCX03 that receives the signal b and creates an internal clock signal d without jitter, a frame position determination circuit that creates the read address clear signal g by the line frame signal c, the external frame signal f supplied from the outside, and the internal clock signal d 4, a line data signal a, a line clock signal b, a line frame signal c, an internal clock signal d, and a memory clear control signal g, and a jitter absorption memory 2 for creating a line data signal e without jitter. . The line synchronization detection circuit 1 at this time is
Instead of outputting the line frame signal c for every frame, the line data signal a for two frames is stored in the jitter absorbing memory 2 by outputting once every two frames.

FIG. 9 shows the line synchronization detection circuit 1. First, the line data signal a is directly input to the synchronization detection ROM 9 and
The line data signal, which is also input to the frame memory 8 and delayed by one frame, is input to the synchronization detection ROM 9. Then, the synchronization detection ROM 9 outputs the synchronization detection signal m of the previous frame to the synchronization detection latch 10 in response to the input of the frame bit position signal 1 from the synchronization detection counter 7, and when the synchronization detection is performed twice consecutively. The line frame signal c is output to (see the frame synchronization circuit of Japanese Patent Publication No. 59-4903 for details).

FIG. 10 shows the circuit of the frame position determination circuit 4, and FIG. 11 shows its operation time chart. First, the frame position determination counter 13 operates according to the internal clock signal d, and outputs the counter value to the frame position determination ROM 14. Then, the frame position determination ROM 14 creates a line frame interpolation control signal o, an external frame interpolation control signal p, and a memory clear signal g. At this time, if the line frame signal c is input while the line frame interpolation control signal o is being output, the frame position determination counter 13 is cleared,
The read address clear signal g is output to the frame position determination ROM 14, and the line frame interpolation control signal o is output before and after the location where the next external frame signal f is output. Then, the line frame interpolation control signal o
Even if the line frame signal c is not input while is output, the read address clear signal g is output to the frame position determination ROM 14, but before and after the location where the next external frame signal f is output, The output of the external frame interpolation control signal p is stopped so that the line frame interpolation control signal o and the read address clear signal g are not output, and the frame position determination counter 13 is not affected.

When the data bit k of the line data signal a is 192 bits and the frame bit j is 1 bit, the line data signal a is composed of 193 bits. A memory capacity of 386 bits or more is required.

[Effects of the Invention] As described above, the jitter absorption circuit according to the present invention can be operated only by the jitter absorption memory 2 without using the frame auxiliary memory, so that the configuration is simplified and therefore the failure rate is reduced. Is effective.

[Brief description of drawings]

FIG. 1 is a block diagram of a jitter absorption circuit according to an embodiment of the present invention, FIG. 2 is a block diagram of a conventional jitter absorption circuit,
FIG. 3 is a diagram for explaining the format of the line data signal a in the jitter absorbing circuits of FIGS. 1 and 2, and FIG. 4 is a diagram when the line frame signal c and the external frame signal f are not close to each other. 2 is a time chart for explaining the operation of the jitter absorbing circuit in FIG. 2, and FIG. 5 is a diagram for explaining the operation of the jitter absorbing circuit in FIG. 2 when the line frame signal c and the external frame signal f are close to each other. Time chart, Fig. 6 shows line frame signal c and external frame signal f
2 is a time chart for explaining the operation of the jitter absorbing circuit of FIG. 2 when the intermediate frame signal h is generated, and FIG. 7 is a block diagram of the intermediate frame creating circuit 5 of the jitter absorbing circuit of FIG. , FIG. 8 is a time chart for explaining the operation of the intermediate frame creating circuit 5 of FIG. 7, FIG. 9 is a block diagram of the synchronization detecting circuit 1 of the jitter absorbing circuit of FIG. 1, and FIG. FIG. 11 is a block diagram of the frame position determination circuit 4 of the jitter absorption circuit shown in FIG. 11, and FIG. 11 is a time chart for explaining the operation of the frame position determination circuit 4 of FIG. 1 …… Line synchronization detection circuit, 2 …… Jitter absorption memory, 3 ……
VCX0,4 …… Frame position determination circuit, 5 …… Intermediate frame creation circuit, 6 …… Frame correction memory, 7 …… Synchronous detection counter, 8 …… Frame memory, 9 …… Synchronous detection ROM, 10 ……
Latch for sync detection, 11 ... Counter for creating intermediate frame,
12 …… Intermediate frame creation ROM, 13 …… Frame position determination counter, 14 …… Frame position determination ROM, a …… Line data signal, b …… Line clock signal, c …… Line frame signal, d… … Internal clock signal, e …… Line data signal, f ……
External frame signal, g …… Read address clear signal, h ……
Intermediate frame signal, i ... Intermediate data signal, 1 ... Frame bit position signal, m ... Pre-sync detection signal, n ... Counter clear signal, o ... Line frame interpolation control signal, p ... External frame interpolation control signal.

Claims (1)

[Claims] 1. A line data signal which is supplied from the outside and includes a frame synchronization signal and data in each frame,
A line synchronization detection circuit that detects the frame synchronization signal in response to a line clock signal supplied from the outside and outputs the detected frame synchronization signal as a line frame signal, and the line clock signal that responds to the line clock signal. A voltage controlled oscillator that absorbs jitter of a signal and outputs a jitter absorption clock signal, the line data signal, the line clock signal, and the line frame signal. The frame synchronization included in each frame of the line data signal, having a jitter absorption memory that responds to the jitter absorption clock signal, absorbs the jitter of the line data signal, and outputs the jitter absorption data signal. A jitter absorption circuit that outputs the jitter absorption data signal based on an external frame signal supplied from the outside at a cycle equal to the signal repetition cycle together with the jitter absorption clock signal as a circuit output signal, wherein the line synchronization detection circuit comprises: Responsive to the line data signal and the line clock signal to set the frame synchronization signal to 1
Every other frame is detected, and the detected every other frame synchronization signal is output as the line frame signal, wherein the jitter absorption memory has a memory capacity for storing two frames of the line data signal, and When the read address clear signal is received, the read address is returned to the initial value, and the jitter absorbing circuit further responds to the line frame signal and the external frame signal, A jitter absorbing circuit having a frame position deciding means for deciding a position of the line frame signal for returning the read address to an initial value and outputting the read address clear signal at the position.