JPH0210978B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an interface circuit, for example, an interface circuit that exchanges data between a microcomputer and an asynchronous external device.

FIG. 1 is a block diagram of an interface circuit which is the background of the present invention, and FIG. 2 is a waveform diagram of each part of FIG. 1.

Next, the structure and operation of a conventional interface circuit will be explained with reference to FIGS. 1 and 2. The coincidence detection circuit 1 is supplied with a data type signal 7 and a selection signal 9 from the control circuit 5 from the outside. The data type signal 7 represents the type of data 6 input to the register 3, and the selection signal 9 output from the control circuit 5 is for selecting the data to be applied to the register 6. A coincidence detection circuit 1 detects a coincidence between a data type signal 7 and a selection signal 9, and if they match, a coincidence detection signal 11 is output.
is given to AND gate 2. This AND gate 2 receives a data strobe signal 8 and a control circuit 5 from the outside.
A gate signal 10 is applied from . This gate signal 10 is derived after the selection signal 9 is output. The AND gate 2 performs a logical product of the data strobe signal 8, the coincidence detection signal 11, and the gate signal 10, and provides the output signal 12 to the register 3. The register 3 stores data 6 at the timing when the AND signal 12 is input. Data 6 stored in register 3 is given to register 4. Register 4 stores data 6 based on a signal given from control circuit 5. Note that the register 4 and the control circuit 5 are built in, for example, a microcomputer.

As mentioned above, in the conventional interface circuit, the gate signal 10 output from the control circuit 5 and the data strobe signal 8 input from the outside are asynchronous, so the data strobe signal 8 and the gate signal 10 are not synchronized in the AND gate 2. In some cases, the timing cannot be obtained, and a signal with a very narrow pulse width, such as the AND signal 12' shown in FIG. 2, may be output. As a result, the register 3 sometimes fails to properly store data based on the AND signal 12'.

Therefore, the main object of the present invention is to provide an interface circuit which can eliminate the above-mentioned drawbacks and which can operate stably.

To summarize the invention, a gate signal is output after a selection signal is output from the control means, and a match detection circuit detects a match between a data type signal inputted from the outside and a selection signal outputted from the control means.
Further, the date signal outputted from the control means is stored in synchronization with the strobe signal inputted from the outside, and data is stored in the register based on this signal, the coincidence detection signal, and the strobe signal. It is configured to synchronize signals input from the outside with the interface circuit.

The above objects and other objects and features of the present invention will become more apparent from the detailed description given below with reference to the drawings.

FIG. 3 is a block diagram of one embodiment of the present invention. This FIG. 3 is the same as FIG. 1 except for the following points. That is, in order to synchronize the data strobe signal 8 and the gate signal 10, a flip-flop 13 is provided as state storage means. When the flip-flop 13 receives the gate signal 10 from the control circuit 5, it stores the gate signal 10 at the falling edge of the data strobe signal 8. Then, AND the synchronization gate signal 14
Give to gate 2.

FIG. 4 is a waveform diagram of each part of FIG. 3. next,
The specific operation of one embodiment of the present invention will be described with reference to FIGS. 3 and 4. The coincidence detection circuit 1 generates a coincidence detection signal 11 when the data type signal 7 and the selection signal 9 match in the same way as shown in FIG.
and is given to AND gate 2. After outputting the selection signal 9, the control circuit 10 applies a gate signal 10 to the flip-flop 13. The flip-flop 13 stores the gate signal 10 at the falling edge of the data strobe signal 8, and stores the synchronous gate signal 14.
is given to AND gate 2. The AND gate 2 takes the AND of the data strobe signal 8, the coincidence detection signal 11, and the synchronization gate signal 14, and outputs the AND signal 12.
is given to register 3. The register 3 stores timing data 6 into which the AND signal 12 is input.

In this way, by synchronizing the gate signal 10 with the data strobe signal 8, even if the gate signal 10 falls during the period of the data strobe signal 8, the synchronized gate signal 14 will remain until the next falling edge of the data strobe signal 8. Since the AND signal 12 is held, the AND signal 12 will have the same pulse width as the data strobe signal 8. Therefore, the AND signal 12 does not output the AND signal 12 with a narrow pulse width because the data strobe signal 8 and the gate signal 10 are not synchronized as in the conventional case. Therefore, register 3 definitely contains data 6.
is memorized.

As described above, according to the present invention, since the gate signal is synchronized with the strobe signal and used as a signal for storing data in the register, data can be reliably stored in the register.

[Brief explanation of drawings]

FIG. 1 is a schematic block diagram of an interface circuit which forms the background of this invention. FIG. 2 is a waveform diagram of each part of FIG. 1. FIG. 3 is a block diagram of one embodiment of the present invention. FIG. 4 is a waveform diagram of each part of FIG. 3. In the figure, 1 is a coincidence detection circuit, 2 is an AND gate, 3 is a register, 5 is a control circuit, and 13 is a flip-flop.

Claims (1)

[Scope of Claims] 1. An interface circuit that receives data, a strobe signal, and a data type signal representing the type of data, and stores the data in a register if the data is desired data, comprising: a control means for outputting a selection signal for selecting data to be selected and a gate signal after outputting the selection signal; detecting coincidence between the data type signal and the selection signal and outputting a coincidence detection signal; a coincidence detection means, a state storage means for storing the gate signal in synchronization with the strobe signal, and a gate for storing the data in the register based on the coincidence detection signal, the output of the state storage means, and the strobe signal. An interface circuit with means.