JPH05151296A - Logic inspecting device for circuit with memory and its method - Google Patents

Abstract

PURPOSE:To accurately inspect logic for a circuit including a memory by com paring input data to memories with addresses when memories exist in respective circuits described at respectively different levels and evaluating the equivalency of the circuits. CONSTITUTION:In the case of inspecting the circuit logic equivalency of two memory-included circuits described by respectively different description methods, a level-A circuit dividing means 3 divides a circuit 1 designed and described at a level A and outputs level-A divided circuit information 5 and level-A I/O terminal information 6. A level B circuit dividing means 4 similarly outputs level-B divided circuit information 7 and level-B I/O terminal information 8. The information 5, 7 are respectively simulated by a level-A simulation means 10 and a level-B simulation means 11 based upon a test pattern 9. Finally the I/O terminals of the levels A, B are allowed to correspond to each other based upon the information 6, 8 and the contents of a signal name corresponding rule file 14 and the simulation results 12, 13 of the same signal are mutually compared by a result comparing means 15 to find out a compared result file 16.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a logic verification method,
In particular, the present invention relates to an apparatus and method for verifying logic equivalence of a circuit including a memory.

[0002]

2. Description of the Related Art In a conventional logic verification method, outputs of a register and a memory of different two-level circuits are cut independently to generate an output signal and an input signal, and a simulation result of each output signal is compared.

[0003]

In the conventional logic verification method described above, in the verification of the circuit in which the memory exists, the output of the memory, that is, the state value read from the memory is compared.

Therefore, depending on the description method of two different circuits, due to the influence of the relationship between the data input to the memory and the address signal, racing (when two or more signals change at the same time, some element of the faster operation) Comes out first,
The output may be temporarily wrong) and the correct status value cannot be written to the specified address.
It could not be read, and a pseudo error was detected. The circuit in which the memory exists could not be accurately verified.

Therefore, the present invention is applicable to verifying the equivalence of a circuit including memories described at two different levels.
Prevents false errors due to memory input data and address signal racing caused by differences in circuit description.
To provide a logic verification device for a circuit with a memory that enables accurate logic verification of the circuit.

A first solving means of the present invention for solving the above-mentioned problems is a circuit logic of a circuit with a first memory and a circuit with a second memory described by different description methods. In a verification device of a logic circuit with a memory for verifying equivalence, a data signal, an address signal, and a control signal which are inputs to the memories of the first and second logic circuits with a memory are cut off independently and externally. Output signal to
A circuit dividing means for dividing the data signal read out from the memory and independently dividing the data signal as an input signal from the outside, and dividing the first and second circuits with memory into a new circuit by the circuit dividing means. Simulation means for simulating the first memory-equipped circuit and the second memory-equipped circuit by a signal test pattern and outputting each simulation result, and the first and second memory-equipped circuits created by the circuit dividing means. Correspondences of the output signals of the circuits are correlated by the signal name correspondence rule, and the first and second simulation results of the output signals of the circuit obtained by the simulation means are compared with each other to extract the difference between the simulation results. And a result comparing means.

A second solving means of the present invention for solving the above problem verifies the circuit logic equivalence between the first circuit with memory and the second circuit with memory described by different description methods. In the method of verifying a logic circuit with memory, the data signal, the address signal, and the control signal, which are the inputs to the memories of the first and second logic circuits with memory, are disconnected and independently output as output signals to the outside, A circuit dividing step of dividing the data signal read out from the memory independently as an input signal from the outside to divide the first and second circuits with memory, and a new circuit by dividing by the circuit dividing step. A simulation step of simulating the first circuit with memory and the second circuit with memory with a signal test pattern and outputting each simulation result; Correspondence between the output signals of the first and second circuits with a memory created in the dividing step is associated by a signal name correspondence rule, and the first and second output signals of the circuit obtained by the simulation step are associated. A result comparing step of comparing the simulation results with each other to extract a difference between the simulation results.

A third solving means of the present invention for solving the above-mentioned problem is to provide a method for verifying a logic circuit with a memory according to the second solving means, an external storage device, an output device, a display device,
It is characterized in that it is executed by an information processing device including an input device and a central processing unit.

[0008]

Embodiments of the present invention will now be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention. The case where logic verification is performed on a circuit described at level A and a circuit described at level B will be described.
The level A circuit dividing unit 3 divides the circuit information 1 designed and described in the level A into circuits, and outputs the level A circuit information 5 and the level A input terminal information 6 after the division. Similarly, the level B circuit dividing means 4
The circuit information 2 described in 1 is divided into circuits, and the divided circuit information 7 of level B after division and the input / output terminal information 8 of level B are respectively output. Then, the level A divided circuit information 5 after the division is simulated by the level A simulation means 10 using the test pattern 9 to obtain a level A simulation result 12. Similarly, the divided circuit information 7 of the level B after the division is simulated by the simulation means of the level B and the simulation result 13
To get Finally, from the input / output terminal information 6 and 8 of the levels A and B and the signal name correspondence rule file 14, the input / output terminals of the levels A and B are made to correspond, and the simulation results 12 and 13 of the same signal are made by the result comparison means 15. The result comparison file 16 is obtained by comparison, and the equivalence of the circuits of level A and level B is verified.

FIG. 2 shows the level A circuit dividing means 3 of the present invention.
7 is a processing flowchart of the circuit dividing means 4 of level B. FIG. In step 21, it is judged whether or not all the elements in the division target circuit have been processed. If not, in step 22, it is judged whether or not the target element is a register. When the target element is a register, the output signal of the register is disconnected and independent in step 29, and the output of the register is set to the output terminal.

In step 210, the input terminal is set and connected to the signal of the output destination of the register. Separately, if the element determined in step 22 is not a register, it is determined in step 23 whether or not the element is a memory, and if it is a memory, the signal to be the input data of the memory is disconnected and independent in step 24. In step 25, the signal which becomes the address data of the memory is disconnected and set as the output terminal, and in step 26, the control signal of the memory is disconnected and set as the output terminal. In step 27, the output signal of the memory is cut off independently, and in step 28, the input terminal is set and connected to the output destination of the memory.

In step 211, the newly set input terminal and output terminal are output to the input / output terminal information file. When the processing is completed for all the elements, the circuit information divided in step 212 is output to a file.

Next, a specific example to which the present invention is applied will be described. FIG. 3 shows a circuit for logic verification. FIG. 3 (1) shows a circuit described at level A, and FIG. 3 (2) shows a circuit described at level B. FIG. 4 (1) is a circuit obtained by dividing the level A circuit, and FIG. 4 (2) is a level A set by circuit division.
Input / output terminal information of. 5 (1) shows a circuit obtained by dividing the level B circuit, and FIG. 5 (2) shows level B input / output terminal information set by the circuit division. FIG. 6 shows a signal name correspondence rule file.

First, FIG. 3 of the circuit information described in level A
Circuit division is performed for (1). Register DFF (Fig. 3
The output terminal is set by disconnecting (see the identification name 30 of (1)) independently to obtain the signal name DFF_O (see the identification name 40 of FIG. 4A). Also, set the input terminal, signal name DFF
(See the identification name 41 in FIG. 4 (1)). Next memory D
Regarding the MEM (see the identification name 31 in FIG. 3A), the input data signal DATA is disconnected and connected to the output terminal, and the address signal ADR is also disconnected and connected to the output terminal. Then, although the control signal C is also disconnected, the control signal C
Is an input signal, the output signal C_O is inserted, the signal C is input to C_O, and C_O is an output terminal (see FIG. 4 (1)).
(See the identification name 42 of the above). In addition, by setting the input terminal and setting the signal name to the original memory signal name DMEM (Fig. 4 (1)
43). Further, the input / output terminal information shown in FIG. 4 (2) newly set by circuit division is output.

Circuit information described in level B FIG. 3 (2)
Similarly, the circuit division is performed. The output signal DFF + 00 of the register R1 is disconnected and set independently to set the output terminal, and the signal name is set to DFF_O + 00 (see FIG. 5 (1)). Also, set the input terminal, register R1 before disconnection
The output element G4 is connected to the output element G4 and the signal name is DFF + 00. Next, the signal DATA + which is the input data of the memory M1
00 is disconnected and connected to the newly set output terminal. Address signal ADR (0) +00, ADR (1) +
00 is also disconnected and connected to the newly set output terminals. The control signal C + 00 of the memory M1 is also disconnected and output independently to the output terminal. At this time, C +
Since 00 is an input signal, an AND logic element G5 is inserted and connected to the input signal of G5, and the output of G5 is C_O + 00.
To the output terminal. Further, the output signal of the memory M1 is disconnected, the newly set input terminal is connected to the logic element G4 which is the output destination of the memory M1, and the signal name is DMEM + 00.
And Then, the input / output terminal information shown in FIG. 5B newly set by the circuit division is output.

Circuit information of level A after circuit division FIG.
Circuit information of (1) and level B In FIG. 5 (1), the same test pattern is set to the input terminal, simulation is performed, and the simulation result of the output terminal of each circuit is obtained.

Signal Correspondence Rule FIG. 6 shows level A and level B.
The signal correspondence rule between and is described. In the signal name of level B, the character string from the first character to the code "+" including the subscript information indicates the rule that the signal name of level A matches. ing.

This signal correspondence rule file FIG. 6 and level A
Input / output terminal information for level and level B Figure 4 (2) and Figure 5 (2)
From DFF_O and DFF_O + 00, DATA and DA
TA + 00, ADR (0) and ADR (0) +00, AD
R (1) and ADR (1) +00, C_O and C_O + 00
It can be known from the result comparison file 16 that and correspond to each other, and the equivalence by the circuit operation can be verified.

[0019]

As described above, according to the present invention, when a memory exists in a circuit, the output of the memory is not compared but the input data of the memory is compared with the address to verify the equivalence of the circuit. To do. Therefore, it is possible to accurately perform the logic verification of the circuit including the memory without paying attention to the memory data and address racing generated by the difference in the circuit description.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a flowchart showing a circuit division process of the present invention.

FIG. 3 is circuit description information showing an application example of the present invention.

FIG. 4 is a diagram showing circuit description information after circuit division described in level A.

FIG. 5 is a diagram showing circuit description information after the circuit division described in level B.

FIG. 6 is a diagram showing a signal name correspondence rule file for level A and level B.

[Explanation of symbols]

 1 level A circuit information 2 level B circuit information 3 level A circuit dividing means 4 level B circuit dividing means 5 level A dividing circuit information 6 level A input / output terminal information 7 level B dividing circuit information 8 levels Input / output terminal information of B 9 Test pattern 10 Simulation means of level A 11 Simulation means of level B 12 Simulation result of level A 13 Simulation result of level B 14 Signal name correspondence rule file 15 Result comparison means 16 Result comparison file

Claims (3)

[Claims] 1. A verification device for a logic circuit with a memory, which verifies circuit logic equivalence between a circuit with a first memory and a circuit with a second memory, which are described by different description methods. Of the logic circuit with memory, the data signal, the address signal, and the control signal, which are input to each memory, are disconnected and made into output signals to the outside, and the data signals read from the memory are disconnected and input from the outside independently. As a signal, a circuit dividing unit that divides the first and second memory-equipped circuits, the first memory-equipped circuit and the second memory-equipped circuit that are divided into new circuits by the circuit dividing unit, Simulation means for simulating with a signal test pattern and outputting each simulation result, and outputs of the first and second memory-equipped circuits created by the circuit dividing means The result comparing means extracts the difference between the simulation results by comparing the first and second simulation results of the output signals of the circuit obtained by the simulation means with each other by corresponding the signal name correspondence rule. A logic verification device for a circuit with a memory, comprising: 2. A method for verifying a logic circuit with a memory, which verifies circuit logic equivalence between a circuit with a first memory and a circuit with a second memory, which are described by different description methods. Of the logic circuit with memory, the data signal, the address signal, and the control signal, which are input to each memory, are disconnected and made into output signals to the outside, and the data signals read from the memory are disconnected and input from the outside independently. As a signal, a circuit dividing step of dividing the first and second memory-equipped circuits, the first memory-equipped circuit and the second memory-equipped circuit that are divided into new circuits by the circuit division step, A simulation step of simulating with a signal test pattern and outputting each simulation result, and the first and second memories created in the circuit dividing step. Correspondence of the output signal of the circuit with the circuit is made to correspond from the signal name correspondence rule, the first and second simulation results of the output signal of the circuit obtained by the simulation step are compared with each other to determine the difference in the simulation result. A logic verification method for a circuit with a memory, comprising: a result comparing step of extracting. 3. The memory-equipped device according to claim 2, wherein the information processing device comprises an external storage device, an output device, a display device, an input device, and a central processing unit. Circuit logic verification method.