JPH04344571A - Logic verifying device - Google Patents

Abstract

PURPOSE:To shorten time taken for verifying logic by aiming at a logic signal whose value has not varied throughout the first simulation, selecting an input signal pattern capable of varying the value of the logic signal, and sending out this pattern to a simulation device. CONSTITUTION:A fixed signal detecting means 1 detects in a signal state value information 5 a fixed signal whose logic value has not varied during simulation, and outputs the fixed signal as fixed signal information 7. Next, a fixed correlated signal retrieval means 2 with the aid of fixed signal information 7 and circuit information 11 about logic circuit model sequentially retrieves signals correlated with the fixed signal at the input side, and prepares fixed correlated signal information 8 that is an input signal that affects the fixed signal. Next, an activating pattern generating means 3 with the aid of fixed signal information 7 and fixed correlated signal information 8 examines an input pattern the can vary the value of fixed signal information and outputs the input pattern to a simulation device 4. Further, the simulation device 4 uses information 8 and activated pattern 9 to carry out simulation again.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a logic verification device, and more particularly to a logic verification device used to verify design errors in a logic circuit after simulating a logic circuit model.

0002

[Background Art] Conventionally, in logic verification performed after simulating a logic circuit, a logic verification device verifies whether or not the logic circuit contains a design error based on information output from a simulation device. was. When a part of the logic circuit that may contain a design error is detected, the results are sent to the simulation device, and the simulation device re-inputs all possible patterns into that circuit part to simulate it. was going on.

0003

[Problems to be Solved by the Invention] In the conventional logic verification of the logic circuit described above, when a logic verification device detects a part that may contain a design error in the logic circuit, the result is simulated. In addition to sending the data to the simulation device, when simulating that part again, all possible input patterns must be set and sent to the simulation device as input signals for that part, and the simulation device must simulate that part again. However, it has the disadvantage that logic verification takes time.

[0004] An object of the present invention is to detect design errors without having to set all possible input patterns for the part of the logic circuit to be simulated again when a logic circuit is simulated again. An object of the present invention is to provide a logic verification device that can perform simulations that can be performed.

[0005]

[Means for Solving the Problems] The logic verification device of the present invention is provided with: (A) signal state value information indicating how the logic values of all signals of a logic circuit change as a result of simulation; fixed signal detection means for detecting a fixed signal, which is a signal whose logical value does not change during the simulation and maintains a fixed state, from among the signal state value information and outputting it as fixed signal information; (B) the fixed signal; From the fixed signal information created by the detection means and the circuit information of the logic circuit model, signals related to the fixed signal are sequentially searched on the input side, and fixed related signal information that is an input signal that affects the fixed signal is created. fixed related signal retrieval means, (C
) Fixed signal information created by the fixed signal detection means, circuit information of the logic circuit model, element function pattern information having the functions of all elements as a combination of input/output patterns, and created by the fixed related signal search means. and activation pattern generating means for examining and outputting an input pattern that can change the value of the fixed signal information based on the fixed related signal information.

[0006]

Embodiments Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the logic verification device of the present invention.

The logic verification device of this embodiment shown in FIG. 1 receives signal state value information 5 indicating how the logical values of all the signals of the logic circuit change as a result of simulation, and calculates the signal state values. The fixed signal detection means 1 detects a fixed signal, which is a signal whose logical value does not change during simulation and maintains a fixed state, from the information 5 and outputs it as fixed signal information 7. Signals related to the fixed signal are sequentially searched on the input side from the fixed signal information 7 and the circuit information 11 of the logic circuit model, and the fixed related signal information 8 which is the input signal that affects the fixed signal is searched.
fixed signal information 7 created by the fixed signal detection means 1, circuit information 11 of the logic circuit model, and element function pattern information having the functions of all elements as a combination of input and output patterns. 12 and the fixed related signal information 8 created by the fixed related signal search means 2, the activation pattern generating means 3 examines and outputs an input pattern that can change the value of the fixed signal information 7. ing.

Next, the operation will be explained.

[0010] FIG. 1 is a diagram showing an example of a logic circuit to be verified by the logic verification device of this embodiment. Figure 2(a) and Figure 2
The circuit diagrams shown in (b) are examples of logic circuits to be verified by the logic verification device of this embodiment.

In FIG. 2, a to f indicate elements, and A to H and P to S indicate signals connected between the elements.

Now, the operation of the logic verification device shown in FIG. 1 will be described when the logic circuit shown in FIG. 2 is simulated by the simulation device 4.

In FIG. 1, as a result of simulating the logic circuit shown in FIG. 2, signal state value information 5 is output from the simulation device 4 to the fixed signal detection means 1.

As shown in FIG. 3, the signal state value information 5 holds the state values taken by all the signals in the logic circuit for each input pattern. For example, "P(0, 0, 0, …
..., 0)" is the state value when the signal P sets the first pattern and performs the simulation, and the next "0" is the state value when the signal P sets the second pattern and performs the simulation. This is the state value when the input pattern is set in the simulation.In this way, when the simulation is performed using each input pattern set in the simulation, the state value corresponding to the input pattern is held.The same goes for other signals. It is.

Fixed signal detection means 1 detects signal state value information 5.
Based on this, fixed signal information 7 indicating the signal name and its state value whose state value, which is a simulation result, did not change throughout all the set patterns is created and output. That is, “P(0, 0, 0, ...,
0)”, it is recognized that the state value of signal P is only “0”, and “Q(1, 1, 0, ..., 0)”
Therefore, it is recognized that the state value of the signal Q is both "0" and "1". Furthermore, “R(1,1
, 1, ..., 1)", the state value for signal R is "
1”, and also recognizes that “S(0, 1, 0,
..., 1)", it is recognized that the state value of the signal S is both "0" and "1". Then, as the fixed signal information 7, "P(0)", "R (1
)” in this fixed signal information 7.
” indicates that the state value of signal P is fixed at “0”, and “R(1)” indicates that the state value of signal R is fixed at “1”.

The fixed related signal search means 2 searches for all signals and element connections in the circuit model of FIG. 2 for each of "P(0)" and "R(1)" in the fixed signal information 7. The input side is sequentially searched using the circuit information 11 shown in FIG.
)", the fixed related signal information 8 shown in FIG.

That is, "a-P, S-D, E" in FIG.
indicates that signal D and signal E are input to element a, and signal P and signal S are output, so from "a-P, S-D, E" in circuit information 11, signal P Signal D and signal E are obtained as input signals related to signal D, and based on signal D, input signal A and signal E are obtained as input signals related to signal D from "b-D-A, B" in circuit information 11. B is obtained. Further, the circuit information 11 is searched based on the signal E, and the input signal C is obtained as an input signal related to the signal E by "c-E-C" in the circuit information 11. In this way, input signals A, B, and C are obtained as input signals that influence signal P whose state value is fixed, and "P-A, B, C"
Fixed related signal information 8 is created and output.

Similarly, input signals F and G are obtained as input signals that affect signal R whose state value is fixed, and fixed related signal information 8 called "R-F, G" is created and output. be done.

Here, the element function pattern information 12 shown in FIG. 6 holds the functions of all elements as a combination of input and output patterns, and "a・01*00" in the element function pattern information 12 of FIG. , the output pattern of element a is “0”
, "1" indicates that the input pattern is "0", "0", and by referring to it in combination with the circuit information 11, the combination of the state values of the input signal and the output signal can be found.

The activation pattern generating means 3 generates circuit information 1
1. “P(0)” and “R(1)” in fixed signal information 7 based on element function pattern information and fixed related signal information 8
The state values of signals P and R indicated by “1” and “
0'' is sequentially searched for, and an activation pattern 9 to be set as the fixed signal information shown in FIG. 7 is created and output.

In other words, “P(0)” in the fixed signal information 7
”, and “a-P, S-D, E” in circuit information 11.
Therefore, it can be seen that the signal P, which is a fixed signal, is the output signal of the element a, and the related input signals are the signals D and E. Also, based on the fact that the state value of the signal P is fixed to "0", the element a whose state value of the signal P becomes "1" is
Search for input patterns. That is, from "a・10*11" in the element function pattern information 12, in order to set the state value of the signal P to "1", the state value "1" must be set for each of the signals D and E, which are the input signals of the element a. ”, “1” should be set.

Furthermore, the state values of the signals D and E are “
1", "1", what kind of combination of state values should be set for the related signals on the input side of the signals D, E is searched. In other words, "b--" in the circuit information 11. D-
A, B'', it can be obtained that the signal D is the output signal of the element b, and the related input signals are the signals A and B. Also, it can be obtained that the signal D is the output signal of the element b, and the related input signals are the signals A and B. The input pattern of b is "b・1" in the element function pattern information 12.
*11", it can be seen that the state values "1" and "1" should be set to the signals A and B, which are the input signals of the element b, respectively.

Furthermore, from "c-E-C" in the circuit information 11, it is found that the signal E is the output signal of the element c, and the related input signals are the signals C and B. The input pattern for element c that results in a state value of "1" is based on "c・1*10" in the element function pattern information 12.
It can be seen that it is sufficient to set the state value "0" to the signal C, which is the input signal of .

Here, “P-A” in the fixed related signal information 8
,B,C'', the signal that affects signal P is
Since it is found that the signals are A, B, and C, the search process for the input side is ended at this stage. In this way, the state value of the signal P whose state value is fixed at "0" is changed to "1".
”, the state values “1”, “1”, and “0” are assigned to the signals A, B, and C, which are input signals related to the signal P, respectively.
"(A, B, C) = (1, 1, 0
)" is created. Similarly, the state value of the signal R whose state value is fixed at "1" is created as "
0", "(F, G) = (G, 0)" indicates that the state values "0" and "0" are set to the signals F and G, which are input signals related to the signal R, respectively. ” is created.

[0025] Then, by using the activation pattern 9 and the fixed-related signal information 8, an activation pattern is set for the input signal that affects the fixed signal, and the signal from the input signal that affects the fixed signal to the fixed signal is set. Regarding the partial circuit,
A simulation is performed using the simulation device 4.

As a result, in the simulation device 4,
The state values of signals P and R, which were fixed signals, are saved,
Partial circuit signal state value information 10 is created. That is,
As a result of setting activation patterns for signals A, B, and C and performing a simulation, partial circuit signal state value information 10 called "P(1)" indicating that the state value of signal P is "1" was obtained. Created. Similarly, as a result of simulation with activation patterns set for signals F and G, partial circuit signal state value information called "R(1)" indicates that the state value of signal R is "1". 10 is created and output.

Finally, the fixed signal detection means 1 receives the partial circuit signal state value information 10 from the simulation device 4, refers to it, searches for signals whose state values are still fixed, and obtains completely fixed signal information 6. create. That is, from "P(1)" in the partial circuit signal state value information 10,
It turns out that the signal P whose state value was fixed at "0" was activated and took on the state value "1", and it turns out that the signal P is not a completely fixed signal. On the other hand, as for the signal R, it is found from "R(1)" that the signal 8 whose state value was fixed to "1" still remains "1", and the complete fixed signal information 6 is "R". (1)” is created and output. That is, even if the input pattern is set so that the signal R takes the state value "0", it does not become "0", which means that it has been verified that there is a design error.

In this way, by focusing on the logic signals whose values did not change through the first simulation, we select an input signal pattern that can change the value of the logic signals, and send this to the simulation device. By simulating that part again using a simulation device, design errors can be detected and the logic circuit can be corrected without having to set all possible input patterns for the part of the logic circuit that is the target of the re-simulation. can be verified.

[0029]

Effects of the Invention As explained above, the logic verification device of the present invention focuses on a logic signal whose value did not change through the initial simulation, and uses an input signal that can change the value of the logic signal. By selecting a pattern, sending it to the simulation device, and having the simulation device simulate that part again, all possible input patterns can be set for the part of the logic circuit that is to be simulated again. It has the effect that design errors can be detected even if there is no such thing.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of a logic verification device of the present invention.

FIG. 2 is a diagram showing an example of a logic circuit to be verified by the logic verification device of the embodiment.

[Fig. 3] Fixed signal detection means 1 of the logic verification device of this embodiment
FIG. 3 is a diagram showing signal state value information of the logic circuit shown in FIG. 2 that is input to the FIG.

FIG. 4 is a diagram showing circuit information of the logic circuit shown in FIG. 2 that is input to the fixed related signal detection means 2 of the logic verification device of the present embodiment.

5 is a diagram showing fixed related signal information of the logic circuit shown in FIG. 2 outputted from the fixed related signal detection means 2 of the logic verification device of the present embodiment.

6 is a diagram showing element function pattern information of the logic circuit shown in FIG. 2, which is input to the activation pattern generating means 3 of the logic verification device of this embodiment.

7 is a diagram showing the activation pattern of the logic circuit shown in FIG. 2 output from the activation pattern generating means 3 of the logic verification device of this embodiment.

[Explanation of symbols]

1 Fixed signal detection means 2 Fixed related signal search means 3 Activation pattern generation means 4 Simulation device 5 Signal status value information 6 Completely fixed signal information 7 Fixed signal information 8 Fixed related signal information 9 Activation pattern 10 Partial circuit signal status value information 11 Circuit information 12 Element function pattern information

Claims (1)

[Claims] (A) As a result of the simulation, signal state value information indicating how the logical values of all the signals of the logic circuit change is inputted, and from among the signal state value information, the signal state value information is selected during the simulation. fixed signal detection means for detecting a fixed signal, which is a signal whose logical value does not change and maintains a fixed state, and outputting it as fixed signal information; (B) fixed signal information and logic circuit created by the fixed signal detection means; (C) fixed-related signal search means for sequentially searching on an input side for signals related to the fixed signal from circuit information of the model and creating fixed-related signal information that is an input signal that affects the fixed signal; Fixed signal information created by the signal detection means, circuit information of the logic circuit model, element function pattern information having the functions of all elements as a combination of input/output patterns, and fixed signal information created by the fixed related signal search means. 1. A logic verification device comprising activation pattern generation means for examining and outputting an input pattern that can change the value of fixed signal information based on related signal information.