JPH10124543A - Simulation method for logic circuit and device therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To allow a worker to easily obtain the result of logical simulation by operating the logical simulation by applying test pattern data described in test cycle units, and outputting the logical simulation result described in the test cycle units. SOLUTION: Input test pattern data are inputted to a test data generating means 205, converted into a format specific to a logical simulator 206, and inputted to the logical simulator 206. The logical simulator 206 operates the logical simulation by inputting the input test pattern data to a logic circuit whose each input pin a delay circuit or a pulse generating circuit is connected with by a building-in means 204, and outputs the simulation result. Thus, the correspondence of the input test pattern data in each test cycle to the output result obtained by the logical simulation can be clearly indicated. Thus, a worker who executes the logical simulation can easily obtain the test result.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method and apparatus for simulating a logic circuit.

[0002]

2. Description of the Related Art When a logic simulation is performed on an LSI logic circuit for testing, input test pattern data expressed in test cycle units is temporarily converted into simulator input data expressed in waveform change time units, and then the logic test data is converted into logic input data. It is necessary to input the simulation and perform the simulation.

FIG. 9 (a) shows how the input test pattern data is represented. The test cycle is 1000 nsec, and the logic circuit under test has input pins I1 to I4. Each input pin I1 to I
For each of four, it is indicated which test mode of the test pattern data to be input is a delay waveform or a pulse waveform. Input pattern data is input to the input pin I1 for 100 ns.
The data generated with a delay of ec is given, and the input pin I3
Requires that the input test pattern data be delayed by 100 nsec to give data having a pulse width of 200 nsec.

FIG. 9 (b) shows test cycles 0, 1, 2,
The waveform mode input to each of the input pins I1 to I4 is shown for each of 3,. Here, “1” and “0” indicate a high level and a low level, respectively, and “P” indicates a pulse waveform.

On the other hand, as shown in FIG. 9 (c), the simulator input data input to the logic simulator has a waveform change time, 0, 1200 nsec, 1300 nsec,
Every 1700 nsec,..., It is necessary to indicate whether the waveform level input to each of the input pins I1 to I4 is logic “1” or “0”.

A process of converting input test pattern data expressed in units of test cycles into simulator input data expressed in units of waveform change time and inputting the data to a logic simulator to perform logic simulation is shown in FIG. Has been performed through the steps shown in FIG. First,
The input test pattern data 101 expressed in test cycle units as shown in FIG.
In FIG. 9, using a conversion tool or the like (not shown)
The waveform is developed into a pattern in which the level is displayed for each waveform change time as shown in FIG. This simulator input data 10
3 is input to the logic simulator 105 together with the circuit connection information data 104. The circuit connection information data 104 is
This is data indicating the connection relationship of each element in the logic circuit to be tested, and also includes information on each of the input pins I1, I2,.

A logic simulation is performed in the logic simulator 105, and a simulation result 106 is output for each waveform change time.

[0008]

However, the simulation result 106 is displayed as a result corresponding to the simulator input data 103. That is, it is expressed in the form of an output result with respect to the level input to each input pin at each waveform change time. Therefore, when the operator performing the simulation grasps the test results, the input test pattern data 101 described in test cycle units and the simulation result 106 described in waveform change time units are used.
There is a problem that it is not easy to correlate with the above, and it is difficult to verify test results.

The present invention has been made in view of the above circumstances, and has as its object to provide a logic circuit simulation method and apparatus which enable an operator to easily grasp the result of a logic simulation.

[0010]

A method of simulating a logic circuit according to the present invention uses a waveform mode determining means to determine whether the waveform mode of input test pattern data described in test cycle units is a delay waveform or a pulse waveform. Determining, and when it is determined that the waveform mode is a delayed waveform, the input test pattern data is given and delayed for a predetermined time, and simulator input data in which a signal level at each waveform change time is described. A step of generating a delay circuit as a timing generation circuit to be output by a delay circuit generating means; and, when the waveform mode is determined to be a pulse waveform, receiving the input test pattern data and having a predetermined pulse width. Timing generation to output simulator input data describing the signal level for each waveform change time Generating a pulse generating circuit as a path by a pulse generating circuit generating means, providing circuit connection information data of the logic circuit to the incorporation means, and inputting the input pin of the logic circuit indicated by the circuit connection information data to the delay circuit; Connecting the timing generation circuit generated by the generation means or the pulse generation circuit generation means; and connecting the test pattern described in test cycle units to a logic circuit in which the timing generation circuit is connected to an input pin by the incorporation means. By giving the data and converting the data into the simulator input data described for each waveform change time by the timing generation circuit to the logic circuit, a logic simulation was performed by the logic simulator, and the simulation was described in test cycle units. Outputting a logic simulation result; It is characterized by comprising.

The determination of the waveform mode is made for each data input to a plurality of input pins. When the waveform mode input to the input pin switches between a delay waveform and a pulse waveform, the waveform mode is determined. According to the switching timing, the method further includes the step of generating a delay circuit by the delay circuit generation means or generating a pulse generation circuit by the pulse generation circuit means.

Further, the method may further include a step of receiving the input test pattern data, converting the input test pattern data into input test pattern data conforming to the format of the logic simulator, and then providing the input test pattern data to the logic simulator. Generating corresponding data in which input test pattern data is associated with address information indicating a test cycle; and using the corresponding data, a logic with address information obtained by adding address information to a logic simulation result output by a logic simulator. The method may further include outputting a simulation result.

The logic simulation apparatus according to the present invention comprises: a waveform mode determining means for determining whether the waveform mode of input test pattern data described in test cycle units is a delay waveform or a pulse waveform; Delay circuit generation means for generating a delay circuit as a timing generation circuit which receives input test pattern data, delays by a predetermined time, and outputs signal input to the simulator describing a signal level at each waveform change time When the waveform mode is determined to be a pulse waveform, the input test pattern data is given and a simulator generating data describing a signal level at each waveform change time having a predetermined pulse width is output as a timing generation circuit. Pulse generating circuit generating means for generating a pulse generating circuit;
A circuit connection information data of a logic circuit, and an incorporation means for connecting an input pin of the logic circuit indicated in the circuit connection information data to a timing generation circuit generated by a delay circuit generation means or a pulse generation circuit generation means; The test pattern data described in test cycle units is given to a logic circuit in which the timing generation circuit is connected to the input pin by the incorporation means, and the simulator input data described for each waveform change time by the timing generation circuit is provided. A logic simulator is provided which performs the logic simulation by giving the converted result to a logic circuit and outputs a logic simulation result described in test cycle units.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to the drawings. FIG. 5 shows the configuration of the logic circuit simulation apparatus according to the present embodiment.

Input test pattern data as shown in FIG. 9A, which indicates the waveform mode to be input to each input pin for each test cycle, is input to the waveform mode determination means 201 (not shown). You. Waveform mode determination means 2
01, it is determined whether the waveform mode of data to be input for each input pin of the logic circuit is a delay waveform or a pulse waveform.

According to the judgment result of the waveform mode judgment means 201, the delay circuit generation means 202 generates a delay circuit as a timing generation circuit when the waveform mode is a delay waveform, and when the waveform mode is a pulse waveform, the pulse generation circuit generation means 2
03 generates a pulse waveform circuit as a timing generation circuit.

FIG. 2 shows a specific example of the delay circuit.
The delay waveform is a waveform whose level changes after a delay of a predetermined time from the start time of the test cycle. A plurality of delay elements 41 such as inverters are connected, input test pattern data is input to an input terminal, and data having a delay waveform delayed by a predetermined time is output. This is supplied to the input pin of the logic circuit indicated by the circuit connection information data described later.

FIG. 3 shows a specific example of the pulse generation circuit. The pulse waveform changes its level at a certain time in a test cycle, and then returns to the original level at a certain time in the same test cycle. This pulse generation circuit includes an oscillation circuit 5 for generating a basic clock.
1 and a counter 52. The input test pattern data is externally input to the counter 52, and the basic clock is input from the oscillation circuit 51 to the counter 52. The input pattern input to the pulse generation circuit has a delay time and a waveform width as shown in FIG. 9A, and a pulse that is turned on during the delay time in the counter 52 and turned off during the waveform width. A waveform is generated. This pulse waveform is input to the input pin of the logic circuit indicated by the circuit connection information data.

The circuit connection information data of the logic circuit is input to the incorporation means 204. For each input pin of the logic circuit indicated by the circuit connection information data, the corresponding delay circuit 202 or pulse generation circuit is connected as a timing generation circuit by the incorporation means 204. FIG. 4 shows that a delay circuit 40 or a pulse waveform circuit 5 is connected to each input pin I1, I2,.
0 indicates a state of being connected and incorporated.

The input test pattern data is input to the test data generation means 205, converted into a format unique to the logic simulator 206, and input to the logic simulator 206. The logic simulator 206 includes the embedding unit 20
In step 4, the input test pattern data is input to a logic circuit in which a delay circuit or a pulse generation circuit is connected to each input pin, a logic simulation is performed, and a simulation result is output. This simulation result is as shown in FIG. The test data input to each of the input pins I1 to I4 is shown in a waveform mode for each test cycle. The output data obtained by the logic simulation is displayed as the level “H” or “L” of the output pins O1 to O4 for each test cycle in a state associated with the input test pattern data.

As described above, the correspondence between the input test pattern data for each test cycle and the output results obtained by the logic simulation is clearly shown, so that the operator who has executed the logic simulation can easily grasp the test results. is there.

Further, even when the operator changes the input test pattern data, the input test pattern data to be input to the logic simulator 206 has a level indicated for each test cycle, similarly to the input test pattern data. Because there is, change and correction work is easy.

FIG. 1 is a flowchart showing the procedure of processing in the logic circuit simulation method according to the present embodiment. This simulation method may be executed using the device shown in FIG.

Input test pattern data 11 described in units of test cycles is input to the waveform mode determining means 201 shown in FIG. 5, and the waveform mode and timing information 12 for each input pin are read. Waveform mode determination means 20
According to 1, as step 13, it is determined whether the waveform mode is the delay waveform mode or the pulse waveform mode for each of the input pins I1 to I4 of the logic circuit.

If it is determined that the mode is the delay waveform mode, the delay circuit 40 having delay elements for the delay time is generated by the delay circuit generation means 302.

When it is determined that the waveform mode is the pulse waveform mode, the pulse generation circuit 50 including the oscillation circuit 51 and the counter 52 as shown in FIG. .

Further, depending on the input test pattern data, there is a type in which a delay waveform and a pulse waveform are switched halfway, such as data to be input to the input pin I3 shown in FIG. In such a case, the input pins I1 to I1
In addition to 4, a control pin S13 for performing waveform mode switching control is set. When the level of the control pin S13 changes from logic "0" to "1", FIG.
As shown in (2), the waveform mode of the data input to the input pin I3 changes.

Such switching control is realized by a configuration as shown in FIG. The control circuit 301 includes
Input test pattern data and a control signal are input. The control circuit 301 includes a delay circuit 40 and a pulse generation circuit 50.
Is input with an enable signal EN for activation to one of the counters 52 included in the counter 52, and the operation state is set.
As a result, the delay waveform and the pulse waveform are switched on the way and output.

Generation of a circuit combining such a delay circuit 40 and a pulse generation circuit 50 is performed in step 1 in FIG.
6 and the control signal 17
Is generated, and a signal in which the delay waveform and the pulse waveform are mixed is generated.

The delay circuit 40 thus generated,
Alternatively, the pulse generation circuit 50 or a circuit in which the delay circuit 40, the pulse generation circuit 50, and the control circuit 301 are combined corresponds to the timing generation circuit 18.

The circuit connection information data 19 is input to the incorporation means 204. In step 20, the corresponding timing generating circuit 18 is incorporated into each input pin of the logic circuit indicated by the circuit connection information data by the incorporating means 204.

The connection information data 21 of the logic circuit whose timing generation circuit 18 is connected to each input pin is input to the logic simulator 206.

On the other hand, the input test pattern data 11 is input to the test data generating means 205 and converted to conform to the format of the logic simulator 206. Thereby, the simulator input data 23 for each test cycle is generated and given to the logic simulator 206.

Further, a test pattern (not shown)
The address information 24 of the test cycle for the input test pattern data is input to the address corresponding data generating means. Thereby, as shown in FIG. 9B, the input test pattern data and the address information 0 of the test cycle,
Data 25 associated with 1, 2,... Is generated.

In the logic simulator 206, the connection information 21 of the logic circuit incorporating the timing generation circuit
And the simulator input data 23 in units of test cycles, and a logic simulation is executed as step 26.

When the logic simulation is completed, a simulation result 27 is output from the logic simulator 206. In step 28, pattern-address correspondence data 25 is added to the simulation result 27, and a logic simulation result with address information of a test cycle as shown in FIG. 6 is output. According to the simulation method and apparatus according to the present embodiment as described above, a logic simulation result can be obtained in units of test cycles as in the case of the input test pattern data, so that the two can be easily associated with each other, and The test results can be grasped appropriately.

The above-described embodiment is an example, and does not limit the present invention. For example, the configurations of the delay circuit and the pulse generation circuit are not limited to those shown in FIGS. 2 to 4, and a delay circuit capable of outputting a delay waveform obtained by delaying an input pattern by a predetermined time, or a pulse having a predetermined width and a predetermined time delay Various modifications are possible as long as the pulse generation circuit can output a pulse waveform having the following. In the procedure of the logic simulation process shown in FIG. 1, a simulation result with address information to which address information for a pattern is added is output as shown in FIG. If the result is described in units of test cycles, it is not necessary to add address information.

[0038]

As described above, according to the method and apparatus for simulating a logic circuit of the present invention, the test cycle is described in units of test cycles, similarly to the input test pattern data described in units of test cycles. Since the logic simulation result can be obtained, the comparison with the input test pattern data is clear, and the operator can easily grasp and verify the test result.

[Brief description of the drawings]

FIG. 1 is a flowchart showing a procedure of processing by a simulation method of a logic circuit according to an embodiment of the present invention.

FIG. 2 is a circuit diagram showing an example of a delay circuit used in the simulation method.

FIG. 3 is a circuit diagram showing an example of a pulse generation circuit used in the simulation method.

FIG. 4 is an explanatory diagram showing how a delay circuit or a pulse generation circuit is connected to a logic circuit in the simulation method.

FIG. 5 is a block diagram showing a configuration of a simulation device for a logic circuit according to one embodiment of the present invention.

FIG. 6 is an explanatory diagram showing a logic simulation result obtained by a logic circuit simulation method or device according to one embodiment of the present invention.

FIG. 7 is an explanatory diagram showing input test pattern data when switching between a delay waveform mode and a pulse waveform mode in the simulation method or apparatus.

FIG. 8 is a circuit diagram showing a configuration of a circuit used when switching between a delay waveform mode and a pulse waveform mode in the simulation method or apparatus.

FIG. 9 is an explanatory diagram showing input test data, input test pattern data, and simulator input data input to a logic simulator used in a conventional simulation method.

FIG. 10 is a flowchart showing a processing procedure in a conventional simulation method.

[Explanation of symbols]

Reference Signs List 11 Input test pattern data 18 Timing generation circuit 19 Circuit connection information data 21 Circuit connection information data with built-in timing generation circuit 23 Simulator input data 25 Pattern-address correspondence data 27 Simulation result 29 Simulation result with address information 40 Delay circuit 41 Delay element 50 Pulse generation circuit 51 Oscillation circuit 52 Counter 60 Logic circuit 201 Waveform mode determination means 202 Delay circuit generation means 203 Pulse generation circuit generation means 204 Incorporation means 205 Test data generation means 206 Logic simulator

Claims (8)

[Claims] 1. A method for simulating a logic circuit, comprising: determining, by a waveform mode determining means, whether a waveform mode of input test pattern data described in test cycle units is a delay waveform or a pulse waveform. If the waveform mode is determined to be a delayed waveform,
A step of generating a delay circuit as a timing generation circuit for outputting a simulator input data in which a signal level at each waveform change time is described by delaying the input test pattern data by a given time and outputting the simulator input data; When the waveform mode is determined to be a pulse waveform, a timing generation circuit which receives the input test pattern data and outputs simulator input data describing a signal level at each waveform change time having a predetermined pulse width. Generating a pulse generation circuit as pulse data by the pulse generation circuit generation means, and providing the circuit connection information data of the logic circuit to the incorporation means to input the input pin of the logic circuit indicated in the circuit connection information data, Means or a timing generation circuit generated by the pulse generation circuit generation means Applying the test pattern data described in test cycle units to a logic circuit in which the timing generation circuit is connected to an input pin by the incorporation means, and the logic circuit is described for each waveform change time by the timing generation circuit. Applying the data converted to the simulator input data to a logic circuit, performing a logic simulation by a logic simulator, and outputting a logic simulation result described in test cycle units. Simulation method for logic circuits. 2. A method for simulating a logic circuit, comprising: determining whether the waveform mode of input test pattern data described in test cycle units is a delay waveform or a pulse waveform, for each input pin of the logic circuit; A step of judging by a mode judging means, and when it is judged that the waveform mode inputted to the input pin is a delayed waveform, the input test pattern data is given and delayed by a predetermined time, and each time the waveform change time Generating, by the delay circuit generating means, a delay circuit as a timing generation circuit that outputs simulator input data in which the signal level of the input signal is described, and the waveform mode input to the input pin is determined to be a pulse waveform In the case where the input test pattern data is given, a signal at each waveform change time having a predetermined pulse width is provided. Generating a pulse generation circuit as a timing generation circuit that outputs simulator input data in which a bell is described by a pulse generation circuit generation means; and wherein the waveform mode input to the input pin is between a delay waveform and a pulse waveform. When it is determined that the waveform mode is switched, a step of generating a delay circuit by the delay circuit generating means or generating a pulse generating circuit by the pulse generating circuit means in accordance with the timing of switching the waveform mode; Providing data to the incorporation means, and connecting the timing generation circuit generated by the delay circuit generation means or the pulse generation circuit generation means to each input pin of the logic circuit indicated in the circuit connection information data, respectively; The timing is applied to each input pin by the incorporation means. A logic circuit to which a logic circuit is connected is provided with the test pattern data described in test cycle units, and converted into the simulator input data described for each waveform change time by the timing generation circuit. Performing a logic simulation by a logic simulator by applying the logic simulation to the input circuit, and outputting a logic simulation result described in a unit of a test cycle for each input pin. 3. The apparatus is provided with the input test pattern data,
3. The logic circuit simulation method according to claim 1, further comprising, after converting the input test pattern data conforming to the format of the logic simulator, applying the converted data to the logic simulator. 4. The apparatus is provided with the input test pattern data,
Generating correspondence data in which the input test pattern data is associated with address information indicating a test cycle; and using the correspondence data, address information obtained by adding the address information to the logic simulation result output by the logic simulator. 4. The logic circuit simulation method according to claim 1, further comprising a step of outputting a result of a logic simulation with a tag. 5. An apparatus for simulating a logic circuit, comprising: a waveform mode determining means for determining whether a waveform mode of input test pattern data described in test cycle units is a delay waveform or a pulse waveform; When the mode determination means determines that the waveform mode is a delayed waveform, the input test pattern data is given and delayed for a predetermined time, and the simulator input data in which a signal level at each waveform change time is described. A delay circuit generating means for generating a delay circuit as a timing generating circuit for outputting, and when the waveform mode determining means determines that the waveform mode is a pulse waveform, the waveform mode determining means is provided with the input test pattern data and given Simulator input data describing the signal level at each waveform change time with a pulse width of Pulse generating circuit generating means for generating a pulse generating circuit as a timing generating circuit to be supplied; circuit connection information data of a logic circuit being given; an input pin of the logic circuit indicated in the circuit connection information data; Means or a built-in means for connecting the timing generation circuit generated by the pulse generation circuit generation means, and the test pattern described in a test cycle unit in a logic circuit in which the timing generation circuit is connected to an input pin by the built-in means. Data is given, and the data converted into the simulator input data described for each waveform change time by the timing generation circuit is provided to a logic circuit to perform a logic simulation, and a logic simulation result described in test cycle units is output. Logic simulator and Simulation device on a logic circuit to. 6. An apparatus for simulating a logic circuit, wherein it is determined for each input pin of the logic circuit whether the waveform mode of the input test pattern data described in test cycle units is a delay waveform or a pulse waveform. When the waveform mode determining means determines that the waveform mode input to the input pin is a delayed waveform, the input mode is given the input test pattern data and delayed by a predetermined time, A delay circuit generating means for generating a delay circuit as a timing generating circuit for outputting a simulator input data describing a signal level at each waveform change time; and the waveform mode input to the input pin by the waveform mode determining means. If the input test pattern data is determined to have a pulse waveform, A pulse generating circuit generating means for generating a pulse generating circuit as a timing generating circuit for outputting simulator input data in which a signal level at each waveform change time having a width is described; If it is determined that the waveform mode is switched between a delay waveform and a pulse waveform, the delay circuit is generated by the delay circuit generation means or a pulse is generated by the pulse generation circuit means in accordance with the timing at which the waveform mode switches. Switching control means for generating a generation circuit; and circuit connection information data of a logic circuit, the delay circuit generation means or the pulse generation circuit being provided to each input pin of the logic circuit indicated by the circuit connection information data. Embedded means for respectively connecting the timing generation circuits generated by the generation means, The test pattern data described in test cycle units is given to the logic circuit in which the timing generation circuit is connected to each input pin by the incorporation means, and the logic described in the timing generation circuit is described for each waveform change time. A logic simulator that performs a logic simulation by providing the logic circuit with the data converted into the simulator input data, and outputs a logic simulation result described in a unit of a test cycle for each input pin. Logic circuit simulation device. 7. The apparatus is provided with the input test pattern data,
7. The logic circuit simulation apparatus according to claim 5, further comprising a format conversion unit that converts the input test pattern data conforming to the format of the logic simulator to the logic tester and converts the input test pattern data to the logic simulator. 8. The apparatus is provided with the input test pattern data,
Means for generating correspondence data in which the input test pattern data is associated with address information indicating a test cycle; and using the correspondence data, address information obtained by adding the address information to the logic simulation result output by the logic simulator. 8. The logic circuit simulation apparatus according to claim 5, further comprising means for outputting a result of a logic simulation with a tag.