JPH1155092A - Clock generating circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a clock circuit which can generate a clock signal even when a time to load data at a counter circuit is simultaneous with time to generate the clock signal stores a count data. SOLUTION: A data generator 4 as a obtained by previously subtracting '1' from the number of times of set counting, the count data are loaded to a counter circuit 3 by a load signal generated from a rate generator 2 by a reference clock signal generated by an oscillator 1, the clock signal is generated while being counted by the reference clock signal, and when the count value is '-1' the clock signal outputted to a 1st route 7 is outputted to a selector circuit 6 by a minus flag signal 4b without being delayed. When the count value is any value except for '-1' the clock signal is outputted to a 2nd route 8, delayed just by the delay time of the same cycle as the reference clock signal and outputted through the selector circuit 6.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock generation circuit applied to an integrated circuit test device for testing functions and electrical characteristics of a semiconductor integrated circuit.

[0002]

2. Description of the Related Art FIG.
This will be described with reference to FIG. FIG. 3 is a block diagram of a clock generation circuit when a conventional integrated circuit test device tests a memory IC. In FIG. 3, an oscillator 1 is a device that generates a reference clock signal as shown in FIG. 4A for a rate generator 2 and a counter circuit 3.

A rate generator 2 has an arbitrary rate (the period of a signal applied to a device under test, not shown) in synchronization with the reference clock signal from the oscillator 1 as shown in FIG.
A load signal as shown in (c) is generated.

The counter circuit 3 loads the count data as shown in FIG. 4B from the data generator 4 with the load signal output from the rate generator 2 and counts with the reference clock signal from the oscillator 1. When the number of times of counting coincides with the number of times of counting the data output from the data generator 4, a clock signal is generated as shown in FIG. The count data of the data generator 4 is written in advance by the controller 5 before the counter circuit 3 operates.

[0005]

In the conventional clock generating circuit, the counter circuit 3 loads the count data output from the data generator 4 with the load signal generated by the late generator 2, and the counter circuit 3 When the number of times matches the count number of the loaded count data, a clock signal is generated. However, when the load signal output from the rate generator 2 coincides with the time when the clock signal is generated in the counter circuit 3, as shown by a broken line circle A in FIG. Has a problem that no clock signal is generated to start the next counting operation.

According to the present invention, a clock signal is generated even when the time for loading the next count data into the counter circuit and the time for generating the clock signal by the counter circuit coincide with the load signal output from the rate generator. It is an object of the present invention to provide a clock generation circuit capable of performing the above.

[0007]

In order to achieve this object, a clock generating circuit according to the present invention comprises an oscillator 1 for generating a reference clock signal, a count data of a value obtained by subtracting "1" from a preset count number in advance and an original count data. A data generator 4 that outputs a minus flag signal when the count number obtained by subtracting “1” from the set count number becomes “−1”.
A rate generator 2 for generating a load signal of an arbitrary rate in synchronization with the reference clock signal generated from the oscillator 1; and loading the count data by the load signal output from the rate generator 2. When the set count is "-1", a clock signal is generated without delay. When the set count is other than "-1", the clock signal is generated by the reference clock signal cycle. And a counter circuit 3 generated with a delay in the same cycle.

[0008]

Next, an embodiment of a clock generation circuit according to the present invention will be described with reference to FIG. FIG. 1 is a block diagram showing the configuration of the first embodiment of the present invention. In FIG. 1, the same parts as those in the conventional example in FIG. A reference clock is sent from an oscillator 1 to a rate generator 2 and a counter circuit 3. The late generator 2 sends a load signal having an arbitrary rate to the counter circuit 3 and the data generator 4 in synchronization with the reference clock. This load signal has a cycle of a signal applied to a device under test (a semiconductor integrated circuit such as a memory IC) not shown.

The count data is written in the data generator 4 before the counter circuit 3 starts operating from the controller 5. The count data written in the data generator 4 is "1" from the originally set count number.
Is the number of counts of the count data 4a obtained by subtracting. The output from the data generator 4 includes the count data 4a for the counter circuit 3 to count and generate a clock signal, and the output from the original set count. It is divided into a minus flag signal 4b when the count number obtained by subtracting "1" becomes "-1".

The count data 4a is input to the counter circuit 3, and the minus flag signal 4b is sent to the selector circuit 6 as a selection signal. When the original set count is “0”, the set count becomes “−1”. Here, the count data in this case is referred to as operation count data.

The counter circuit 3 loads the count data 4a stored in the data generator 4 by the load signal output from the rate generator 2, and counts the count data 4a by the reference clock signal from the oscillator 1. To generate a clock signal.

When the operation count data is "-1", the counter circuit 3 cannot operate. Therefore, the counter circuit 3 is connected to the output side of the counter circuit 3 via the first path 7 and the second path 8. It is connected to the input side of the selector circuit 6.

The first path 7 outputs the clock signal output from the counter circuit 3 as it is, without delay, to the terminal 6 a of the selector circuit 6 only when the operation count data is “−1”. Is entered. A delay element 9 is inserted in the second path 8 so as to have a delay time corresponding to the cycle of the reference clock generated by the oscillator 1.

A clock signal output from the counter circuit 3 is guided to the second path 8 when the operation count data is other than "-1" and sent to the terminal 6b of the selector circuit 6. The selector circuit 6 is configured to output a clock signal by switching so that only the clock signal of the first path 7 is selected using the minus flag signal 4a output from the data generator 4 as a selection signal.

Next, the operation of the first embodiment will be described with reference to the timing chart of FIG. First, before the counter circuit 3 starts operating, the controller 5 stores the count number of count data obtained by subtracting “1” from the originally set count number in the data generator 4.

In this state, a reference clock signal as shown in FIG. 2A is sent from the oscillator 1 to the rate generator 2 and the counter circuit 3. By inputting the reference clock signal, the rate generator 2 generates a load signal having an arbitrary rate as shown in FIG. 2C in synchronization with the clock signal.

This load signal is sent to the data generator 4 and the counter circuit 3. The data generator 4 reads out the operation count data 4a (see FIG. 2B) obtained by subtracting "1" from the set count stored in the data generator 4 by the load signal, and outputs the read count data to the counter circuit 3. Is output.

In the counter circuit 3, operation count data is loaded at the timing of generation of a load signal, and counting is started by a reference clock signal. The operation count data 4a is "-1" with respect to the originally set count number.
Therefore, the time for loading the count data in the counter circuit 3 which has existed with the conventional set count number does not match the time for outputting the clock signal by counting with the reference clock signal.

The operation count data 4a in the counter circuit 3 is the same for both "-1" and "0", and the operation in the counter circuit 3 is the same.
In the case of "1", the counter circuit 3 cannot operate, so the data generator 4 sends the minus flag signal 4b to the selector circuit 6 only when the operation count data 4a is "-1".

As a result, the selector circuit 6 receives the clock signal output from the first path 7 and counted by the counter circuit 3 without delay as shown in FIG. And output.

On the other hand, when the operation count data 4a in the counter circuit 3 is other than "-1", the data generator 4 does not output the minus flag signal 4b, and the clock signal generated by the counter circuit 3 is the second signal. Is output to the path 8. In the second path 8, for example, a delay element 9 such as an inductive element having the same delay time as the period of the reference clock signal generated by the oscillator 1 is inserted, and therefore, as shown in FIG. The clock signal output to the second path 8 is delayed by the delay time and output through the selector circuit 6 as shown in FIG.

That is, the minus flag signal 4b whose count data in the counter circuit 3 is other than "-1"
When the clock signal does not occur, the controller 5 adds a value obtained by subtracting “1” from the originally set count number in advance to the clock signal obtained by the counter circuit 3 and output to the second path 8 for correction. Do.

On the other hand, when the operation count data in the counter circuit 3 is "-1", the clock signal output from the counter circuit 3 to the first path 7 is not delayed, and 6, the selector circuit 6 selects and outputs the clock signal guided from the first path 7 in accordance with the minus flag signal 4b input to the selector circuit 6 from the terminal 6a. 1) The time is reduced by the count and output. Therefore, when the waveform is observed as the clock generation circuit, the time for loading the next count data into the counter circuit 3 by the load signal output from the late generator 2 and the time for the counter circuit 3 to generate the clock signal Even in the case of coincidence, a clock signal can be generated as shown in FIG.

That is, by setting the time difference between the first path 7 and the second path 8 to be the cycle time of the reference clock signal of the oscillator 1, when the count data 4a in the count circuit 3 is "-1", , The same as the case where the number of times of counting is smaller by one.

[0025]

According to the present invention, a count signal obtained by subtracting "1" from the set count previously stored in the data generator is counted by the reference clock signal to generate a clock signal, and the set count is "-". In the case of "1", the clock signal is output without delay, and in the case where the set count number is other than "-1", the clock signal is output with the same delay as that of the reference clock signal. Therefore, the clock can be generated even if the time for loading the data and the time for generating the clock are simultaneous in the counter circuit.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a clock generating circuit according to a first embodiment of the present invention;

FIG. 2 is a timing chart for explaining an operation of the clock generation circuit of FIG. 1;

FIG. 3 is a block diagram showing a configuration of a conventional clock generation circuit.

FIG. 4 is a timing chart for explaining the operation of the clock generation circuit of FIG. 3;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Oscillator 2 Late generator 3 Counter circuit 4 Data generator 5 Controller 6 Selector circuit 7 First path 8 Second path 9 Delay element

Claims (4)

[Claims] An oscillator for generating a reference clock signal (1)
And a data generator that outputs count data of a value obtained by subtracting “1” from the preset count number and a minus flag signal when the count number obtained by subtracting “1” from the original set count number becomes “−1”. (4), a rate generator (2) that generates a load signal of an arbitrary rate in synchronization with the reference clock signal generated from the oscillator (1), and a rate generator (2) that is output from the rate generator (2). The count data is loaded by the load signal and counted by the reference clock signal. When the set count is "-1", a clock signal is generated without delay and the set count is other than "-1". A counter circuit (3) for generating a clock signal delayed by the same period as the reference clock signal period. 2. The clock generation circuit according to claim 1, wherein said count data of said counter circuit is "-1".
In the case of (1), the first path (7) for leading the clock signal output from the counter circuit and the count data of the counter circuit (3) are "-1".
Otherwise, a second path (8) for leading the clock signal output from the counter circuit with a delay time corresponding to the cycle of the reference clock signal, and a second path (8) for counting the count of the counter circuit (3) Data is "-1"
In other cases, the data generator outputs the clock signal guided to the second path (8), and the data generator only when the count data of the counter circuit (3) is "-1".
A selector circuit (6) for selecting and outputting the clock signal guided to the first path (7) according to the minus flag signal output from (4). 3. The clock generation circuit according to claim 1, wherein the count data is output from a controller (5) and stored in advance in the data generator (4). 4. A test burn-in system using the clock generation circuit according to claim 1.