JP2000338184A - Fault simulator - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a fault simulating method and a fault simulator capable of reducing a calculation time and a cost for calculating a fault detection rate in the whole of an integrated circuit. SOLUTION: A fault dictionary for a module single body is prepared is a fault dictionary preparing part 11, and is formed into a library to be stored in a library storing part 12. The presence of a library of a module contained in an integrated circuit to find a fault detection rate is detected therefrom in a presence-of-library detecting part 13, the library is applied when detected, and the fault dictionary for a corresponding module is prepared in the fault dictionary preparing part 11, when not detected, to be stored in the library storing part 12. A connecting condition between the module single body and a module part in the integrated circuit is analyzed by an integrated circuit analyzing part 14 to prepare a dictionary as the module part. A fault assumption portion file as to the module part and its peripheral part is prepared by a fault assumption portion file preparing part 15, fault simulation for the integrated circuit is conducted by a fault simulation executing part 16 to prepare a peripheral part fault dictionary, and the fault dictionary and the fault detection rate of the integrated circuit are found by a fault detection rate calculating part 17.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a failure simulator, and more particularly to a megacell and an intellectual property (IP).
The present invention relates to a failure simulation for obtaining a failure detection rate by performing a failure simulation of an integrated circuit including at least one module such as the above.

[0002]

2. Description of the Related Art Conventionally, when testing an integrated circuit including at least one module and a peripheral circuit, the test is performed separately for each module. Was performing a failure simulation.

[0003] The failure detection rate of each module has been obtained by executing a failure simulation by itself. But,
Even if the same module is included in an integrated circuit, the internal connection state often differs for each product. For this reason, the failure simulation is performed again on the entire integrated circuit including the module without using the result of the failure detection rate obtained for the module alone. For this reason,
An enormous amount of time and cost was required to obtain a failure detection rate for each integrated circuit as a whole.

[0004]

As described above, conventionally, when a fault detection rate of a different integrated circuit including the same module is obtained, each of the integrated circuits can be integrated without using the fault detection rate obtained by the module alone. Since the failure simulation was performed again for the entire circuit, the time and cost required for the failure simulation were enormous.

The present invention has been made in view of the above circumstances, and has as its object to provide a failure simulation method and a failure simulator capable of reducing the time and cost for calculating the failure detection rate.

[0006]

SUMMARY OF THE INVENTION A fault simulator of the present invention is a fault simulator for performing a fault simulation of an integrated circuit including at least one module section and a peripheral section. A failure dictionary storage unit, a library presence detection unit that detects whether a library of a failure dictionary of the module alone exists in the failure dictionary storage unit, and the library presence detection unit does not detect the presence of the library. A failure dictionary creating unit for creating a failure dictionary of the module alone for storing in the failure storage unit, and a failure dictionary of the module alone stored in the failure dictionary storage unit, Using a netlist, the module alone included as a module in the integrated circuit An integrated circuit analysis unit that analyzes a connection state between a terminal and a terminal of the integrated circuit and creates a failure dictionary of the module unit from a failure dictionary of the module using the analysis result, and a failure dictionary of the module unit. A fault assumption location file for the module section, a failure assumption location file creating section for creating the fault assumption location file for the peripheral section, a failure assumption location file for the module section, and a fault assumption location for the peripheral section. Files and
A fault simulation executing unit that executes a fault simulation for the integrated circuit using the netlist of the integrated circuit and test data of the integrated circuit to create a fault dictionary of the peripheral unit; and a fault dictionary of the module unit. And a calculating unit for obtaining a fault detection rate and a fault dictionary of the integrated circuit by using the fault dictionary of the peripheral part.

Here, the failure dictionary creating unit simulates the failure of the module alone using the netlist of the module alone and the test data of the module alone, and detects the failure detection rate and the failure dictionary of the module alone. May be created.

[0008] The integrated circuit analysis unit may use the netlist of the integrated circuit, the netlist of the module alone, and the failure dictionary of the module alone to integrate the output pin of the module. A failure dictionary of the module unit including information on whether or not the module is directly connected to an output pin of the circuit may be created.

A failure simulation method according to the present invention is a method for performing a failure simulation of an integrated circuit including at least one module part and a peripheral part by using a failure simulator. Detecting whether a library of the fault dictionary of the module alone is present in the fault dictionary storage unit performing the module, and using the fault dictionary of the module and the netlist of the integrated circuit to perform the integration. The connection state between the terminal of the module unit included in the circuit as a module unit and the terminal of the integrated circuit is analyzed, and the failure dictionary of the module unit is created from the failure dictionary of the module unit using the analysis result. Using the failure dictionary of the module unit and a failure assumption location file of the module unit. Creating a fault assumption location file for the peripheral part, a failure assumption location file for the module part, a failure assumption location file for the peripheral part, a netlist of the integrated circuit, Performing a failure simulation on the integrated circuit using test data to create a failure dictionary for the peripheral part; and using the failure dictionary for the module part and the failure dictionary for the peripheral part, Calculating the failure detection rate and the failure dictionary.

Here, in the step of creating a failure dictionary of the module unit, a failure simulation of the module unit is performed using a net list of the module unit and test data of the module unit, and a failure simulation of the module unit is performed. A failure detection rate and a failure dictionary may be created.

In the step of creating the failure dictionary of the module, the output of the module is output using the netlist of the integrated circuit, the netlist of the module alone, and the failure dictionary of the module alone. A failure dictionary of the module unit may be created including information on whether a pin is directly connected to an output pin of the integrated circuit.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows a configuration of a fault simulator according to the present embodiment. In this failure simulator, a failure dictionary creation unit 11 that creates a failure dictionary for each module, a library storage unit 12 that stores a failure dictionary for each module as a library, and a library of failure dictionaries for the module in the library storage unit 12. A library presence detection unit 13 for detecting whether or not the connection is established between a terminal of the module unit and a terminal of the integrated circuit to generate a failure dictionary of the module unit included in the integrated circuit from the failure dictionary of the module unit A circuit analysis unit 14, a failure assumption location file creation unit 15 that creates a failure assumption location file of a module section and a failure assumption location file of a peripheral section using a failure dictionary of the module section, and a failure assumption location file and a surrounding area of the module section. Part failure assumption file, integrated circuit netlist, and integrated circuit test data. A failure simulation execution unit 16 that executes a failure simulation of the entire integrated circuit and creates a failure dictionary of the peripheral part; and a failure detection rate calculation that calculates a failure detection rate using the failure dictionary of the module part and the failure dictionary of the peripheral part. A part 17.

With this configuration, according to the present embodiment, the connection state between the terminal of the module included in the integrated circuit and the terminal in the integrated circuit is analyzed, and the module unit that has been library-prepared in advance is analyzed. By diverting the failure dictionary and performing the failure simulation only on the parts other than the dictionary, the failure detection rate of the entire integrated circuit can be efficiently calculated.

FIG. 2 is a flowchart showing a procedure for obtaining a failure detection rate according to the present embodiment.

As a step S1, a file 21 for designating a module name included in the integrated circuit is inputted, and whether or not the file exists in a module name list file 23 in the failure dictionary library 22 stored in the library storage unit 12 is determined. Is detected.

In step S2, if all the corresponding module names exist, the process proceeds to step S4. Otherwise, that is, if at least one module name does not exist, the process proceeds to step S3. A failure dictionary is created for each module for which no dictionary exists. Here, a library is created in order to make the failure dictionary for the module itself once created available later when it is included in another integrated circuit.

FIG. 3 shows a procedure for obtaining a fault dictionary and a fault detection rate for a single module. A net list 25 indicating connection information of each element in a single module and test data 42 of a single module are input, and step S1 is performed.
As 1, the failure simulation of the module alone is executed. Thereby, the failure dictionary 24 of the module alone is
And the failure detection rate 44 of the module alone.

In a normal fault simulation, once a fault location is detected, the fault location is excluded from fault detection targets at subsequent test data times. However, when creating a fault dictionary for a single module, a fault simulation is performed for all fault locations at all times of the test data.

Here, the circuit configuration of the module alone is shown in FIG.
FIG. 5 shows the format of the failure dictionary in this case. The failure dictionary of the module alone is the failure detection time 51
And the fault location 5 detected by the fault simulation
2, an output pin 53 of the module, a normal value 54 of the output pin when a failure is detected, and a failure value 55 of the output pin.

When the failure dictionaries of all the modules included in the integrated circuit become available, the integrated circuit is analyzed in step S4. The analysis procedure in this case is shown in FIG.

The netlist 26 of the integrated circuit, the netlist 25 of the module alone, and the failure dictionary 24 of the module as a library are input, and information is acquired for each pin of the module as step S1.

In step S22, it is determined whether or not the signal of the output pin of the module unit is directly output from the integrated circuit to the outside, that is, whether or not the output pin is directly connected to the output terminal of the integrated circuit. If they are directly connected, a new failure dictionary including detected or undetected information is created in step S23. If not output,
Move to step S24.

In step S24, it is determined whether the pin is an open pin. If it is an open pin, undetectable information is added to the failure dictionary of the module in step S25.

In step S26, it is determined whether or not the processing has been performed for all the output pins of the module section, and the flow returns to step S21 to repeat the above processing until the processing is completed.

In step S27, a failure dictionary 27 for the module is created using the obtained new failure dictionary and the undetectable information. Here, the module unit refers to a module in a state where a single module is incorporated in an integrated circuit. FIG. 7 shows a format of the failure dictionary 27 of the module unit. This failure dictionary 27
Is a fault assumption location name 71, a detection result 72 regarding the presence or absence of fault detection, a detection time 73, and an unmatched pin name 74.
And are included. Here, the detection result 72 indicates the result of detection or non-detection of each of the assumed fault location names 71, and the detection time 73 and the unmatched pin name 74 are stored only when the result is detection.

Next, as step S5 in FIG.
A failure assumed location file 28 for the module is created.

As shown in FIG. 7, the failure dictionary of the module unit may include an undetected failure assumed location N5. However, by performing the failure detection of the entire integrated circuit, there may be a case where an undetected failure assumed portion in such a module unit can be detected. Therefore, a fault assumption location file 28 for the module is created using the information on the undetected fault assumption locations.

Fault assumption location file 28 for module section
8 is as shown in FIG. 8, and includes a fault assumed location name 81, a detection result 82, a detection time 83, and an unmatch pin 84, like the failure dictionary 27 of the module unit shown in FIG. The detection results 82 are all undetected.

In step S6, the analysis of the integrated circuit in step S4 and the creation of the assumed fault location of the module in step S5 are repeated until the circuit analysis is completed.

Next, as a step S7, a failure assumed location file 30 is created for peripheral parts of the integrated circuit except for the module part.

FIG. 9 shows the format of the assumed failure location file 30. The failure assumption location file 30 includes a failure assumption location name 91, a detection result 92, a detection time 93, and an unmatch pin 94, similarly to the failure dictionary 27 of the module unit shown in FIG. In the peripheral area, there is no library of the failure dictionary, and it is necessary to perform failure detection for the entire integrated circuit. Therefore, the detection result 92 is not yet executed at this point.

In step S8, a failure simulation of the entire integrated circuit is performed by using the assumed failure location file 30 of the peripheral part, the assumed failure location file 28 of the module part, and the integrated circuit test data 29. This allows
The failure dictionary 31 for the peripheral part is created.

The peripheral failure dictionary 31 has a format as shown in FIG. 10, and includes a failure assumption part 101, a detection result 102, a detection time 103, and an unmatch pin 104.
Contains. Detected or undetected is entered in the failure assumption part name 101 as the execution result of the failure simulation.

In step S9, the peripheral failure dictionary 3
1 and the failure dictionary 27 of the module section as inputs, the failure detection rate of the integrated circuit is calculated, and the failure dictionary 33 of the integrated circuit is calculated.
And the fault detection rate 32 of the integrated circuit.

The fault dictionary 33 of the integrated circuit has a format as shown in FIG.
1, a detection result 112, a detection time 113, and an unmatch pin 114. Detected or undetected is written as the detection result 112.

The processes from step S1 to step S9 are repeated by the number of test data, and a fault detection rate and a fault dictionary for the entire integrated circuit are created for each test data.

The failure simulator according to the present embodiment and a method for performing a failure simulation using the same have been described above. Here, in the present embodiment, a library of a failure dictionary for a single module is prepared, and a failure simulation time and cost are reduced by using a library of failure dictionaries for module units included in the integrated circuit. There is a feature. Therefore, a procedure for creating the failure dictionary 27 of the module portion included in the integrated circuit by using the failure dictionary of the module alone in the library will be described in detail below.

FIG. 12 shows an example of the configuration of an integrated circuit.
This integrated circuit includes a module unit 129, selectors 123 and 126 as peripheral units, and inverters IN101 to IN101.
N103 is provided. The module unit 129 has a configuration as shown in FIG. 4 as a single module, and has input pins I1, I2, I3 and output pins A, B, C, D, E as external pins.

As shown in FIG. 5, the fault dictionary 24 of the module alone includes a fault detection time 51, a fault location 52 detected by the fault simulation, a normal value 54 of the output pin at the time of fault detection, and a fault value. Value 55.

In the failure detection determination method in the failure simulation, when the normal value 54 of the output pin is different from the failure value 55, it is determined that a failure has been detected.

The external output pins A, B,
C, D, and E are external output pins 01, 02, 0 of the integrated circuit.
3, 04, 05 are directly connected.

At the failure detection time 1000, the output pin of the module whose normal value is different from the failure value is B, and it becomes the node N1 as a failure location. This information is described in the failure dictionary 27 of the module unit shown in FIG. The failure assumption part name 71 is “N1”, the detection result 72 is “detection”, the detection time 73 is “1000”, and the unmatched pin is “O2”. Here, since the unmatched pin is output under the name of the external pin in the integrated circuit, the external pin B of the module alone becomes “O2” as the external pin of the integrated circuit.

Such processing is repeated at each time. The fault location already detected at the previous time is not output as the fault dictionary 27 of the module unit. For a failure location where a failure cannot be detected, “N5” is output as the assumed failure location name and “not detected” is output as the detection result in the failure dictionary 27 of the module unit shown in FIG. Further, the name of a failure assumption part which is not detected in the failure dictionary 27 of the module part is output to the failure assumption part file 28 of the module part shown in FIG. That is, “N5” is output as the assumed fault location name 81 and “not detected” is output as the detection result. As shown in FIG. 9, when creating the peripheral assumed fault location file 30, the fault location name obtained by removing the fault assumed location name of the module part from the fault assumed location name of the entire integrated circuit is used as the fault location of the peripheral part. Output as the assumed location name 91. The assumed fault location names are A1, A2, A3, B
1, B2, B3, C1, C2, C3, D1, D2, D
3, E1, E2, and E3 are targets, and all “unexecuted” are output as detection results.

In the failure simulation of the integrated circuit, the assumed failure location file 30 in the peripheral portion shown in FIG.
Assumed fault location file 28 of the module shown in FIG.
The net simulation 26 of the integrated circuit and the test data 29 of the integrated circuit are input, and the fault simulation is executed by the number of test data input to the integrated circuit.

However, when all functions are not used in a state where the test data is incorporated in the integrated circuit from the test data used for creating the failure dictionary of the module alone, only the test data relating to the function to be used is targeted. For example, if there are 10 test data used for a single module and 8 test data are to be incorporated into a module in an integrated circuit, a failure simulation is performed only for the 8 test data. I do.

After execution, a peripheral failure dictionary 31 as shown in FIG. 10 is created. The created peripheral failure dictionary 31 includes a module assumed failure location file 28.
The fault assumption location name “N5” designated by “1” is also included. In the processing of step S9 for calculating the failure detection rate of the integrated circuit, the failure dictionary 33 of the integrated circuit shown in FIG. 11 is created by using the failure dictionary 31 of the peripheral part and the failure dictionary 27 of the module part. .

The fault dictionary 33 of the integrated circuit stores, as fault assumed location names 111, A1, A2, A3, B1, B
2, B3, C1, C2, C3, D1, D2, D3, E
1, E2, E3, and N1, N2, N3,
A total of 20 N4 and N5 are output. The fault detection rate 32 of the integrated circuit is obtained using the fault dictionary 33 of the integrated circuit. There are 20 assumed fault locations of the integrated circuit, 15 detected fault assumed locations, and 5 undetected fault assumed locations. Therefore, the failure detection rate is 15 (detection) / 2.
0 (entire) × 100% = 75%.

According to this embodiment, a fault dictionary obtained by executing a fault simulation on a single module is stored in a library, and a fault detection rate of the entire integrated circuit including at least one module and a peripheral portion is stored. By using the fault dictionary of the module alone in the library when obtaining the above, it is not necessary to perform the fault simulation again up to the module part included in the integrated circuit, so that the time and cost can be reduced.

The above-described embodiment is merely an example, and does not limit the present invention. For example, the format of the failure dictionary of the module shown in FIG.
The format of the failure dictionary of the module section shown in (1) is an example, and can be changed as needed.

[0051]

As described above, according to the fault simulation method and the fault simulator of the present invention, a fault dictionary obtained by executing a fault simulation by a single module is stored in a library, and an integration including at least one module is performed. When determining the fault detection rate of a circuit, the need for performing a fault simulation including the module again is eliminated by diverting the fault dictionary of the module as a library, reducing the time and cost required for the fault simulation. It is possible to

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a fault simulator according to an embodiment of the present invention.

FIG. 2 is a flowchart showing a procedure of processing in a failure simulation according to one embodiment of the present invention.

FIG. 3 is a flowchart showing a procedure for creating a failure dictionary for a single module in the failure simulation.

FIG. 4 is a circuit diagram showing a configuration of a module alone.

FIG. 5 is an explanatory diagram showing an example of a format of a failure dictionary of a module alone.

FIG. 6 is a flowchart showing a procedure for analyzing an integrated circuit.

FIG. 7 is an explanatory diagram showing an example of a format of a failure dictionary of a module unit in an integrated circuit.

FIG. 8 is an explanatory diagram showing an example of a format of a failure assumed location file of a module unit.

FIG. 9 is an explanatory diagram showing an example of a format of a fault assumption location file in a peripheral portion.

FIG. 10 is an explanatory diagram showing an example of a format of a failure dictionary in a peripheral portion.

FIG. 11 is an explanatory diagram showing an example of a format of a failure dictionary of an integrated circuit.

FIG. 12 is a circuit diagram showing a configuration of an integrated circuit including a module section and a peripheral section.

[Explanation of symbols]

11 failure dictionary creation unit 12 library storage unit 13 library existence detection unit 14 integrated circuit analysis unit 15 failure assumption location file creation unit 16 failure simulation execution unit 17 failure detection rate calculation unit 21 module unit designation file 22 failure dictionary library 23 module name list File 24 Module failure dictionary 25 Module netlist 26 Integrated circuit netlist 27 Module failure dictionary 28 Module failure assumption location file 29 Integrated circuit test data 30 Peripheral failure assumption location file 31 Peripheral Failure dictionary 32 failure detection rate of integrated circuit 33 failure dictionary of integrated circuit 42 test data of single module 44 failure detection rate of single module 121, 122 input pins 123, 126 of integrated circuit selector 12 , The output pin of the output pin 131 integrated circuit node 129 module 130 module alone the periphery of 125,127,128 integrated circuits IN1 to IN3, IN101～IN103 inverter NA1 NAND circuit OR1 OR circuits EX1 EX-OR circuit

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Masaki Uehara 25-1, Ekimae Honcho, Kawasaki-ku, Kawasaki, Kanagawa Prefecture Inside Toshiba Microelectronics Co., Ltd. (72) Inventor Mamoru Takatsuka 25, Ekimae-Honcho, Kawasaki-ku, Kawasaki-ku, Kanagawa Prefecture Address 1 Toshiba Microelectronics Co., Ltd. (72) Inventor Naoki Goto 25-eki Ekimae, Kawasaki-ku, Kawasaki-shi, Kanagawa 25-1 Toshiba Microelectronics Co., Ltd. (72) Inventor Yusuke Inoue, Kawasaki-ku, Kawasaki-shi, Kanagawa 25-1 Honcho Toshiba Microelectronics Corporation (72) Inventor Yukihiro Abe 25-1 Ekimae Honcho, Kawasaki-ku, Kawasaki-shi, Kanagawa Prefecture F-term in Toshiba Microelectronics Corporation 2G032 AA01 AB20 AC09 AD00 AE07 AE08 AE10 AE12 AG10 5B046 AA08 BA09 JA04 KA06 5B 048 AA20 DD11 DD16 5F064 DD04 DD25 HH06 HH09 HH10 HH12

Claims (6)

[Claims] 1. A failure simulator for performing a failure simulation of an integrated circuit including at least one module unit and a peripheral unit, comprising: a failure dictionary storage unit configured to store a failure dictionary of a single module as a library; A library presence detecting unit for detecting whether a library of a failure dictionary of the module alone exists in the unit; and storing the failure dictionary in the failure dictionary storage unit when the library presence detecting unit does not detect the presence of the library. A failure dictionary creating unit for creating a failure dictionary for the module alone; and using the failure dictionary for the module alone stored in the failure dictionary storage unit, using the netlist of the integrated circuit, The connection state between the terminal of the module unit included in the module unit and the terminal of the integrated circuit Analyzing, an integrated circuit analysis unit that creates a failure dictionary of the module unit from the failure dictionary of the module using the analysis result, and a failure assumption location file of the module unit using the failure dictionary of the module unit A fault assumption location file creating section for creating the fault assumption location file of the peripheral portion; a failure assumption location file of the module portion; a failure assumption location file of the peripheral portion; a netlist of the integrated circuit; A failure simulation execution unit that performs a failure simulation on the integrated circuit using test data of an integrated circuit and creates a failure dictionary of the peripheral unit; a failure dictionary of the module unit; and a failure dictionary of the peripheral unit. A calculating unit for calculating a fault detection rate and a fault dictionary of the integrated circuit. Simulator. 2. The failure dictionary creating section simulates a failure of a single module using a netlist of the single module and test data of the single module, and detects a failure detection rate and a failure dictionary of the single module. The fault simulator according to claim 1, wherein 3. The integrated circuit analyzing section, using a netlist of the integrated circuit, a netlist of the module, and a failure dictionary of the module, outputs the output pin of the module. 2. The fault simulator according to claim 1, wherein a fault dictionary of the module unit including information on whether or not the module is directly connected to an output pin of the integrated circuit is created. 4. The method according to claim 1, wherein at least one
A method of performing a failure simulation of an integrated circuit including two module parts and a peripheral part, wherein a library of failure dictionaries of a single module exists in a failure dictionary storage unit that stores a failure dictionary of a single module as a library. Detecting whether or not the library does not exist; creating a failure dictionary for the module alone and storing the failure dictionary in the failure dictionary storage unit; and detecting a failure of the module stored in the failure dictionary storage unit. Using a dictionary, using the netlist of the integrated circuit, analyze the connection state between the terminal of the module unit included as a module unit in the integrated circuit and the terminal of the integrated circuit, and use the analysis result. Creating a failure dictionary of the module unit from the failure dictionary of the module alone by using Creating a fault assumption location file for the module part and a fault assumption location file for the peripheral part using a failure dictionary for the module part; a failure assumption location file for the module part; and a failure assumption for the peripheral part. Executing a fault simulation for the integrated circuit using the location file, the netlist of the integrated circuit, and test data of the integrated circuit to create a fault dictionary for the peripheral portion; and a fault dictionary for the module portion. And a step of calculating a fault detection rate and a fault dictionary of the integrated circuit using the fault dictionary of the peripheral part. 5. The step of creating a failure dictionary for a single module includes the steps of:
The failure simulation method according to claim 4, wherein the failure simulation of the module alone is performed using the test data of the module alone, and a failure detection rate and a failure dictionary of the module alone are created. 6. The step of creating a failure dictionary of the module unit comprises using the netlist of the integrated circuit, the netlist of the module unit, and the failure dictionary of the module unit to generate the failure dictionary for the module unit. 5. The failure simulation method according to claim 4, wherein a failure dictionary of said module unit including information on whether said output pin is directly connected to an output pin of said integrated circuit is created.