JPH07319927A - System for measuring ratio of comprehension in logic verification - Google Patents

Abstract

PURPOSE:To provide a method for checking the operation of state transition in logical simulation and finding out a comprehension ratio, an operation part and an unoperation part. CONSTITUTION:A branch condition extracting part 1 inputs a source file 4, extracts a branch condition and outputs the extracted condition to a branch condition file 5. A branch condition dividing part 2 divides respective branch conditions read out from the file 5 into individual signals and prepares a branch condition signal file 6 together with signal values obtained when respective branch conditions are set up. A comprehension ratio measuring part 3 calculates the number of combinations capable of setting up individual signals of the branch conditions which are stored in the file 6, calculates the number of practically executed combinations out of the combinations read out from a simulation result file 9, prepares a list of unexecuted signals out of the calculated combinations, and outputs 'the number of executed combinations/the total number of combinations' as a comprehension ratio for logic verification to a comprehension ratio file 10 together with the list of unexecuted combinations.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to logic simulation, and more particularly to a method for measuring a test coverage rate from a simulation result based on a test pattern in logic verification.

[0002]

2. Description of the Related Art Conventionally, as a method of measuring a coverage rate in logic simulation, O of individual signals in a logic circuit is measured.
A method of measuring the occurrence rate of N / OFF events has been proposed. However, in the case of a complicated combinational circuit, it cannot be said that even if the operation of each signal is confirmed, the operation of the function given as the specification could not be confirmed, and it cannot be said that the coverage ratio is sufficiently expressed.

[0003]

Since the above-mentioned conventional technique does not consider the combination of a plurality of signals in the combination circuit, it is not directly connected to the function given as the specification and is suitable for measuring the coverage rate. It cannot be said that there is. In order to confirm the operation of the function in the combinational circuit, it is necessary to confirm the operation of the state transition.

An object of the present invention is to present a method of confirming the operation of state transition in logic simulation and determining the coverage and the execution / non-execution of the measurement unit.

[0005]

According to the coverage measuring method of the present invention, a source file of a hardware description language that describes hardware functions is input, a branch statement is detected from the input file, and a branch condition is extracted. A condition extraction unit,
A branch condition dividing unit that divides the branch condition extracted by the branch condition extracting unit into individual signals that compose the branch condition and records the value together with the value when the signal is satisfied, and an individual signal that is divided by the branch condition dividing unit. It is composed of a coverage number measuring unit which calculates the number of combinations of whether or not is satisfied, and outputs from the result of the simulation the coverage ratio and whether each combination is executed.

[0006]

In the hardware description language in which the function of hardware is described in the logic circuit, the state transition is expressed by a branch statement. In the present invention, since the execution rate of branch statements is measured, it is possible to easily confirm the operation of state transition. In particular,
Since the branch sentence is divided into individual signals inside it, it is also effective for abnormal operations that differ from normal operations.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a block diagram showing the construction of an embodiment of the present invention. Particularly, the portion surrounded by a dotted line is a portion relating to the present invention.

In the branch condition extraction unit 1, the source file 4
Is input and the branch condition file 5 is created. The branch condition dividing unit 2 creates a branch condition signal file 6 from the branch condition file 5. The coverage rate measuring unit 3 creates a coverage rate file 10 from the branch condition signal file 6 and the simulation result file 9 created by the logic simulator 8.

FIG. 2 shows an example of the source file 4.
In this example, there are two branch blocks, if blocks (401 to 405) and case blocks (406 to 413). In if block, operations 401 and 402 when satisfied and operation 4 when not satisfied
Branch in two ways 03 and 404, condition 1 in case block
There are three branches, that is, 407 and 408 are satisfied, 409 and 410 are satisfied, and 411 and 412 are not satisfied. The source file 4 is input to the branch condition extraction unit 1. Although the hardware description language VHDL is used in the present embodiment, the present invention is not limited to VHDL, and other hardware description languages such as Verilog and hardware description using drawings may be used by other companies in the same industry. It is easily applicable.

FIG. 3 is a flow chart for explaining the operation of the branch condition extraction unit 1. When the source file 4 is input, the branch condition extraction unit 1 first performs branch extraction, gives an identification name to the extracted branch (101), and then extracts and identifies each branch condition in the extracted branch statement. Give a name (10
2). Each is output to the branch condition file 5.

FIG. 4 shows a branch condition file 5 in the case of the embodiment. The branch condition file 5 is the branch name table 50.
1, branch condition name table 502, branch condition table 50
It consists of three. The branch name table 501 contains the branch identification names assigned by the branch extraction 101, and the branch condition name table 502 contains the branch condition identification names assigned by the branch condition extraction 102.
Stores the branch condition corresponding to each branch condition name. In the case of the embodiment, there are two branch statements, if statement and case statement. Therefore, the branch names of C1 and C2 are given to each. Furthermore, the branch condition “a =
"1-1" or b = "1" or c = "0""has C1-1,
The branch condition “X = 'STAT1'” of the branch C2 is C2-
1, C2-2 is added to "X = 'STAT2'" as a branch condition name. The branch condition file 5 is input to the branch condition dividing unit 2.

FIG. 5 is a flow chart for explaining the operation of the branch condition dividing unit 2. When the branch condition file 5 is input, the branch condition dividing unit 2 divides each branch condition into individual signals (201), and further extracts the value of each signal when the branch condition is satisfied (202). , And output to the branch condition signal file 6, respectively.

FIG. 6 is a branch condition signal file 6 in the case of the embodiment. The branch condition signal file 6 includes a branch name table 501, a branch condition name table 502, and a signal name table.
601 and the establishment signal value table 602. The individual signals calculated by the branch condition division unit 2 are designated as signal names 6
In 01, the value of each signal at the time of establishment is set to the establishment signal value table 60.
Store in 2. In the case of the embodiment, the branch condition C1-1 is satisfied when the signals (a, b, c) are (1, 1, 0), and the branch condition C2-1 is C2-2 when the signal X is'STAT1 '. Holds when signal X is'STAT2 '. The respective information is stored in the branch condition file 6. The branch condition signal file 6 is input to the coverage rate measuring unit 3 together with the simulation result file 9.

FIG. 7 shows a simulation result file 9
Is an example. The simulation result file 9 is obtained as an output of the logic simulator 8 with the source file 4 and the test data file 7 as input, and the value of each branch condition signal in each cycle is described. The logic simulator 8 is conventionally used and will not be mentioned in the present invention. Further, the simulation result file 9 does not need to describe only the value in each cycle of the branch condition signal as shown in FIG. 7, and if the value taken by the branch condition signal is included as information, It can be easily applied by other companies in the same industry.

FIG. 8 is a flow chart for explaining the operation of the coverage ratio measuring unit 3. The coverage measurement unit 3 calculates the number of combinations from the branch condition signal file 6 as to whether or not each signal of the branch condition is satisfied (301), and calculates the number of the combinations actually executed from the simulation result file 9. (302) and a list of combinations that have not been executed (303) are created. Furthermore, “the number of executed combinations / the total number of combinations” is calculated as the coverage of the logic verification (30
4) Output to the coverage rate file 10 together with the unexecuted combination list.

In the case of the branch condition signal file 6 of FIG. 6, there are two combinations of the signals a, b, and c in the branch C1 and there are two combinations of the combinations, and the number of combinations is 2 × 2 × 2 = 8. Are STAT1, STAT2, and other three types.
In the present invention, since a plurality of branches are considered independently, the total number of combinations is 8 + 3 = 11.

Further, in the case of the simulation result file 9 of FIG. 7, in branch C1 (0,0,0), (0,1,)
1), (0,1,0), (0,0,1), (1,0,1) 5
At the branch C2, STAT0, STAT1, STA
Three types of T2 are executed. Therefore, the coverage of logic verification in this case is (5 + 3) / (8 + 3) = 72.7%
Is. In addition, the unexecuted combination is (1,
0,0), (1,1,0), (1,1,1), and there is no branch C2.

As described above, in this embodiment, since the simulation result file is used as the interface between the coverage measurement processing and the logic simulation, if only the simulation result file can be output from the existing logic simulator, the simulation result file can be output to the existing logic simulator. It can be used only by combining the coverage measurement processing.

Further, as a modified example of the above embodiment, an actual form without using a simulation result file is also possible, and can be easily constructed by other companies in the same industry. That is,
The branching condition extracting unit 1 and the branching condition dividing unit 2 are left as they are, the coverage ratio measuring unit 3 is incorporated into the simulator, and the branching condition signal file 6 is used as an interface file at that time. In the modified example of this embodiment, since the simulation result file is not used, the memory capacity of the disk or the like is small, and the coverage rate can be measured during the execution of the simulation, so that the processing is also fast.

[0020]

According to the present invention, since the coverage rate is measured as the branch statement execution rate, it is possible to easily grasp the progress of the state transition test in the logic circuit.
This has the effect of reducing the time required for logic verification and ensuring sufficientness. In particular, since the branch sentence is divided into the individual signals inside the branch sentence, it is possible to confirm the operation even for an unexpected combination of signal values.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

FIG. 2 is a diagram showing an example of a source file to be simulated.

FIG. 3 is a flowchart showing the operation of a branch condition extraction unit.

FIG. 4 is an explanatory diagram of a branch condition file in the case of the embodiment.

FIG. 5 is a flowchart showing the operation of a branch condition dividing unit.

FIG. 6 is an explanatory diagram of a branch condition signal file in the case of the embodiment.

FIG. 7 is an explanatory diagram of an example of a simulation result file.

FIG. 8 is a flowchart showing the operation of the coverage measuring unit.

[Explanation of symbols]

1 ... Branch condition extracting unit, 2 ... Branch condition dividing unit, 3 ... Coverage rate measuring unit.

Continued Front Page (72) Inventor Toru Shonai 1-280 Higashi Koikekubo, Kokubunji, Tokyo Inside the Central Research Laboratory, Hitachi, Ltd.

Claims (1)

[Claims] 1. In a logic simulation, a source file of a hardware description language that describes hardware functions is input, a branch condition extraction unit that detects a branch statement from the input file and extracts a branch condition, and a branch condition extraction unit. Divide the branch condition extracted in step 1 into the individual signals that compose it, and record with the value when the signal was established, and whether the individual signals divided by the branch condition divider are satisfied. The method of measuring the coverage of logic verification, comprising: calculating the number of combinations of the above, and providing from the result of the simulation the coverage and a coverage measuring unit that outputs whether each combination has been executed.