JPH0514519Y2 - - Google Patents
Info
- Publication number
- JPH0514519Y2 JPH0514519Y2 JP1988114737U JP11473788U JPH0514519Y2 JP H0514519 Y2 JPH0514519 Y2 JP H0514519Y2 JP 1988114737 U JP1988114737 U JP 1988114737U JP 11473788 U JP11473788 U JP 11473788U JP H0514519 Y2 JPH0514519 Y2 JP H0514519Y2
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- ceramic substrate
- gate electrode
- semiconductor
- semiconductor element
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
- Wire Bonding (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1988114737U JPH0514519Y2 (en:Method) | 1988-08-30 | 1988-08-30 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1988114737U JPH0514519Y2 (en:Method) | 1988-08-30 | 1988-08-30 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0235453U JPH0235453U (en:Method) | 1990-03-07 |
| JPH0514519Y2 true JPH0514519Y2 (en:Method) | 1993-04-19 |
Family
ID=31355761
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1988114737U Expired - Lifetime JPH0514519Y2 (en:Method) | 1988-08-30 | 1988-08-30 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0514519Y2 (en:Method) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE19950026B4 (de) * | 1999-10-09 | 2010-11-11 | Robert Bosch Gmbh | Leistungshalbleitermodul |
| JP4626445B2 (ja) * | 2004-08-24 | 2011-02-09 | ソニー株式会社 | 半導体パッケージの製造方法 |
| JP5239736B2 (ja) * | 2008-10-22 | 2013-07-17 | 株式会社デンソー | 電子装置 |
| US9706643B2 (en) * | 2014-06-19 | 2017-07-11 | Panasonic Intellectual Property Management Co., Ltd. | Electronic device and method for manufacturing the same |
-
1988
- 1988-08-30 JP JP1988114737U patent/JPH0514519Y2/ja not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0235453U (en:Method) | 1990-03-07 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5902959A (en) | Lead frame with waffled front and rear surfaces | |
| US11972997B2 (en) | Semiconductor device | |
| KR20090056594A (ko) | 온도 감지소자가 장착된 반도체 파워 모듈 패키지 및 그제조방법 | |
| JP2504610B2 (ja) | 電力用半導体装置 | |
| JPS59141249A (ja) | 電力チツプ・パツケ−ジ | |
| JPH0770641B2 (ja) | 半導体パッケージ | |
| JPH0629459A (ja) | 半導体装置およびその製造方法 | |
| WO2005119896A1 (ja) | インバータ装置 | |
| JPH0514519Y2 (en:Method) | ||
| JPH09321216A (ja) | 電力用半導体装置 | |
| JP4409064B2 (ja) | パワー素子を含む半導体装置 | |
| JPH0418694B2 (en:Method) | ||
| US6975513B2 (en) | Construction for high density power module package | |
| JPH04249353A (ja) | 樹脂封止型半導体装置 | |
| JPH0382060A (ja) | 半導体装置 | |
| JPS63190363A (ja) | パワ−パツケ−ジ | |
| KR100244826B1 (ko) | 반도체장치 및 그 제조방법 | |
| JP7147186B2 (ja) | 半導体装置 | |
| CN116913792B (zh) | 一种双面散热封装模块及制作方法 | |
| JP2022139064A (ja) | 半導体モジュール | |
| JP4258411B2 (ja) | 半導体装置 | |
| JPH03191554A (ja) | 半導体装置 | |
| JP2003347507A (ja) | 半導体パワーデバイス | |
| JPS59152654A (ja) | 絶縁形半導体装置 | |
| JPH03256351A (ja) | 半導体装置 |