JPH0514519Y2 - - Google Patents
Info
- Publication number
- JPH0514519Y2 JPH0514519Y2 JP11473788U JP11473788U JPH0514519Y2 JP H0514519 Y2 JPH0514519 Y2 JP H0514519Y2 JP 11473788 U JP11473788 U JP 11473788U JP 11473788 U JP11473788 U JP 11473788U JP H0514519 Y2 JPH0514519 Y2 JP H0514519Y2
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- ceramic substrate
- gate electrode
- semiconductor
- semiconductor element
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 claims description 41
- 239000000919 ceramic Substances 0.000 claims description 17
- 239000000758 substrate Substances 0.000 claims description 17
- 229910052751 metal Inorganic materials 0.000 claims description 10
- 239000002184 metal Substances 0.000 claims description 10
- 239000011347 resin Substances 0.000 claims description 6
- 229920005989 resin Polymers 0.000 claims description 6
- 238000005476 soldering Methods 0.000 claims description 4
- 238000000605 extraction Methods 0.000 claims description 2
- 238000000465 moulding Methods 0.000 claims description 2
- 238000005516 engineering process Methods 0.000 description 4
- 239000004020 conductor Substances 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000004806 packaging method and process Methods 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- 229910000881 Cu alloy Inorganic materials 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 239000003566 sealing material Substances 0.000 description 1
- 230000035939 shock Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
Description
【考案の詳細な説明】
イ 考案の目的
〔産業上の利用分野〕
本考案は、電力用半導体モジユールの構造に関
するものである。[Detailed Description of the Invention] A. Purpose of the Invention [Field of Industrial Application] The present invention relates to the structure of a power semiconductor module.
従来、この種の複数個の半導体素子を組合せ、
電力用半導体モールドモジユールを構成するとき
は、第２図に示すように、金属製基台８の上に、
複数の高熱伝導特性を持つセラミツクス基板を置
き、セラミツクス基板に半導体素子５と、外部導
体へ接続するドレーン電極２、ソース電極３、ゲ
ート電極４と、ソース電極ワイヤ６、ゲート電極
ワイヤ７により電極間を接続し、モールド樹脂９
の封止材より全体を封止し構成されている。第２
図に示す従来の技術では、半導体素子が平板状に
配置されているためソース電極３と半導体素子５
のソース側はソース電極ワイヤ６により接続され
ており、ワイヤの太さによりソース電流容量、即
ちドレーン電流が制限されてしまう。又、電流容
量を増すためにワイヤの数を増やすためワイヤボ
ンデイングの数を増やす必要があり、ワイヤボン
デイングは半導体素子に衝撃を与え、半導体素子
に欠陥を生ずる原因となる欠点があつた。
Conventionally, multiple semiconductor elements of this type were combined,
When constructing a power semiconductor mold module, as shown in FIG.
A plurality of ceramic substrates having high thermal conductivity are placed, and a semiconductor element 5 is placed on the ceramic substrate, a drain electrode 2, a source electrode 3, a gate electrode 4 are connected to the external conductor, and a source electrode wire 6 and a gate electrode wire 7 are used to connect the electrodes. Connect the mold resin 9
The entire structure is sealed with a sealing material. Second
In the conventional technology shown in the figure, since the semiconductor elements are arranged in a flat plate, the source electrode 3 and the semiconductor element 5
The source side of is connected by a source electrode wire 6, and the thickness of the wire limits the source current capacity, that is, the drain current. Furthermore, in order to increase the current capacity, it is necessary to increase the number of wire bondings to increase the number of wires, and wire bonding has the disadvantage that it gives a shock to the semiconductor element, causing defects in the semiconductor element.
本考案は、外部導体へ接続する電極と電流容量
の大きい半導体素子との接続に、半導体素子のソ
ースとドレーンと外部接続電極との間にワイヤボ
ンデイングを使用せず、電極と半導体素子とを面
接続となるよう配置し、実装密度が大きく、モジ
ユール組み立て作業の省略化を計り、電流容量の
大きい、高信頼性、高密度実装の大電力モジユー
ルとする。
The present invention does not use wire bonding between the source and drain of the semiconductor element and the external connection electrode to connect the electrode connected to the external conductor and the semiconductor element with a large current capacity, but instead connects the electrode and the semiconductor element face-to-face. The module is arranged so as to be connected, has a high packaging density, and simplifies module assembly work, resulting in a high-power module with high current capacity, high reliability, and high-density packaging.
ロ 考案の構成
〔課題を解決するための手段〕
半導体素子と外部導体へ導出する電極を立体的
に配置し、電流容量の大きいソース電極、ドレー
ン電極と半導体素子との間は、面接続構造で半田
接続とし、ワイヤボンデイングはゲート電極と半
導体素子の間のみとした。B. Structure of the invention [Means for solving the problem] The semiconductor element and the electrode leading to the external conductor are arranged three-dimensionally, and a surface connection structure is used between the source electrode and drain electrode, which have a large current capacity, and the semiconductor element. The connection was made by soldering, and wire bonding was performed only between the gate electrode and the semiconductor element.
即ち本考案は、複数の偶数個の半導体素子を組
合せ構成する電力用半導体モールドモジユールに
おいて半導体素子のドレーン・ソース面に外部導
出のため電極を半田接続し、ドレーン電極とゲー
ト電極とは金属製基台に裏張りされた熱伝導セラ
ミツクス基板に半田接続し、ゲート電極は半導体
素子とワイヤボンデイングにより接続し、ソース
電極を熱伝導セラミツクス基板を介し対向して配
置し、外部と接続する導出電極部分を除き一体に
樹脂モールドしたことを特徴とする電力用半導体
モールドモジユールである。 That is, in the present invention, in a power semiconductor mold module configured by combining a plurality of even number of semiconductor elements, electrodes are soldered to the drain and source surfaces of the semiconductor elements for external extraction, and the drain electrode and gate electrode are made of metal. The lead-out electrode part is connected to the heat conductive ceramic substrate lined with the base by soldering, the gate electrode is connected to the semiconductor element by wire bonding, the source electrode is placed facing each other through the heat conductive ceramic substrate, and is connected to the outside. This is a power semiconductor mold module characterized by being integrally molded with resin except for.
外側両側に半導体素子を搭載した熱伝導体のセ
ラミツクス基板を取り付けた金属製基台８を半導
体素子を向き合わせ、中央に熱伝導性のある、又
電気絶縁性のセラミツクス基板を置き配置し、半
導体素子に接続するソース・ドレーン側外部導出
用電極は、半導体素子のソース・ドレーン電極と
は半田接続としてあるため電流容量は従来の技術
のワイヤボンデイングの際のように制限を受ける
ことはなく、また半導体素子、電極が立体的に配
置されるため電力用半導体モールドモジユールは
小形に実装される。
A metal base 8 with heat conductive ceramic substrates mounted with semiconductor elements mounted on both outer sides is placed with the semiconductor elements facing each other, and a thermally conductive or electrically insulating ceramic substrate is placed in the center. The external lead electrodes on the source/drain side connected to the element are connected to the source/drain electrodes of the semiconductor element by solder, so the current capacity is not limited as in the case of wire bonding in the conventional technology. Since the semiconductor elements and electrodes are arranged three-dimensionally, the power semiconductor mold module can be mounted in a small size.
本考案は、高熱伝導セラミツクス基板を用い、
その両面に金属板を半田接続し、それぞれの面に
半導体素子を取り付けた構造に組合せ樹脂モール
ドしたもので、半導体素子に直接接続した金属板
をそのまま供電用端子として使用することを特徴
とする。
This invention uses a high thermal conductivity ceramic substrate,
A metal plate is connected to both sides by soldering, and a semiconductor element is attached to each side by resin molding.The metal plate directly connected to the semiconductor element can be used as a power supply terminal as it is.
第１図は本考案による大電力モールドモジユー
ルを示す。第１図ｂはその平面図を示すが、外側
両側には銅、又はアルミニウムからなる金属製基
台８と、金属製基台８上にはアルミナ等の高熱伝
導セラミツクス基板１、高熱伝導セラミツクス基
板上には表面に半田メツキした銅板、又は銅合金
板よりなるドレーン電極２、ゲート電極４を、ド
レーン電極２上には半導体素子５が搭載されてお
り、半導体素子のソース側にはソース電極を面接
続し、半導体素子とゲート電極との間はワイヤに
より接続する。これらの電力用半導体モジユール
は、中央に高熱伝導セラミツクス基板１１（以下
セラミツクス基板と称す）を置き、セラミツクス
基板１１をはさんで左右対称に配置され、セラミ
ツクス基板１１とソース電極間は半田接続され
る。第１図ｃは側面図を示すが、ドレーン電極
２、ゲート電極４、ソース電極３は上方に延ばさ
れ、金属製基台８とセラミツクス基板１１との間
はモールド樹脂９によりモールドし、金属製基台
８の外側は外枠１０により保持され、また本考案
の構成によつて半導体素子５の高密度実装が可能
となる。本考案の実施例では半導体素子を４個実
装して、20mm×37mm×84mmの容積の大電力モール
ドモジユールが作製出来る。従来の技術では半導
体を２個実装して、15mm×37mm×84mmの容積であ
る。 FIG. 1 shows a high power molded module according to the present invention. FIG. 1b shows a plan view of the same. On both sides of the outside there is a metal base 8 made of copper or aluminum, and on the metal base 8 there are a high heat conductive ceramic substrate 1 made of alumina or the like, and a high heat conductive ceramic substrate 1. A drain electrode 2 and a gate electrode 4 made of a copper plate or a copper alloy plate whose surface is soldered are mounted on the top, a semiconductor element 5 is mounted on the drain electrode 2, and a source electrode is mounted on the source side of the semiconductor element. Surface connection is made, and the semiconductor element and the gate electrode are connected by a wire. These power semiconductor modules have a highly thermally conductive ceramic substrate 11 (hereinafter referred to as a ceramic substrate) placed in the center, are arranged symmetrically with the ceramic substrate 11 in between, and are connected by solder between the ceramic substrate 11 and the source electrode. . FIG. 1c shows a side view, and the drain electrode 2, gate electrode 4, and source electrode 3 are extended upward, and the space between the metal base 8 and the ceramic substrate 11 is molded with mold resin 9, and the metal The outer side of the base 8 is held by an outer frame 10, and the structure of the present invention enables high-density mounting of the semiconductor elements 5. In the embodiment of the present invention, a high-power mold module with a volume of 20 mm x 37 mm x 84 mm can be manufactured by mounting four semiconductor elements. In the conventional technology, two semiconductors are mounted and the volume is 15 mm x 37 mm x 84 mm.
ハ 考案の効果
以上述べたごとく、本考案によれば、半導体素
子と電極の接続に関して高信頼性を有し、従来の
ものよりも高密度実装が可能な電力用半導体モー
ルドモジユールの提供が可能となつた。C. Effects of the invention As described above, according to the invention, it is possible to provide a power semiconductor mold module that has high reliability in connection between semiconductor elements and electrodes and can be mounted at a higher density than conventional ones. It became.
第１図は本考案による電力用モールドモジユー
ルの構造を示す図で、ａは正面図、ｂは平面図、
ｃは側面図。第２図は従来の電力用モールドモジ
ユールの構造を示す図でａは正面図、ｂは平面
図、ｃは側面図。
１，１１……高熱伝導セラミツクス基板、２…
…ドレーン電極、３……ソース電極、４……ゲー
ト電極、５……半導体素子、６……ソース電極ワ
イヤ、７……ゲート電極ワイヤ、８……金属製基
台、９……モールド樹脂、１０……外枠。
FIG. 1 is a diagram showing the structure of a power mold module according to the present invention, in which a is a front view, b is a plan view,
c is a side view. FIG. 2 is a diagram showing the structure of a conventional power mold module, in which a is a front view, b is a plan view, and c is a side view. 1, 11...High thermal conductivity ceramic substrate, 2...
... drain electrode, 3 ... source electrode, 4 ... gate electrode, 5 ... semiconductor element, 6 ... source electrode wire, 7 ... gate electrode wire, 8 ... metal base, 9 ... mold resin, 10... Outer frame.
Claims (1)
力用半導体モールドモジユールにおいて半導体素
子のドレーン・ソース面に外部導出のための電極
を半田接続し、ドレーン電極とゲート電極とは金
属製基台に裏張りされた熱伝導セラミツクス基板
に半田接続し、ゲート電極は半導体素子とワイヤ
ボンデイングにより接続し、ソース電極を熱伝導
セラミツクス基板を介し対向して配置し、外部と
接続する導出電極部分を除き一体に樹脂モールド
したことを特徴とする電力用半導体モールドモジ
ユール。 In a power semiconductor mold module configured by combining a plurality of even number of semiconductor elements, electrodes for external extraction are soldered to the drain and source surfaces of the semiconductor elements, and the drain electrode and gate electrode are placed on the back side of a metal base. The gate electrode is connected by soldering to a stretched thermally conductive ceramic substrate, the gate electrode is connected to the semiconductor element by wire bonding, and the source electrode is placed facing each other with the thermally conductive ceramic substrate interposed in between. A power semiconductor mold module characterized by resin molding.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11473788U JPH0514519Y2 (en) | 1988-08-30 | 1988-08-30 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11473788U JPH0514519Y2 (en) | 1988-08-30 | 1988-08-30 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0235453U JPH0235453U (en) | 1990-03-07 |
| JPH0514519Y2 true JPH0514519Y2 (en) | 1993-04-19 |
Family
ID=31355761
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11473788U Expired - Lifetime JPH0514519Y2 (en) | 1988-08-30 | 1988-08-30 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0514519Y2 (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE19950026B4 (en) * | 1999-10-09 | 2010-11-11 | Robert Bosch Gmbh | The power semiconductor module |
| JP4626445B2 (en) * | 2004-08-24 | 2011-02-09 | ソニー株式会社 | Manufacturing method of semiconductor package |
| JP5239736B2 (en) * | 2008-10-22 | 2013-07-17 | 株式会社デンソー | Electronic equipment |
| US9706643B2 (en) * | 2014-06-19 | 2017-07-11 | Panasonic Intellectual Property Management Co., Ltd. | Electronic device and method for manufacturing the same |
-
1988
- 1988-08-30 JP JP11473788U patent/JPH0514519Y2/ja not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0235453U (en) | 1990-03-07 |
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