JPH09260557A - Semiconductor device and its manufacture - Google Patents

Semiconductor device and its manufacture

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Publication number
JPH09260557A
JPH09260557A JP6237696A JP6237696A JPH09260557A JP H09260557 A JPH09260557 A JP H09260557A JP 6237696 A JP6237696 A JP 6237696A JP 6237696 A JP6237696 A JP 6237696A JP H09260557 A JPH09260557 A JP H09260557A
Authority
JP
Japan
Prior art keywords
common electrode
semiconductor device
plate
insulating substrate
electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6237696A
Other languages
Japanese (ja)
Inventor
Masanori Saotome
全紀 早乙女
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Original Assignee
Fuji Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Co Ltd filed Critical Fuji Electric Co Ltd
Priority to JP6237696A priority Critical patent/JPH09260557A/en
Publication of JPH09260557A publication Critical patent/JPH09260557A/en
Pending legal-status Critical Current

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  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Thyristors (AREA)

Abstract

PROBLEM TO BE SOLVED: To electrically insulate a semiconductor device from a cooling body, and improve the heat radiation, with a flat IGBT(insulated gate bipolar transistor). SOLUTION: A solder sheet 7, a metallic plate 5 for takeout of currents, a solder sheet 7, and an insulating substrate 6 are stacked on the emitter terminal 2 of a flat IBGT 1. Likewise, also on the collector terminal side 3, a solder sheet 7, a metallic plate 5 for takeout of currents, a solder sheet 7, and an insulating substrate 6 are stacked. The insulating board 6 is pressed with a flat press not shown in the figure, and the solder sheet 7 is fused by heating these parts and then is cooled to solder each part. The insulating board 6 is manufactured by covering both sides of an insulating board 10 such as an alumina plate, an aluminum nitride plate, etc., with metallic films 11. By constituting it this way, the flat IGBT 1 is insulated electrically from the cooling body not shown in the figure, but thermally good conductivity can be secured.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】この発明は、絶縁ゲート型バ
イポーラトランジスタ(IGBT)などのパワーデバイ
スを対象に、基板の一主面に第主電極(エミッタ)と制
御電極(ゲート)、別の主面に第二主電極(コレクタ)
を有する半導体チップの複数個を同一のパッケージ内に
組み込みんだ半導体装置およびその製造方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is intended for a power device such as an insulated gate bipolar transistor (IGBT) and the like. A main electrode (emitter) and a control electrode (gate) are provided on one main surface of a substrate, and another main surface is provided. On the second main electrode (collector)
The present invention relates to a semiconductor device in which a plurality of semiconductor chips having the above are incorporated in the same package, and a manufacturing method thereof.

【0002】[0002]

【従来の技術】従来のサイリスタやGTOと同等のセラ
ミックパッケージに実装した加圧接触形の平形IGBT
が提案されている。この平形IGBTはGTO等と違
い、加圧面がMOS構造となるため、初期特性および長
期信頼性を確保するために、ゲート電極などのMOS部
を加圧しない配慮が必要である。そのため、ゲート電極
が形成されていない領域に冷却と通電を兼ねた集電電極
を設けて、この集電電極をコンタクト端子体とパッケー
ジ側の共通電極板とを介して外部から加圧する構造とし
ている。この共通電極板は冷却体で加圧され、負荷電流
をIGBTチップに流し、IGBTチップで発生した熱
を放散させている。
2. Description of the Related Art A pressure contact type flat IGBT mounted in a ceramic package equivalent to a conventional thyristor or GTO.
Has been proposed. Unlike the GTO and the like, the flat IGBT has a MOS structure on the pressing surface, and therefore, in order to ensure initial characteristics and long-term reliability, it is necessary to consider not pressing the MOS portion such as the gate electrode. Therefore, a structure is provided in which a collector electrode for both cooling and energization is provided in a region where the gate electrode is not formed, and the collector electrode is externally pressed through the contact terminal body and the common electrode plate on the package side. . This common electrode plate is pressurized by a cooling body, a load current is passed through the IGBT chip, and heat generated in the IGBT chip is dissipated.

【0003】[0003]

【発明が解決しようとする課題】しかし、インバータや
コンバータに半導体装置を用いる場合、冷却体と半導体
装置とを熱放散は良好であるが電気的には絶縁した方が
使用し易い場合が多い。従来の平形IGBTは共通電極
板から冷却体に電流を流すため、共通電極板と冷却体と
は電気的にも熱的にも絶縁されていない。そのため、使
い勝手が悪い半導体装置となっていた。
However, when a semiconductor device is used in an inverter or a converter, it is often easier to use the electrically insulating material if the cooling body and the semiconductor device have good heat dissipation. In the conventional flat IGBT, a current flows from the common electrode plate to the cooling body, so that the common electrode plate and the cooling body are not electrically or thermally insulated from each other. Therefore, the semiconductor device is not easy to use.

【0004】この発明の目的は、前記の課題を解決し、
冷却体と共通電極板の間を熱伝導はよいが電気的には絶
縁されている平形の半導体装置を提供することにある。
The object of the present invention is to solve the above problems,
It is an object of the present invention to provide a flat semiconductor device in which heat conduction between the cooling body and the common electrode plate is good but electrically insulated.

【0005】[0005]

【課題を解決するための手段】前記の目的を達成するた
めに、第一主面に第一主電極と制御電極を、第二主面に
第二主電極をそれぞれ有するMOS構造の半導体チップ
を複数個並置して、両面が露出する一対の共通電極板の
間に絶縁外筒を介装してなる平形パッケージに組み込
み、該半導体チップの第一主電極とこれに対向する一方
のパッケージ側の共通電極板との間に加圧、導電、放熱
を兼ねたコンタクト端子体を介装し、他方のパッケージ
側の共通電極板上に第二主電極が固着される半導体装置
において、両共通電極板の露出面上に絶縁基板が固着さ
れる構成とする。両共通電極板と絶縁板との間に電流取
り出し用金属板を挟み、且つ、固着してもよい。この絶
縁基板がアルミナ(Al2 3 )または窒化アルミニウ
ム(NAl)で形成されるとよい。また絶縁基板の外周
部に絶縁環を設けると効果的である。前記のMOS構造
の半導体チップが絶縁ゲート型バイポーラトランジス
タ、MOS制御サイリスタまたはMOSトランジスタで
あり、同一の平形パッケージ内にMOS構造の半導体チ
ップと並置してフリーホイールダイオードを組み込み、
一方のパッケージ側の共通電極とフリーホイールダイオ
ードとの間に加圧、導電、放熱を兼ねたコンタクト端子
体を具備するとよい。
In order to achieve the above object, a semiconductor chip of MOS structure having a first main electrode and a control electrode on a first main surface and a second main electrode on a second main surface is provided. A plurality of juxtaposed devices are mounted in a flat package having a pair of common electrode plates with both surfaces exposed and an insulating outer tube interposed therebetween, and the first main electrode of the semiconductor chip and the common electrode on the side of one package facing the first main electrode. Exposure of both common electrode plates in a semiconductor device in which a contact terminal body that also functions as pressure, conductivity, and heat dissipation is interposed between the plate and the second main electrode is fixed on the common electrode plate on the other package side. An insulating substrate is fixed on the surface. A current extraction metal plate may be sandwiched and fixed between both common electrode plates and the insulating plate. This insulating substrate is preferably made of alumina (Al 2 O 3 ) or aluminum nitride (NAl). Further, it is effective to provide an insulating ring on the outer peripheral portion of the insulating substrate. The semiconductor chip of the MOS structure is an insulated gate bipolar transistor, a MOS control thyristor or a MOS transistor, and a free wheel diode is incorporated side by side with the semiconductor chip of the MOS structure in the same flat package,
It is preferable to provide a contact terminal body that also serves as pressure, conductivity, and heat dissipation between the common electrode on one package side and the free wheel diode.

【0006】前記の半導体装置の製造方法として、絶縁
基板と共通電極板または絶縁基板と電流取り出し用金属
板と共通電極板とに挟まれたそれぞれのはんだが平坦な
プレスで加圧され、且つ、加熱されて溶融し、冷却によ
り絶縁基板と共通電極板とをはんだ接合する方法がよ
い。前記の構成のように、電流取り出し用金属板を設け
ることで、この金属板の表面に熱伝導のよいアルミナ板
や窒化アルミニウム板などで構成された絶縁基板を平坦
なプレスで加圧しながら加熱・冷却し、はんだ付けする
ことで、冷却体とIGBTとを電気的絶縁を確保するこ
とができ、またこの構成により、冷却体と接触する絶縁
基板の露出表面を平坦化でき、IGBTで発生した熱を
スムーズに冷却体に放散できる。
As a method of manufacturing the semiconductor device, each solder sandwiched between the insulating substrate and the common electrode plate or between the insulating substrate, the current extracting metal plate and the common electrode plate is pressed by a flat press, and A method is preferable in which the insulating substrate and the common electrode plate are solder-bonded by being heated and melted and then cooled. By providing a metal plate for current extraction as in the above configuration, an insulating substrate made of an alumina plate or an aluminum nitride plate having good thermal conductivity is heated on the surface of the metal plate while pressing it with a flat press. By cooling and soldering, it is possible to ensure electrical insulation between the cooling body and the IGBT, and with this configuration, the exposed surface of the insulating substrate that contacts the cooling body can be flattened, and the heat generated by the IGBT Can be smoothly dissipated to the cooling body.

【0007】[0007]

【発明の実施の形態】図1はこの発明の第1実施例の要
部構成図で、同図(a)は各部品を分解した状態の図
で、同図(a)は完成品の側面図である。図1におい
て、平形IGBT1のエミッタ端子2(一方の共通電極
板のこと)上にはんだシート7、電流取り出し用金属板
5、はんだシート7、絶縁基板6を積層する。同様にコ
レクタ端子3(他方の共通電極板のこと)側もはんだシ
ート7、電流取り出し用金属板5、はんだシート7、絶
縁基板6が積層される。絶縁基板6を図示されていない
平坦なプレスで加圧し、これらの部品を加熱してはんだ
シート7を溶融させ、冷却して、各部品をはんだ付けす
る。絶縁基板6はアルミナ板や窒化アルミニウム板など
の絶縁板10(熱的には良伝導体)の両面に金属膜11
を被覆して製作されている。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a schematic view of the essential parts of a first embodiment of the present invention, in which FIG. 1 (a) is an exploded view of each part and FIG. 1 (a) is a side view of a finished product. It is a figure. In FIG. 1, a solder sheet 7, a current extracting metal plate 5, a solder sheet 7, and an insulating substrate 6 are laminated on an emitter terminal 2 (one common electrode plate) of a flat IGBT 1. Similarly, on the collector terminal 3 (the other common electrode plate) side, the solder sheet 7, the current extracting metal plate 5, the solder sheet 7, and the insulating substrate 6 are laminated. The insulating substrate 6 is pressed by a flat press (not shown), these components are heated to melt the solder sheet 7, and cooled to solder each component. The insulating substrate 6 has a metal film 11 on both sides of an insulating plate 10 (thermally good conductor) such as an alumina plate or an aluminum nitride plate.
It is manufactured by coating.

【0008】図2は平形IGBTの外観図で、同図
(a)は平面図、同図(b)は側面図である。図2にお
いて、セラミックでできた絶縁筒9(通称セラミックケ
ースともいう)にエミッタ端子2、コレクタ端子3、ゲ
ート端子4が溶接されている。絶縁筒9内に図示されて
いない半導体チップやコンタクト端子体が収納されてい
る。
FIG. 2 is an external view of the flat IGBT, FIG. 2 (a) is a plan view, and FIG. 2 (b) is a side view. In FIG. 2, an emitter terminal 2, a collector terminal 3, and a gate terminal 4 are welded to an insulating cylinder 9 (also called a ceramic case) made of ceramic. A semiconductor chip and a contact terminal body (not shown) are housed in the insulating cylinder 9.

【0009】図3は電流取り出し用金属板の構成図で、
同図(a)は平面図、同図(b)は側面図である。図3
において、外部回路と接続する電流端子5aが電流取り
出し用金属板5の側面に設けられている。また電流端子
5aには取り付け孔5bが開いている。この電流端子5
aは平形IGBT1のエミッタ端子2、コレクタ端子3
に設けて、この電流取り出し用金属板5を構成から省く
ことも可能である。
FIG. 3 is a block diagram of a metal plate for extracting electric current.
FIG. 1A is a plan view, and FIG. 1B is a side view. FIG.
In, the current terminal 5a connected to the external circuit is provided on the side surface of the current extraction metal plate 5. A mounting hole 5b is opened in the current terminal 5a. This current terminal 5
a is an emitter terminal 2 and a collector terminal 3 of the flat IGBT 1.
It is also possible to dispose the metal plate 5 for current extraction in the structure by omitting it from the configuration.

【0010】図4は絶縁基板の構造図で、同図(a)は
平面図、同図(b)は側面図である。図4において、絶
縁基板6は熱伝導性が良く、電気的絶縁性に優れたアル
ミナ板や窒化アルミニウム板などの絶縁板10の両面に
金属膜11を被覆した構成となっている。図5はこの発
明の第2実施例の側面図を示す。絶縁基板6を構成する
絶縁板10の周囲に絶縁環8を設けて、図示されていな
い冷却体に挟まれた絶縁基板6を含む平形IGBT1の
沿面距離を長くすることで、平形IGBT1の沿面放電
を防止する。
4A and 4B are structural views of the insulating substrate. FIG. 4A is a plan view and FIG. 4B is a side view. In FIG. 4, the insulating substrate 6 has a structure in which a metal film 11 is coated on both surfaces of an insulating plate 10 such as an alumina plate or an aluminum nitride plate having good thermal conductivity and excellent electric insulation. FIG. 5 shows a side view of the second embodiment of the present invention. By providing the insulating ring 8 around the insulating plate 10 forming the insulating substrate 6 and increasing the creeping distance of the flat IGBT 1 including the insulating substrate 6 sandwiched between the cooling bodies (not shown), the creeping discharge of the flat IGBT 1 Prevent.

【図面の簡単な説明】[Brief description of drawings]

【図1】図1はこの発明の第1実施例の要部構成図で、
(a)は各部品を分解した状態の図で、(b)は完成品
の側面図
FIG. 1 is a configuration diagram of a main part of a first embodiment of the present invention,
(A) is a view of each part disassembled, (b) is a side view of the finished product

【図2】平形IGBTの外観図で、(a)は平面図、
(b)は側面図
FIG. 2 is an external view of a flat IGBT, (a) is a plan view,
(B) is a side view

【図3】電流取り出し用金属板の構成図で、(a)は平
面図、(b)は側面図
FIG. 3 is a configuration diagram of a metal plate for current extraction, (a) is a plan view and (b) is a side view.

【図4】絶縁基板の構造図で、(a)は平面図、(b)
は側面図
4A and 4B are structural views of an insulating substrate, where FIG. 4A is a plan view and FIG.
Is a side view

【図5】この発明の第2実施例の側面図FIG. 5 is a side view of the second embodiment of the present invention.

【符号の説明】[Explanation of symbols]

1 平形IGBT 2 エミッタ端子 3 コレクタ端子 4 ゲート端子 5 電流取り出し用金属板 5a 電流端子 5b 取り付け孔 6 絶縁基板 7 はんだシート 8 絶縁環 9 絶縁筒 10 絶縁板 11 金属膜 1 Flat IGBT 2 Emitter Terminal 3 Collector Terminal 4 Gate Terminal 5 Current Extraction Metal Plate 5a Current Terminal 5b Mounting Hole 6 Insulating Substrate 7 Solder Sheet 8 Insulation Ring 9 Insulation Tube 10 Insulation Plate 11 Metal Film

Claims (6)

【特許請求の範囲】[Claims] 【請求項1】第一主面に第一主電極と制御電極を、第二
主面に第二主電極をそれぞれ有するMOS構造の半導体
チップを複数個並置して、両面が露出する一対の共通電
極板の間に絶縁外筒を介装してなる平形パッケージに組
み込み、該半導体チップの第一主電極とこれに対向する
一方のパッケージ側の共通電極板との間に加圧、導電、
放熱を兼ねたコンタクト端子体を介装し、他方のパッケ
ージ側の共通電極板上に第二主電極が固着される半導体
装置において、両共通電極板の露出面上に絶縁基板が固
着されることを特徴とする半導体装置。
1. A pair of common semiconductor chips having a first main electrode and a control electrode on a first main surface and a plurality of MOS structure semiconductor chips each having a second main electrode on a second main surface, which are arranged side by side. Built in a flat package having an insulating outer tube interposed between the electrode plates, pressure, conduction, between the first main electrode of the semiconductor chip and the common electrode plate on the one package side facing the first main electrode.
In a semiconductor device in which a contact terminal that also serves as heat dissipation is interposed and a second main electrode is fixed on the common electrode plate on the other package side, an insulating substrate is fixed on the exposed surface of both common electrode plates. A semiconductor device characterized by:
【請求項2】両共通電極板の露出面上に電流取り出し用
金属板と絶縁基板が固着されることを特徴とする請求項
1記載の半導体装置。
2. The semiconductor device according to claim 1, wherein the current extracting metal plate and the insulating substrate are fixed on the exposed surfaces of both common electrode plates.
【請求項3】絶縁基板の外周部に絶縁環が設けられたこ
とを特徴とする請求項1記載の半導体装置。
3. The semiconductor device according to claim 1, wherein an insulating ring is provided on an outer peripheral portion of the insulating substrate.
【請求項4】絶縁基板がアルミナ(Al2 3 )または
窒化アルミニウム(NAl)で形成されることを特徴と
する請求項1記載の半導体装置。
4. The semiconductor device according to claim 1, wherein the insulating substrate is made of alumina (Al 2 O 3 ) or aluminum nitride (NAl).
【請求項5】MOS構造の半導体チップが絶縁ゲート型
バイポーラトランジスタ、MOS制御サイリスタまたは
MOSトランジスタであり、同一の平形パッケージ内に
MOS構造の半導体チップと並置してフリーホイールダ
イオードを組み込み、一方のパッケージ側の共通電極と
フリーホイールダイオードとの間に加圧、導電、放熱を
兼ねたコンタクト端子体を具備することを特徴とする請
求項1記載の半導体装置。
5. A semiconductor chip having a MOS structure is an insulated gate bipolar transistor, a MOS control thyristor or a MOS transistor, and a freewheel diode is incorporated in parallel with the semiconductor chip having a MOS structure in the same flat package, and one package is provided. 2. The semiconductor device according to claim 1, further comprising: a contact terminal body that also serves as a pressurizing member, a conductive member, and a heat sink between the common electrode on the side and the free wheel diode.
【請求項6】第一主面に第一主電極と制御電極を、第二
主面に第二主電極をそれぞれ有するMOS構造の半導体
チップを複数個並置して、両面が露出する一対の共通電
極板の間に絶縁外筒を介装してなる平形パッケージに組
み込み、該半導体チップの第一主電極とこれに対向する
一方のパッケージ側の共通電極板との間に加圧、導電、
放熱を兼ねたコンタクト端子体を介装し、他方のパッケ
ージ側の共通電極板上に第二主電極が固着される半導体
装置において、両共通電極板の側面に外部導出端子がそ
れぞれに設けられ、且つ、両共通電極板の露出面上に絶
縁基板が固着される半導体装置にあって、絶縁基板と共
通電極板または絶縁板と電流取り出し用金属板と共通電
極板とに挟まれたそれぞれのはんだが平坦なプレスで加
圧され、且つ、加熱されて溶融し、冷却により絶縁基板
と共通電極板とがはんだ接合する半導体装置の製造方
法。
6. A pair of common semiconductor chips, each having a first main electrode and a control electrode on the first main surface and a plurality of MOS structure semiconductor chips each having a second main electrode on the second main surface, arranged side by side to expose both surfaces. Built in a flat package having an insulating outer tube interposed between the electrode plates, pressure, conduction, between the first main electrode of the semiconductor chip and the common electrode plate on the one package side facing the first main electrode.
In a semiconductor device in which a contact terminal that also serves as heat dissipation is interposed and a second main electrode is fixed to the common electrode plate on the other package side, external lead terminals are provided on the side surfaces of both common electrode plates, Further, in a semiconductor device in which an insulating substrate is fixed on the exposed surfaces of both common electrode plates, each solder sandwiched between the insulating substrate and the common electrode plate or between the insulating plate, the current extraction metal plate and the common electrode plate. Is a method of manufacturing a semiconductor device in which the insulating substrate and the common electrode plate are solder-joined by being pressed by a flat press, heated and melted, and cooled.
JP6237696A 1996-03-19 1996-03-19 Semiconductor device and its manufacture Pending JPH09260557A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6237696A JPH09260557A (en) 1996-03-19 1996-03-19 Semiconductor device and its manufacture

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6237696A JPH09260557A (en) 1996-03-19 1996-03-19 Semiconductor device and its manufacture

Publications (1)

Publication Number Publication Date
JPH09260557A true JPH09260557A (en) 1997-10-03

Family

ID=13198344

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6237696A Pending JPH09260557A (en) 1996-03-19 1996-03-19 Semiconductor device and its manufacture

Country Status (1)

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JP (1) JPH09260557A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006066465A (en) * 2004-08-24 2006-03-09 Toyota Industries Corp Semiconductor device
JP2012028401A (en) * 2010-07-20 2012-02-09 Denso Corp Semiconductor device
JP2012028400A (en) * 2010-07-20 2012-02-09 Denso Corp Semiconductor device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006066465A (en) * 2004-08-24 2006-03-09 Toyota Industries Corp Semiconductor device
JP2012028401A (en) * 2010-07-20 2012-02-09 Denso Corp Semiconductor device
JP2012028400A (en) * 2010-07-20 2012-02-09 Denso Corp Semiconductor device

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