JPH05144882A - Film carrier for semiconductor device - Google Patents

Film carrier for semiconductor device

Info

Publication number
JPH05144882A
JPH05144882A JP32950391A JP32950391A JPH05144882A JP H05144882 A JPH05144882 A JP H05144882A JP 32950391 A JP32950391 A JP 32950391A JP 32950391 A JP32950391 A JP 32950391A JP H05144882 A JPH05144882 A JP H05144882A
Authority
JP
Japan
Prior art keywords
film
thickness
lead portion
insulating film
weight
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP32950391A
Other languages
Japanese (ja)
Inventor
Osamu Yoshioka
修 吉岡
Norio Okabe
則夫 岡部
Hiromichi Suzuki
博通 鈴木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Cable Ltd
Hitachi Ltd
Original Assignee
Hitachi Cable Ltd
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Cable Ltd, Hitachi Ltd filed Critical Hitachi Cable Ltd
Priority to JP32950391A priority Critical patent/JPH05144882A/en
Publication of JPH05144882A publication Critical patent/JPH05144882A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H01L2224/48228Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item the bond pad being disposed in a recess of the surface of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item

Landscapes

  • Wire Bonding (AREA)

Abstract

PURPOSE:To enable an outer lead to be hardly lessened in adhesive strength to a carrier film even if it is formed of iron alloy high in mechanical strength by a method wherein an iron alloy foil which contains 2% chrome by weight is used as a foil laminated on an insulating film. CONSTITUTION:A metal layer 2 formed after a pattern is bonded onto an insulating film 1 through the intermediary of an epoxy adhesive agent 20mum or so in thickness to form inner leads 3 and outer leads 4. The insulating film 1 is formed of polyimide film 75mum in thickness and 35mm in width, the metal layer 2 is formed of Ni-Cr-Fe alloy film 50mum in thickness where a tin alloy electroplating film is formed as thick as 1mum. The Ni-Cr-Fe alloy contains 12% nickel by weight and 2% chrome by weight, and the tin alloy contains 90% tin by weight and 10% lead by weight. The inner lead 3 is 40mum in with and the inner leads 3 are arranged at an interval of 60mum between them. By this setup, a semiconductor device can be kept high in mounting reliability.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は半導体装置用フィルムキ
ャリア、特に薄い金属箔を用いることにより多ピン化を
可能にする、半導体装置用フィルムキャリアに関するも
のである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a film carrier for a semiconductor device, and more particularly to a film carrier for a semiconductor device, which enables a multi-pin structure by using a thin metal foil.

【0002】[0002]

【従来の技術】半導体素子の実装では、高集積度の半導
体装置を高速で量産するため、TAB(tape automated
bonding) による自動化が図られている。TABでは、
連続帯状のフィルムキャリアにパターン形成された銅箔
に、半導体素子を、ワイヤを用いないギャングボンディ
ングによって接合し、連続的な実装を可能にしている。
2. Description of the Related Art In the mounting of semiconductor elements, TAB (tape automated) is used to mass-produce high-integration semiconductor devices at high speed.
It is being automated by bonding). In TAB,
A semiconductor element is joined to a copper foil patterned on a continuous strip-shaped film carrier by gang bonding without using a wire to enable continuous mounting.

【0003】TABによる実装の例を図6(A)ないし
(C)に示す。図6(A)に示すように、フィルムキャ
リア31は、可撓性絶縁フィルム1と、その上にパター
ン形成したインナーリード部3及びアウターリード部4
から成る。可撓性絶縁フィルム1はデバイスホール5、
アウターホール6、およびスプロケットホール7を有す
る。フィルムキャリア31上のインナーリード部3を、
図6(B)に示すように、ICチップ41の電極上の金
バンプ42と位置合わせし、加熱されたボンディングツ
ール(図示せず)を押圧することにより、インナーリー
ド部3とICチップ41の金バンプ42を接合する。次
いで、図6(C)に示すように、ICチップ41とイン
ナーリード部3とをモールド樹脂43により封止した上
で、アウターリード部4の先端部で外側の部分から切り
離し、アウターリード部4を配線基板44上の導体部4
5と接合する。
An example of mounting by TAB is shown in FIGS. 6 (A) to 6 (C). As shown in FIG. 6A, the film carrier 31 includes a flexible insulating film 1, and inner lead portions 3 and outer lead portions 4 each having a pattern formed thereon.
Consists of. The flexible insulating film 1 is a device hole 5,
It has an outer hole 6 and a sprocket hole 7. The inner lead portion 3 on the film carrier 31,
As shown in FIG. 6B, the inner lead portion 3 and the IC chip 41 are aligned by aligning with the gold bumps 42 on the electrodes of the IC chip 41 and pressing a heated bonding tool (not shown). The gold bumps 42 are joined. Next, as shown in FIG. 6C, the IC chip 41 and the inner lead portion 3 are sealed with the molding resin 43, and then the outer lead portion 4 is separated from the outer portion by the tip portion of the outer lead portion 4. The conductor part 4 on the wiring board 44
Join with 5.

【0004】図6(A)に示したフィルムキャリア31
を製作するには、可撓性絶縁フィルム1にデバイスホー
ル5、アウターホール6、スプロケットホール(図示せ
ず)等を打抜きにより形成した後、金属箔を接着(ラミ
ネート)し、インナーリード部3およびアウターリード
部4となる部分以外の金属箔2を、フォトエッチングに
より除去する。
The film carrier 31 shown in FIG.
In order to fabricate, the flexible insulating film 1 is formed with a device hole 5, an outer hole 6, a sprocket hole (not shown) and the like by punching, and then a metal foil is adhered (laminated) to the inner lead portion 3 and The metal foil 2 other than the portion to be the outer lead portion 4 is removed by photoetching.

【0005】従来、可撓性絶縁フィルム1としては約7
5〜125μmのポリイミドフィルムが、インナーリー
ド部3およびアウターリード部4となる金属箔2として
は厚さ75μm又は35μmの電解銅箔又は圧延銅箔が
用いられている。銅箔表面は、通常、ポリイミドフィル
ムとの充分な接着が得られるように、粗面化される。イ
ンナーリード3は50〜300本設けられ、金バンプ4
2との接合のため、錫、ハンダ、金等でメッキされる。
アウターリード部4も、配線基板44の導体部45との
ハンダ接合のため、錫、ハンダ、金等でメッキされる。
Conventionally, the flexible insulating film 1 is about 7
A polyimide film having a thickness of 5 to 125 μm is used as the metal foil 2 to be the inner lead portion 3 and the outer lead portion 4, and an electrolytic copper foil or a rolled copper foil having a thickness of 75 μm or 35 μm is used. The copper foil surface is usually roughened so that sufficient adhesion with the polyimide film can be obtained. 50 to 300 inner leads 3 are provided, and gold bumps 4 are provided.
It is plated with tin, solder, gold, etc. for joining with 2.
The outer lead portion 4 is also plated with tin, solder, gold or the like for soldering to the conductor portion 45 of the wiring board 44.

【0006】TABによらない実装方式としては、従来
からのリードフレームを用いたワイヤボンディングによ
る方法がある。リードフレームには、シリコンチップと
熱膨張率が近似している42アロイ(ニッケル42%を
含む鉄合金)が一般に用いられている。
As a mounting method not using TAB, there is a conventional method of wire bonding using a lead frame. A 42 alloy (iron alloy containing 42% nickel), which has a thermal expansion coefficient similar to that of a silicon chip, is generally used for the lead frame.

【0007】[0007]

【発明が解決しようとする課題】半導体素子の集積度の
増大に伴い、多ピン化、すなわちインナーリードの本数
が増加する傾向が著しく、その結果、インナーリードの
幅を細くする必要に迫られている。最近では約40μm
の幅のものが現れている。インナーリードの幅の精度を
保つためには、銅箔をリード幅に近い厚さまで薄くする
必要があるので、40μmの幅に対しては35μm程度
の厚さの銅箔を用いなければならない。厚さ80μm以
下の銅箔を用いたフィルムキャリアでは、アウターリー
ドの強度が不充分で、アウターリードの変形が生じ易
く、実装の信頼度が低下する。
As the degree of integration of semiconductor elements increases, the number of pins, that is, the number of inner leads, tends to increase, and as a result, it becomes necessary to reduce the width of the inner leads. There is. Recently about 40 μm
The width of is appearing. In order to maintain the accuracy of the width of the inner leads, it is necessary to reduce the thickness of the copper foil to a thickness close to the lead width. Therefore, for a width of 40 μm, a copper foil with a thickness of about 35 μm must be used. In the case of a film carrier using a copper foil having a thickness of 80 μm or less, the strength of the outer leads is insufficient, the outer leads are easily deformed, and the mounting reliability is reduced.

【0008】リードフレームに一般に用いられている4
2アロイは、強度は大きいが、ポリイミド等の絶縁フィ
ルムとの接着性に乏しいため、TAB方式のフィルムキ
ャリアには用いることができない。
4 commonly used for lead frames
Although the 2-alloy has high strength, it cannot be used in a TAB type film carrier because of poor adhesion to an insulating film such as polyimide.

【0009】本発明の目的は、インナーリードおよびア
ウターリードの幅を細くして多ピン化するとき、機械的
強度の大きい鉄合金箔でアウターリードを形成しても、
キャリアフィルムとの接着強度が低下しないようにし
た、半導体装置用フィルムキャリアを実現することにあ
る。
An object of the present invention is to reduce the width of the inner lead and the outer lead so as to increase the number of pins, even if the outer lead is formed of an iron alloy foil having high mechanical strength.
It is intended to realize a film carrier for a semiconductor device in which the adhesive strength with the carrier film is not lowered.

【0010】[0010]

【課題を解決するための手段】本発明では、インナーリ
ードおよびアウターリードの幅を細くして多ピン化する
とき、機械的強度の大きい鉄合金箔でアウターリードを
形成しても、キャリアフィルムとの接着強度が低下しな
いようにした、半導体装置用フィルムキャリアを実現す
るため、絶縁フィルムにラミネートする金属箔として、
少なくとも2重量%のクロムを含む鉄合金箔を用いる。
According to the present invention, when the inner leads and the outer leads are thinned to have a large number of pins, even if the outer leads are formed of an iron alloy foil having a high mechanical strength, As a metal foil to be laminated on an insulating film in order to realize a film carrier for semiconductor devices in which the adhesive strength of is not lowered,
An iron alloy foil containing at least 2% by weight of chromium is used.

【0011】多ピン化の目的を達するためには、鉄合金
箔の厚さは80μm以下とする。特に40μm以下とす
る場合、本発明の効果が大きい。
In order to achieve the purpose of increasing the number of pins, the iron alloy foil has a thickness of 80 μm or less. Particularly when the thickness is 40 μm or less, the effect of the present invention is great.

【0012】鉄合金としては、少なくとも2重量%のク
ロムと12%のニッケルを含むFe−Ni−Cr合金
を、用いることができる。
As the iron alloy, an Fe-Ni-Cr alloy containing at least 2% by weight of chromium and 12% of nickel can be used.

【0013】インナーリードの少なくとも先端部、およ
びアウターリードの少なくとも先端部には、半導体チッ
プおよび配線基板との接合のため、錫、ハンダ、金等で
メッキすることが好ましい。鉄は錫よりもイオン化傾向
が大きいため、無電解メッキを利用して錫またはハンダ
をメッキすることができないので、錫またはハンダをメ
ッキするためには電解メッキを用いる必要がある。
At least the tip portion of the inner lead and at least the tip portion of the outer lead are preferably plated with tin, solder, gold or the like for joining to the semiconductor chip and the wiring board. Since iron has a greater ionization tendency than tin, tin or solder cannot be plated using electroless plating, so electrolytic plating must be used to plate tin or solder.

【0014】絶縁フィルムとしては、通常のもの、例え
ば厚さ75ないし125μmのポリイミドフィルムを用
いることができる。
As the insulating film, a usual one, for example, a polyimide film having a thickness of 75 to 125 μm can be used.

【0015】本発明のフィルムキャリアは、ICチップ
上のバンプとインナーリードの圧接によるギャングボン
ディングだけでなく、ワイヤボンディングにも利用でき
る。
The film carrier of the present invention can be used for wire bonding as well as gang bonding by pressure contact between bumps on an IC chip and inner leads.

【0016】[0016]

【作用】本発明のフィルムキャリアは、少なくとも2重
量%のクロムを含む鉄合金から成る金属箔を用いている
ので、銅箔と同様に、ポリイミド等から成る絶縁フィル
ムに接着し、銅箔を用いた従来のフィルムキャリアと同
様にTABによる実装に適用することができる。そし
て、この合金箔は同じ厚さの銅箔より強度が大きいか
ら、薄い箔を用いても、アウターリードに充分な強度を
持たせることができるので、実装においてアウターリー
ドの変形が容易に生じない。
Since the film carrier of the present invention uses a metal foil made of an iron alloy containing at least 2% by weight of chromium, it is adhered to an insulating film made of polyimide or the like in the same manner as the copper foil, and the copper foil is used. It can be applied to mounting by TAB like the conventional film carrier. Since this alloy foil has a higher strength than the copper foil of the same thickness, the outer leads can be made to have sufficient strength even if a thin foil is used, so that the outer leads are not easily deformed during mounting. ..

【0017】[0017]

【実施例】以下に実施例を示し、本発明のさらに具体的
説明とする。 〔実施例1〕本発明によるフィルムキャリアを、ワイヤ
ボンディングに利用した例を示す。図1はワイヤボンデ
ィングのためのフィルムキャリアを示し、絶縁フィルム
1上に、厚さ約20μmのエポキシ接着剤(図示せず)
を介して、パターンに従い形成された金属層2が接着さ
れ、インナーリード部3とアウターリード部4を形成し
ている。絶縁フィルム1は厚さ75μm、幅35mmのポ
リイミドフィルム、金属層2は厚さ50μmのNi−C
r−Fe合金箔で、厚さ1μmの錫合金電気めっきが施
されている。Ni−Cr−Fe合金は12重量%のニッ
ケル、2重量%のクロムを含む合金、錫合金は錫90%
と鉛10%から成るものである。インナーリード部3の
幅は40μm、間隔は60μmである。インナーリード
部3はデバイスホール5内に突き出ていない。
EXAMPLES The following examples are given to further illustrate the present invention. Example 1 An example in which the film carrier according to the present invention is used for wire bonding will be described. FIG. 1 shows a film carrier for wire bonding, in which an epoxy adhesive (not shown) having a thickness of about 20 μm is provided on the insulating film 1.
The metal layer 2 formed in accordance with the pattern is adhered to form the inner lead portion 3 and the outer lead portion 4. The insulating film 1 is a polyimide film having a thickness of 75 μm and a width of 35 mm, and the metal layer 2 is Ni-C having a thickness of 50 μm.
An r-Fe alloy foil is electroplated with a tin alloy having a thickness of 1 μm. Ni-Cr-Fe alloy is an alloy containing 12% by weight nickel and 2% by weight chromium, and tin alloy is 90% tin.
And lead 10%. The inner lead portions 3 have a width of 40 μm and an interval of 60 μm. The inner lead portion 3 does not protrude into the device hole 5.

【0018】このフィルムキャリアは次のようにして製
造した。デバイスホール5、アウターホール6、および
スプロケット(パイロット)ホール7を設けたポリイミ
ド絶縁フィルム1上に、エポキシ接着剤を用いて、Ni
−Cr−Fe合金箔を接着する。フォトエッチングによ
り塩化第二鉄エッチング浴を用いてエッチングを行い、
図4に示すようなパターンの鉄合金の金属層2を、絶縁
フィルム1上に形成する。金属層2はインナーリード部
3とアウターリード部4を含む。パターン形成後、金属
層2の外周部分をメッキ用電源端子に接続し、ハンダ電
気めっき浴中で金属層2の全面に厚さ1μmのハンダ電
気めっきを施す。
This film carrier was manufactured as follows. On the polyimide insulating film 1 provided with the device hole 5, the outer hole 6 and the sprocket (pilot) hole 7, an epoxy adhesive is used to form Ni.
Adhere the Cr-Fe alloy foil. Etching is performed using a ferric chloride etching bath by photoetching,
A metal layer 2 of iron alloy having a pattern as shown in FIG. 4 is formed on the insulating film 1. The metal layer 2 includes an inner lead portion 3 and an outer lead portion 4. After forming the pattern, the outer peripheral portion of the metal layer 2 is connected to a power source terminal for plating, and solder electroplating having a thickness of 1 μm is applied to the entire surface of the metal layer 2 in a solder electroplating bath.

【0019】図2に、本発明のフィルムキャリアを用い
てワイヤボンディングにより製作されたICパッケージ
の断面を示す。ICチップ21とインナーリード部3
は、それぞれ接着剤(図示せず)により可撓性絶縁フィ
ルム1の上に固定され、ICチップ21の接続電極部2
6は、インナーリード部3にボンディングワイヤ11で
接続されている。可撓性絶縁フィルム1の下面にはグラ
ウンド層12が接着されている。グラウンド層12は、
スルーホール13の内壁の導体を通してインナーリード
部3の一つに接続され、また、スルーホール14を通し
た別のボンディングワイヤ15で、ICチップ21の接
続電極部26の一つに接続されている。これらはボンデ
ィングワイヤ11,15とともにモールド樹脂23に封
入されている。
FIG. 2 shows a cross section of an IC package manufactured by wire bonding using the film carrier of the present invention. IC chip 21 and inner lead 3
Are fixed on the flexible insulating film 1 by an adhesive (not shown), respectively, and are connected to the connection electrode portion 2 of the IC chip 21.
Reference numeral 6 is connected to the inner lead portion 3 by a bonding wire 11. A ground layer 12 is adhered to the lower surface of the flexible insulating film 1. The ground layer 12 is
It is connected to one of the inner lead portions 3 through the conductor on the inner wall of the through hole 13 and is also connected to one of the connection electrode portions 26 of the IC chip 21 by another bonding wire 15 passing through the through hole 14. .. These are encapsulated in the molding resin 23 together with the bonding wires 11 and 15.

【0020】上記のテープキャリアを用いた半導体チッ
プの実装は、次のように行う。図3(A)に示すよう
に、ICチップ21上の接続電極部26と、インナーリ
ード部3の先端部の間を、ボンディングワイヤ11で常
法により接続する。またグラウンド層12を、スルーホ
ール14を通してボンディングワイヤ15でアウターリ
ード部4の一つに接続する。アウターリード部4以外
を、図3(B)に示すように、モールド樹脂23で被覆
する。そして、アウターホール6(図1)の外側に沿っ
て金型で打ち抜き、アウターリード部4はその外側の部
分の金属層2及び絶縁フィルム1から切り離される。図
3(C)に示すように、アウターリード部4は折り曲げ
られて、プリント基板24の上のハンダペースト25と
ハンダ接合され、実装が完了する。
Mounting of a semiconductor chip using the above tape carrier is carried out as follows. As shown in FIG. 3A, the connection electrode portion 26 on the IC chip 21 and the tip portion of the inner lead portion 3 are connected by a bonding wire 11 by a conventional method. Further, the ground layer 12 is connected to one of the outer lead portions 4 by the bonding wire 15 through the through hole 14. Parts other than the outer lead portions 4 are covered with a mold resin 23 as shown in FIG. Then, the outer lead portion 4 is separated from the metal layer 2 and the insulating film 1 on the outer side by punching with a mold along the outer side of the outer hole 6 (FIG. 1). As shown in FIG. 3C, the outer lead portion 4 is bent and solder-bonded to the solder paste 25 on the printed board 24, and the mounting is completed.

【0021】〔実施例2〕本発明によるフィルムキャリ
アの他の一例は、図4に示すもので、絶縁フィルム1上
に、厚さ約20μmのエポキシ接着剤(図示せず)を介
して、パターンに従い形成された金属層2が接着され、
インナーリード部3とアウターリード部4を形成してい
る。絶縁フィルム1は厚さ75μm、幅35mmのポリイ
ミドフィルム、金属層2は厚さ50μmのNi−Cr−
Fe合金箔で、厚さ1μmの錫合金電気めっきが施され
ている。Ni−Cr−Fe合金は12重量%のニッケ
ル、2重量%のクロムを含み、錫合金は錫90%と鉛1
0%から成る。インナーリード部3の幅は40μm、間
隔は60μmである。図1に示したフィルムキャリアと
異なり、インナーリード部3がデバイスホール5内に突
き出ている。上述のフィルムキャリアは、実施例1のも
のとほぼ同様の方法で製造される。
Example 2 Another example of the film carrier according to the present invention is shown in FIG. 4, in which a pattern is formed on the insulating film 1 through an epoxy adhesive (not shown) having a thickness of about 20 μm. The metal layer 2 formed according to
The inner lead portion 3 and the outer lead portion 4 are formed. The insulating film 1 is a polyimide film having a thickness of 75 μm and a width of 35 mm, and the metal layer 2 is a Ni—Cr— film having a thickness of 50 μm.
A Fe alloy foil is electroplated with a tin alloy having a thickness of 1 μm. The Ni-Cr-Fe alloy contains 12% by weight nickel, 2% by weight chromium, and the tin alloy contains 90% tin and 1% lead.
It consists of 0%. The inner lead portions 3 have a width of 40 μm and an interval of 60 μm. Unlike the film carrier shown in FIG. 1, the inner lead portion 3 projects into the device hole 5. The film carrier described above is manufactured in a manner substantially similar to that of Example 1.

【0022】上記のテープキャリアを用いた半導体チッ
プの実装は、次のように行う。図5(A)に示すよう
に、ICチップ21上の接続電極部のバンプ22と、イ
ンナーリード部3の先端部が、約500℃の温度で圧接
され、接合される。ICチップ21とインナーリード部
3は、図5(B)に示すように、モールド樹脂23で被
覆される。そして、アウターホール6(図4)の外側に
沿って金型で打ち抜き、アウターリード部4はその外側
の金属層2の外側寄りの部分及び絶縁フィルム1から切
り離される。図5(C)に示すように、アウターリード
4は折り曲げられて、プリント基板24の上に印刷され
たハンダペースト25とハンダ接合され、実装が完了す
る。ハンダ電気メッキされたアウターリード4に対する
ハンダの濡れは良好である。
Mounting of a semiconductor chip using the above tape carrier is performed as follows. As shown in FIG. 5 (A), the bumps 22 of the connection electrode portion on the IC chip 21 and the tips of the inner lead portions 3 are pressed and joined at a temperature of about 500 ° C. As shown in FIG. 5B, the IC chip 21 and the inner lead portion 3 are covered with the mold resin 23. Then, the outer lead portion 4 is separated from the outer portion of the metal layer 2 on the outer side and the insulating film 1 by punching with a mold along the outer side of the outer hole 6 (FIG. 4). As shown in FIG. 5C, the outer leads 4 are bent and solder-bonded to the solder paste 25 printed on the printed board 24, and the mounting is completed. Wetting of the solder on the electroplated outer leads 4 is good.

【0023】〔比較例1〜2〕比較のため、金属層2と
してNi−Cr−Fe合金箔の代わりに、同じ厚さの4
2アロイ箔(比較例1)および電解銅箔(比較例2)を
それぞれ用い、それ以外は実施例2と同様にしてテープ
キャリアを調製した。
[Comparative Examples 1 and 2] For comparison, as the metal layer 2, instead of the Ni—Cr—Fe alloy foil, the metal layer 4 having the same thickness was used.
A tape carrier was prepared in the same manner as in Example 2 except that the two alloy foils (Comparative Example 1) and the electrolytic copper foil (Comparative Example 2) were used.

【0024】実施例2と比較例1及び2の各フィルムキ
ャリアについて、金属箔とポリイミドフィルムの接着力
を測定した。結果を表1に示す。
For each film carrier of Example 2 and Comparative Examples 1 and 2, the adhesive force between the metal foil and the polyimide film was measured. The results are shown in Table 1.

【0025】 [0025]

【0026】表1から明らかなように、本発明のフィル
ムキャリアは、42アロイを用いた比較例1に比べて、
ポリイミドフィルムとの接着力が大幅に向上している。
As can be seen from Table 1, the film carrier of the present invention has a higher density than that of Comparative Example 1 using 42 alloy.
The adhesive strength with the polyimide film is greatly improved.

【0027】[0027]

【発明の効果】本発明による半導体装置用フィルムキャ
リアは、インナーリードの幅を細くして多ピン化するた
めに薄い金属箔を用いても、充分な機械的強度を有する
鉄合金箔でアウターリードを構成しているため、実装に
おいてアウターリードの変形が容易に生じないから、実
装の信頼性を保つことができ、信頼性の低下を伴わずに
多ピン化が可能となる。
According to the film carrier for a semiconductor device of the present invention, the outer lead is made of an iron alloy foil having sufficient mechanical strength even if a thin metal foil is used in order to reduce the width of the inner lead and increase the number of pins. Since the outer leads are not easily deformed during mounting, the reliability of the mounting can be maintained and the number of pins can be increased without lowering the reliability.

【0028】強度の優れた鉄合金をアウターリードの材
料とした半導体デバイスは、これまでリードフレームを
用いて製造するほかなかったが、本発明によるとキャリ
アフィルムとの充分な接着強度を得ることができ、フィ
ルムキャリアを用いて製造することができるから、多ピ
ン化が可能になり、しかも高能率に量産できる。
A semiconductor device using an iron lead having excellent strength as a material for an outer lead has been manufactured by using a lead frame, but according to the present invention, a sufficient adhesive strength with a carrier film can be obtained. Since it can be manufactured using a film carrier, the number of pins can be increased and mass production can be performed with high efficiency.

【図面の簡単な説明】[Brief description of drawings]

【図1】図1は本発明によるテープキャリアの他の実施
例を示す平面図である。
FIG. 1 is a plan view showing another embodiment of a tape carrier according to the present invention.

【図2】図2は、本発明によるテープキャリアの他の実
施例で製作される半導体パッケージを示す断面説明図で
ある。
FIG. 2 is a sectional view showing a semiconductor package manufactured by another embodiment of the tape carrier according to the present invention.

【図3】図3(A)ないし(C)は、本発明によるテー
プキャリアを用いた、ワイヤボンディングによる半導体
チップの実装を示す断面説明図である。
FIGS. 3A to 3C are cross-sectional explanatory views showing mounting of a semiconductor chip by wire bonding using the tape carrier according to the present invention.

【図4】図4は本発明によるテープキャリアの一実施例
を示す平面図である。
FIG. 4 is a plan view showing an embodiment of the tape carrier according to the present invention.

【図5】図5(A)ないし(C)は、本発明によるテー
プキャリアを用いた半導体チップの実装を示す断面説明
図である。
5A to 5C are cross-sectional explanatory views showing mounting of a semiconductor chip using the tape carrier according to the present invention.

【図6】図6(A)ないし(C)は、一般的なTABに
よる実装を示す断面説明図である。
FIG. 6A to FIG. 6C are cross-sectional explanatory views showing mounting by a general TAB.

【符号の説明】[Explanation of symbols]

1 可撓性絶縁フィルム 2 金属層 3 インナーリード部、インナーリード 4 アウターリード部、アウターリード 5 デバイスホール 6 アウターホール 7 スプロケットホール 11 ボンディングワイヤ 12 グラウンド層 13 スルーホール 14 スルーホール 15 ボンディングワイヤ 21 ICチップ 22 バンプ 23 モールド樹脂 24 プリント基板 25 ハンダペースト 26 接続電極部 31 フィルムキャリア 41 ICチップ 42 金バンプ 43 モールド樹脂 44 配線基板 45 導体部 1 flexible insulating film 2 metal layer 3 inner lead part, inner lead 4 outer lead part, outer lead 5 device hole 6 outer hole 7 sprocket hole 11 bonding wire 12 ground layer 13 through hole 14 through hole 15 bonding wire 21 IC chip 22 Bump 23 Mold Resin 24 Printed Circuit Board 25 Solder Paste 26 Connection Electrode Section 31 Film Carrier 41 IC Chip 42 Gold Bump 43 Mold Resin 44 Wiring Board 45 Conductor Section

───────────────────────────────────────────────────── フロントページの続き (72)発明者 鈴木 博通 東京都小平市上水本町5丁目20番1号 株 式会社日立製作所武蔵工場内 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor, Hiromichi Suzuki, 5-20-1 Kamimizuhonmachi, Kodaira-shi, Tokyo Inside the Musashi Factory, Hitachi Ltd.

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】 半導体素子の電極と直接または間接に接
合されるインナーリード部と、外部回路と接続するため
の、前記インナーリード部と一体に形成されたアウター
リード部と、前記インナーリード部および前記アウター
リード部がラミネートされた絶縁フィルムから成り、 前記アウターリード部が、少なくとも2重量%のクロム
を含む鉄合金から成ることを特徴とする、半導体装置用
フィルムキャリア。
1. An inner lead portion directly or indirectly joined to an electrode of a semiconductor element, an outer lead portion integrally formed with the inner lead portion for connecting to an external circuit, the inner lead portion, and A film carrier for a semiconductor device, wherein the outer lead part is made of a laminated insulating film, and the outer lead part is made of an iron alloy containing at least 2% by weight of chromium.
【請求項2】 前記アウターリード部が80μm以下の
厚さを有し、0.15ないし0.30mmのピッチで形成さ
れている、請求項1の半導体装置用フィルムキャリア。
2. The film carrier for a semiconductor device according to claim 1, wherein the outer lead portions have a thickness of 80 μm or less and are formed at a pitch of 0.15 to 0.30 mm.
【請求項3】 半導体素子の電極と接合されるインナー
リード部と、外部回路と接続するための、前記インナー
リード部と一体に形成されたアウターリード部と、前記
インナーリード部および前記アウターリード部がラミネ
ートされた絶縁フィルムから成り、 前記アウターリード部が、80μm以下の厚さを有する
鉄合金箔から成り、0.15ないし0.30mmのピッチで
形成されていることを特徴とする、半導体装置用フィル
ムキャリア。
3. An inner lead portion joined to an electrode of a semiconductor element, an outer lead portion formed integrally with the inner lead portion for connecting to an external circuit, the inner lead portion and the outer lead portion. A laminated insulating film, wherein the outer lead portions are made of an iron alloy foil having a thickness of 80 μm or less, and are formed at a pitch of 0.15 to 0.30 mm. Film carrier.
JP32950391A 1991-11-18 1991-11-18 Film carrier for semiconductor device Pending JPH05144882A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP32950391A JPH05144882A (en) 1991-11-18 1991-11-18 Film carrier for semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP32950391A JPH05144882A (en) 1991-11-18 1991-11-18 Film carrier for semiconductor device

Publications (1)

Publication Number Publication Date
JPH05144882A true JPH05144882A (en) 1993-06-11

Family

ID=18222104

Family Applications (1)

Application Number Title Priority Date Filing Date
JP32950391A Pending JPH05144882A (en) 1991-11-18 1991-11-18 Film carrier for semiconductor device

Country Status (1)

Country Link
JP (1) JPH05144882A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0855879A (en) * 1994-08-16 1996-02-27 Nec Corp Tape for tab and manufacture of semiconductor device using tape for tab
JP2010074621A (en) * 2008-09-19 2010-04-02 Nitto Denko Corp Circuit board for isolator, isolator, and method for manufacturing isolator

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0855879A (en) * 1994-08-16 1996-02-27 Nec Corp Tape for tab and manufacture of semiconductor device using tape for tab
JP2010074621A (en) * 2008-09-19 2010-04-02 Nitto Denko Corp Circuit board for isolator, isolator, and method for manufacturing isolator

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