JPH0513567A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To manufacture a semiconductor device of high integration degree regardless of high threshold voltage of a parasitic MOS transistor and high junction breakdown strength between a diffusion layer for a channel stopper and a diffusion layer in an element active region. CONSTITUTION:After a diffusion layer 15 of low concentration is formed a pattern of an isolation region 16 and an SiO2 film 22 is formed on a surface of the isolation region 16, a diffusion layer 21 of high concentration is formed to have an offset amount (o) from the isolation active region 14. Therefore, side diffusion is not caused in the diffusion layer 21 by heat during heat oxidation for forming the SiO2 film 22 and the formed diffusion layer 15 is not eroded by the diffusion layer 21. Therefore, integration degree can be improved with a little offset amount (o) for preventing disappearance of the diffusion layer 15.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device having a diffusion layer for a channel stopper under a dielectric film for element isolation.

[0002]

2. Description of the Related Art There is dielectric isolation as one of element isolation methods in a monolithic IC. However, the threshold voltage of a parasitic MOS transistor whose channel is a semiconductor substrate below a dielectric film for element isolation is higher than the operating voltage of the IC. Raise this parasitic M
In order to cut off the OS transistor and thereby complete the element isolation, it is general to form a diffusion layer called a channel stopper under the dielectric film.

However, if the high-concentration channel stopper and the high-concentration diffusion layer in the element active region come into direct contact with each other at the boundary between the element isolation region and the element active region, the junction breakdown voltage between them decreases. On the other hand, if the impurity concentration of the channel stopper is low, the threshold voltage of the parasitic MOS transistor will not be sufficiently high and element isolation cannot be completed.

Therefore, conventionally, a semiconductor device having a channel stopper has been formed by the method shown in FIG. That is,
In this conventional example, as shown in FIG.
Forming a SiO ₂ film 12 of the pad on the surface of, Si ₃ N
_{After processing the 4} film 13 on the SiO ₂ film 12 into the pattern of the element active region 14, a low concentration diffusion layer 15 is formed in the Si substrate 11 using the Si ₃ N ₄ film 13 as a mask. Therefore, the diffusion layer 15 is formed in the pattern of the element isolation region 16.

After that, the resist 17 is patterned so as to have a predetermined offset amount o from the edge of the element active region 14 to the element isolation region 16 side, and impurities 18 are ion-implanted using the resist 17 as a mask. S
A high-concentration diffusion layer 21 is formed in the i substrate 11. Then, after removing the resist 17, thermal oxidation is performed using the Si ₃ N ₄ film 13 as an oxidation resistant mask to form a SiO ₂ film 22 on the surface of the element isolation region 16 as shown in FIG. 2B. .

[0006]

However, due to the heat generated during the thermal oxidation for forming the SiO ₂ film 22, the already formed diffusion layer 21 is laterally diffused, and the diffusion layer 15 is eroded by the diffusion layer 21. To be done. If the offset amount o is not sufficient, the diffusion layer 15 disappears completely as shown in FIG. 2B, and the high-concentration diffusion layer 23 and the diffusion layer 21 which will be formed in the element active region 14 later are formed. Contact directly.

As described above, in order to prevent the diffusion layer 21 and the diffusion layer 23 from directly contacting each other and preventing the junction breakdown voltage between them from decreasing, the offset amount o is at least about 0.5 μm. Is necessary. On the other hand, the patterning width of the resist 17 is currently required to be about 0.6 μm due to the limit of lithography. Therefore, SiO
The width of the _two films 22 needs to be 1.6 μm or more, and it is difficult to further reduce the width and increase the degree of integration.

[0008]

According to a first aspect of the present invention, there is provided a method of manufacturing a semiconductor device, wherein after forming a dielectric film 22 for element isolation, a first diffusion layer 21 for a channel stopper is formed on the dielectric film 22. It is formed below and apart from the element active region 14.

In the method of manufacturing a semiconductor device according to a second aspect of the present invention, the second diffusion layer 15 for a channel stopper having an impurity concentration intermediate between the semiconductor substrate 11 and the first diffusion layer 21 is formed on the dielectric film 22. Form self-aligned below.

[0010]

In the method of manufacturing a semiconductor device according to the first aspect, since the first diffusion layer 21 is formed after the dielectric film 22 for element isolation is formed, the dielectric film 22 for element isolation is formed. Therefore, the first diffusion layer 21 does not laterally diffuse due to the heat treatment. Therefore, in order to separate the first diffusion layer 21 from the element active region 14, the distance o that should be secured between them may be short.

In the method of manufacturing a semiconductor device according to the second aspect, the second diffusion layer 15 having an impurity concentration intermediate between the semiconductor substrate 11 and the first diffusion layer 21 is formed below the dielectric film 22 for element isolation. This second diffusion layer 1 is formed in a consistent manner.
5 is formed in a self-aligned manner between the first diffusion layer 21 and the device active region 14.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIG.

Also in this embodiment, the Si ₃ N ₄ film 13 is used as a mask until the diffusion layer 15 having a low impurity concentration of about 10 ¹⁷ cm ^-3 or more is formed in the Si substrate 11 as shown in FIG. Substantially the same steps as the conventional example shown are performed. However, in this embodiment, before forming the high-concentration diffusion layer 21, thermal oxidation is performed using the Si ₃ N ₄ film 13 as an oxidation resistant mask to form the SiO ₂ film 22. So at this point,
The diffusion layer 15 is formed under the SiO ₂ film 22 in a self-aligned manner.

Thereafter, as shown in FIG. 1, the device active region 1
By patterning the resist 24 so as to have a predetermined offset amount o from the edge of No. 4 toward the element isolation region 16 side, and by ion-implanting the impurity 18 so as to penetrate the SiO ₂ film 22 using the resist 24 as a mask. , The impurity concentration of about 10 ¹⁸ cm ⁻³ or more and the high concentration diffusion layer 21
It is formed under the O ₂ film 22. As a result, the diffusion layer 15 is formed between the diffusion layer 21 and the device active region 14 in a self-aligned manner.

As the impurity 18, B ⁺ or the like is used when the portion where the diffusion layer 21 is to be formed is the N channel portion, and Phos ⁺ or the like is used when the portion is the P channel portion. The energy of ion implantation depends on the thickness of the SiO ₂ film 22, but B ⁺ is 7
Ion implantation with an energy of about 0 to 220 kev, Ph
os ⁺ is ion-implanted at an energy of about 200 to 600 kev.

[0016] As a result of the high concentration diffusion layer 21 is formed in a center portion of the lower SiO ₂ film 22 in this manner, the SiO ₂ film 22
The threshold voltage of the parasitic MOS transistor whose channel is the lower Si substrate 11 is high. Further, since the low-concentration diffusion layer 15 is in direct contact with the high-concentration diffusion layer 23 formed in the element active region 14 later, these diffusion layers 15 and 2 are formed.
The junction breakdown voltage between the three is also high.

In this embodiment as described above, the SiO ₂ film 22 is used.
Since the high-concentration diffusion layer 21 is formed after forming, the diffusion layer 21 does not laterally diffuse due to the heat at the time of thermal oxidation for forming the SiO ₂ film 22, and the diffusion layer already formed. 15 is not eroded by the diffusion layer 21. Therefore, in order to avoid direct contact between the high-concentration diffusion layer 23 and the diffusion layer 21 formed in the element active region 14 later, if an offset amount o of about 0.2 μm is secured. Good.

Therefore, an offset amount o of about 0.5 μm
In this embodiment, a semiconductor device having a much higher degree of integration can be manufactured, as compared with the above-described conventional example which required the above.
Further, as is apparent from the above description, the diffusion layer 15 is formed between the diffusion layer 21 and the element active region 14 in a self-aligned manner, so that the diffusion layer 15 can be easily formed.

[0019] Although in the above embodiment to form a diffusion layer 15 before the formation of the SiO ₂ film 22, in a manner similar to the formation of the diffusion layer 21, the SiO ₂ film after formation of the SiO ₂ film 22 22
The diffusion layer 15 may be formed by ion-implanting impurities with a high energy so as to penetrate through.

The present invention requires an EPROM and an EEPROM that require a voltage of about 5 V, which is significantly higher than that of a normal V _CC power supply, for writing and erasing data, and specifications that input / output terminals are higher than the V _CC power supply. The present invention can be applied to an MCU having a fluorescent display tube driving terminal and the like.

[0021]

According to the method of manufacturing a semiconductor device of claim 1,
Since the distance to be secured between the first diffusion layer for the channel stopper and the element active region may be short, the distance between the diffusion layer for the channel stopper and the diffusion layer in the element active region may be small. It is possible to manufacture a semiconductor device having a high degree of integration despite having a high junction breakdown voltage.

According to another aspect of the method of manufacturing a semiconductor device of the present invention, the second diffusion layer for a channel stopper having a relatively low concentration includes the first diffusion layer for a channel stopper having a relatively high concentration and the element active region. Since it is formed in a self-aligned manner, the semiconductor device having a high threshold voltage of the parasitic MOS transistor and a high junction breakdown voltage between the diffusion layer for the channel stopper and the diffusion layer in the element active region can be easily manufactured. it can.

[Brief description of drawings]

FIG. 1 is a side sectional view showing an embodiment of the present invention.

FIG. 2 is a side sectional view sequentially showing a conventional example of the invention of the present application.

[Explanation of symbols]

11 Si substrate 14 element active region 15 diffusion layer 16 element isolation region 21 diffusion layer 22 SiO ₂ film

Claims (2)

[Claims] 1. A method of manufacturing a semiconductor device, comprising forming a dielectric film for element isolation, and then forming a first diffusion layer for a channel stopper under the dielectric film and away from an element active region. 2. A second diffusion layer for a channel stopper, which has an impurity concentration between the semiconductor substrate and the first diffusion layer, is formed under the dielectric film in a self-aligned manner. Manufacturing method of semiconductor device.