JPH02309653A - Manufacture of semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To miniaturize both an active region and a separation region and enhance integration by performing etching so that the concentration of impurities near the bottom of a field insulating film reaches the maximum and by setting thickness within a specific range. CONSTITUTION:Boron ions are implanted at an acceleration voltage so that the distribution of impurities near the bottom part of a field insulating film 2 reaches the maximum, namely at an acceleration voltage where the projection tracing may nearly agree with the film thickness of the field insulating film 2. Then, heat treatment for activating the implanted boron ions is performed, thus forming a channel stopper region 4 below the field insulating film 2 and an inverse slant well region 5 below an active region 3. Then the field insulting film 2 is selectively etched to have a thickness of 100-400nm. This makes it possible to narrow the width of active region since the horizontal diffusion at the channel stopper region 4 below the element isolation region can be restricted, thus obtaining a highly integrated semiconductor integrated circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a method of manufacturing a semiconductor integrated circuit suitable for high integration.

2. Description of the Related Art A MIS type integrated integrated circuit device is composed of a so-called active region forming an integrated circuit device and a so-called isolation region electrically separating adjacent active regions. As integrated circuits become more highly integrated,
The width of the isolation region tends to be miniaturized, and it is necessary to increase the impurity concentration of the isolation region in order to suppress the spread of the depletion layer into the isolation region.

Conventionally, the method of manufacturing a semiconductor integrated circuit for increasing the impurity concentration in the isolation region has been as described below.

FIGS. 3A to 3C show step-by-step cross-sectional views of a conventional method for manufacturing a semiconductor integrated circuit, and will be described with reference to these drawings.

First, as shown in FIG. 3(a), a P-type semiconductor substrate 11
A silicon oxide film 12 and a silicon nitride film 13 are sequentially laminated thereon.

Next, as shown in FIG. 3(b), only the portion that will become the active region is covered with photoresist@14, and the silicon nitride film 1
3 is selectively etched away, and boron ions are implanted using the photoresist film 14 as a mask.

Next, as shown in FIG. 3C, after removing the photoresist film 14, the entire substrate is heat-treated in an oxidizing atmosphere to form a field oxide film 15.

During this heat treatment process, the implanted boron ions are activated as impurities and diffused into the substrate 11, forming a channel stopper region 16 with a higher concentration than the substrate 11 directly under the field oxide film. . Silicon nitride film 13
The area covered by becomes the active region 17.

Thereafter, elements such as transistors are formed according to a normal semiconductor integrated circuit manufacturing method.

Problems to be Solved by the Invention In the conventional semiconductor integrated circuit manufacturing method as described above, if the width of the isolation region, that is, the field oxide film 15 is to be reduced in order to achieve high integration, the width of the channel stopper region 16 is reduced. It is necessary to increase the impurity concentration, but in this case, when the field oxide film 15 is formed, the channel stopper region 16 will be diffused laterally by thermal diffusion and will also enter the active region 17, resulting in the effective reduction of the active region 17. Since the width of the active region 17 becomes narrower and the characteristics of the device change, the width of the active region 17 cannot be made very small, making it difficult to achieve high integration.

When the oxidation temperature is lowered to suppress the lateral diffusion of the channel stopper region 16, the viscosity of the silicon oxide film decreases, which causes mechanical stress at the edge of the field oxide film 15, causing crystal defects in the substrate 11. occurs, causing leakage current, etc.

Means for Solving the Problems A method for manufacturing a semiconductor integrated circuit according to the present invention for solving the above-mentioned problems includes defining the surface of a semiconductor substrate into an active region and an isolation region, and forming a thickness in the isolation region. forming a field insulating film with a thickness of 500 nm or more, and implanting impurity ions into the active region and isolation region at an acceleration voltage such that the impurity concentration is maximum near the bottom of the field insulating film; This process consists of etching the film to a thickness in the range of 1100 nm to 400 nm.

Effect: According to the method of manufacturing a semiconductor integrated circuit of the present invention, both the active region and the isolation region can be miniaturized, and a semiconductor integrated circuit with a high degree of integration can be manufactured.

Embodiment An embodiment of the present invention will be explained with reference to the sectional views shown in FIGS.

First, as shown in FIG. 1(a), a field insulating film 2 with a thickness of 600 to 800 nm is formed on a part of the surface of a P-type semiconductor substrate 1 by a well-known photoetching method, and at the same time an active region 3 is formed. - The thickness of the field insulating film 2 is set to 500 nm in order to prevent the impurity distribution under the active region from greatly affecting the surface in the later ion implantation.
m or more is required.

Next, as shown in FIG. 1(b), the field insulating film 2
Boron ions are implanted at an accelerating voltage such that the impurity distribution is maximum near the bottom of the field insulating film 2, that is, the so-called projected range approximately matches the thickness of the field insulating film 2. B
For + ions, acceleration voltage 220keV and 310k
eVi? Projected ranges in silicon dioxide of approximately 600 nm and approximately 800 nm are obtained, respectively.

Next, as shown in FIG. 1(C), a heat treatment is performed to activate the implanted boron ions, and a channel stopper region 4 is formed under the field oxide film 2, and a channel stopper region 4 is formed under the active region 3. At the same time, a reversely inclined well region 5 is formed.

Next, as shown in FIG. 1(b), the field insulating film 2
is selectively etched to a thickness of 100 to 400 nm. The film thickness of the field insulating film 2 at this point is 110
If it is smaller than 0n, a sufficient threshold voltage of the parasitic Mis) transistor using the field insulating film 2 as the gate oxide film cannot be secured. Furthermore, if the film thickness is greater than 400 nm, the steps on the surface will become thicker, causing problems such as disconnection of wiring.

The depth distribution of impurities at this point is shown in FIG. As shown in the figure, the impurity distribution in the active region 3 is maximum at a deep portion, and is sufficiently low at the surface, so that it is easy to adjust in a later step.

Thereafter, elements such as transistors may be formed according to a normal semiconductor integrated circuit manufacturing method.

According to this method of manufacturing a semiconductor integrated circuit, channel stopper region 4 is not subjected to high-temperature, long-term heat treatment, so that lateral diffusion can be suppressed. Furthermore, since ions are implanted sufficiently deeply in the active region 3, the influence on the impurity concentration near the surface is small. Furthermore, the existence of the reversely inclined well region 5 lowers the resistance of the substrate 1, so that so-called latch-up is suppressed in the complementary MIS integrated circuit.

As mentioned above, the film thickness of the field insulating film 2 is ultimately thinner than the film thickness originally formed, so the level difference on the surface of the substrate 1 can be sufficiently alleviated, and problems such as disconnection of wiring do not occur. .

In the embodiment shown in FIG. 1, the field insulating film 2 is etched after activating the implanted ions.
The formation order may be reversed, and the activation heat treatment may also serve as the heat treatment for forming elements such as transistors.

Further, although a P-type semiconductor substrate is used in the embodiment for convenience of explanation, the same method can be applied to an N-type semiconductor substrate by selecting the ion species and the implantation acceleration voltage.

It is also possible to select and set the film thickness etc. as appropriate.

Effects of the Invention According to the method of manufacturing a semiconductor integrated circuit of the present invention, lateral diffusion of the channel stopper region under the element isolation region can be suppressed, so that the width of the active region can be narrowed. Furthermore, since a reversely inclined well is formed in the active region, the resistance of the substrate is reduced. Furthermore, the level difference on the substrate surface can be made smaller.

Therefore, according to the present invention, a highly integrated semiconductor integrated circuit can be manufactured as a result.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view showing an embodiment of the method for manufacturing a semiconductor integrated circuit according to the present invention, FIG.
The figure is a cross-sectional view showing a conventional method for manufacturing a semiconductor FI precision circuit. DESCRIPTION OF SYMBOLS 1... P-type semiconductor substrate, 2... Field insulating film, 3... Active region, 4...
Channel stopper region, 5...Reverse inclined well region. Name of agent: Patent attorney Shigetaka Awano and 1 other person Figure 2 Basic EA side Kari's structure Toshiba Hanjo 2 Figure 3

Claims (1)

[Claims] defining a surface of the semiconductor substrate into an active region and an isolation region;
forming a field insulating film with a thickness of 500 nm or more on the isolation region, and implanting impurity ions into the active region and the isolation region at an accelerating voltage such that the impurity concentration is maximum near the bottom of the field insulating film. After that, the field insulating film is etched to a thickness of 1
1. A method for manufacturing a semiconductor integrated circuit, comprising a step of making the thickness within a range of 00 nm to 400 nm.