JPH05134921A - Memory space expanding system - Google Patents

Abstract

PURPOSE:To provide a memory space expanding system which can expand a memory space without requiring the control carried out by the software of a microprocessor. CONSTITUTION:The status signal 5 of a microprocessor 1 is decoded by a decoder 2 and an instruction memory selection signal 6 and a data memory selection signal 7 are produced. Then the spaces of an instruction memory 3 and a data memory 4 are generated in the same size as the address space of the microprocessor 1.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a system composed of a microprocessor and a memory, and more particularly to a system for expanding a memory space.

[0002]

2. Description of the Related Art A conventional memory space expansion method will be described with reference to the drawings. FIG. 4 is a block diagram illustrating a conventional technique. The data bus 9 of the microprocessor 1 is connected to the memory bank switching register 22, and the address bus 8 is connected to the address decoder 24. The register selection signal 25 output from the address decoder 24 is connected to the memory bank switching register 22. The memory bank selection signal 26 output from the memory bank switching register 22 is connected to the chip select of each memory constituting the memory bank 23.

Next, the operation will be described. The microprocessor 1 outputs an address for selecting the memory bank switching register 22 to the address bus 8 by executing the I / O instruction, and the address decoder 24 outputs a register selection signal 25 for selecting the memory bank switching register 22 by address decoding. .. Subsequently, the microprocessor 1 puts information on which one of the memory banks 23 is selected on the data bus 9 and writes the information in the memory bank switching register 22. The memory bank switching register 22 activates the selected memory bank 23 by activating the memory bank selection signal 26 according to the written information.

The memory bank selection is completed by the procedure described above, and the subsequent memory access of the microprocessor 1 is fixedly performed to the activated memory bank 23. In this way, the memory space is expanded by overlappingly mapping each bank in the address space of the microprocessor.

[0005]

As described above, in the conventional memory space expansion method using the memory bank, the software executed by the microprocessor 1 must control the memory bank 23 when the memory space is expanded. There was a problem.

The present invention has been made in view of the above points, and an object of the present invention is to provide a memory space expansion system capable of expanding a memory space without control by software of a microprocessor.

[0007]

In order to achieve the above object, the memory space expansion method according to the present invention is based on a status signal of a microprocessor, from a memory control signal of the microprocessor to an instruction memory control signal and a data memory control. Signal is generated, and the instruction memory and the data memory are individually controlled by the instruction memory control signal and the data memory control signal.

[0008]

According to the present invention, an instruction memory control signal and a data memory control signal are generated from a memory control signal of the microprocessor according to a status signal of the microprocessor, and an instruction memory is generated by the instruction memory control signal and the data memory control signal. By controlling the data memory individually, an instruction memory space and a data memory space having the same size as the address space of the microprocessor are generated.

[0009]

【Example】

Embodiment 1 Next, the present invention will be described with reference to the drawings. FIG. 1 is a block diagram of an embodiment of the present invention. A status signal 5 including instruction access and data access information of the microprocessor 1 is input to the decoder 2. The instruction memory selection signal 6 output from the decoder 2 is connected to the chip select of the instruction memory 3, and the data memory selection signal 7 is connected to the chip select of the data memory 4.

Next, the operation will be described. At the same time that the bus cycle of the microprocessor 1 is activated, the status signal 5 outputs information indicating whether the bus cycle is an instruction fetch cycle or a data access cycle.
Entered in. When the bus cycle is the instruction fetch cycle, the decoder 2 activates the instruction memory selection signal 6 and activates the instruction memory 3. Subsequently, the microprocessor 1 fetches an instruction from the instruction memory 3. On the other hand, when the bus cycle is the data access cycle, the decoder 2 activates the data memory selection signal 7 and activates the data memory 4. Subsequently, the microprocessor 1 makes a data access to the data memory 4.

As a result, the instruction memory 3 and the data memory 4
Are redundantly mapped in the address space of the microprocessor 1, so that the memory space including the instruction memory 3 and the data memory 4 is doubled to the address space of the microprocessor 1.

Embodiment 2 FIG. 2 is a block diagram showing another embodiment of the present invention. The status signal 5 and the address 8 including the instruction access and data access information of the microprocessor 1 are input to the decoder 10. The memory bank selection signal 11 output from the decoder 10 is connected to the chip select of each memory bank 12.

Next, the operation will be described. At the same time that the bus cycle of the microprocessor 1 is activated, the status signal 5 outputs information indicating whether the bus cycle is an instruction fetch cycle or a data access cycle and address information is output to the decoder 10. The decoder 10 selects one of the memory banks 12 on the basis of the information, and the microprocessor 1 subsequently performs instruction fetch or data access to the selected memory bank 12. In this case, the same memory bank 12 can have an instruction memory area and a data memory, and in this case, it is superior to the first embodiment in that the instruction memory can be a RAM (the method of implementation will be shown as a supplement below).

FIG. 3 shows a block diagram of a system in which the instruction memory is a RAM. Memory bank is memory bank α2
1 and a memory bank β20, and each memory bank includes a ROM 13 and a RAM 27. The instruction area 14 of the instruction transfer program of the boot loader built into the ROM 13 is arranged in the memory bank β20, the data area 15 is arranged in the memory bank α21, the instruction area 15 of the data transfer program is arranged in the memory bank α21, and the data area 16 is arranged in the memory bank α21. Place at β20.

Next, the operation will be described. After resetting the microprocessor, first, an instruction is transferred from the secondary storage to the instruction area 19 of the memory bank α21 by an instruction transfer instruction on the memory bank β20, and then the attribute (instruction / data) of the memory bank is switched to the memory bank α21 From the secondary storage to the memory bank β20 by the above data transfer instruction.
The data is transferred to the data area 18 of. By using such a method, the instruction memory can also be made into RAM.

[0016]

As described above, according to the present invention, by individually controlling the instruction memory and the data memory based on the status signal of the microprocessor, the memory space can be software up to twice the size of the address space of the microprocessor. The effect is that it can be expanded without control by.

[Brief description of drawings]

FIG. 1 is a block diagram of a first embodiment of the present invention.

FIG. 2 is a block diagram of a second embodiment of the present invention.

FIG. 3 is a block diagram of capturing explanation of the second embodiment.

FIG. 4 is a block diagram of a conventional example.

[Explanation of symbols]

 1 Microprocessor 2 Decoder 3 Instruction Memory 4 Data Memory 5 Status Signal 6 Instruction Memory Selection Signal 7 Data Memory Selection Signal 8 Address Bus 9 Data Bus 10 Decoder 11 Memory Bank Selection Signal 12 Memory Bank 13 ROM 14 Instruction Instruction area of transfer program 15 Data area of instruction transfer program 16 Data area of data transfer program 17 Instruction area of data transfer program 18 Data area 19 Instruction area 20 Memory bank β 21 Memory bank α 22 Memory bank switching register 23 Memory・ Bank 24 Address decoder 25 Register selection signal 26 Memory bank selection signal 27 RAM

Claims (1)

[Claims] 1. A status signal of the microprocessor generates an instruction memory control signal and a data memory control signal from the memory control signal of the microprocessor, and the instruction memory control signal and the data memory control signal generate the instruction memory and the data memory. A memory space expansion method characterized by generating individually an instruction memory space and a data memory space having the same size as the address space of a microprocessor.