JPH04280333A - Address extension system - Google Patents

Abstract

PURPOSE:To realize the extension of an address without adding hardware and to branch it into desired addresses on the address extension system of a microprocessor having a limited and peculiar address designation signal line. CONSTITUTION:The rewrite instructions 22 and 23 of an address extension register 12 are arranged in the fixed areas 20 and 21 of basic space 16 and extended space 17 in a memory 15.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention This invention relates to address extension schemes for microprocessors having a limited number of unique addressing signal lines. In recent years, as computer systems have become larger, the address space of processors has expanded, but in conventional microprocessors that house processors on a single chip, the address lines they originally had exceeded the address space that could be specified. It was not possible to expand the memory.

[0002] For this reason, a method has been adopted in which an address extension register is provided in a microprocessor and the register value is output as is to an external pin to extend the address.

0003

2. Description of the Related Art As a conventional address extension method, there is one shown in FIG. 6, for example. In FIG. 6, 1 is a microprocessor, and a program counter 2 is provided in the microprocessor 1, and the program counter 2 specifies the address of the basic space 4 or the extended space 5 of the memory 3.

Reference numeral 6 denotes an address extension register provided in the microprocessor 1. When the address extension register 6 is set to "0", the output of the inverter 7 becomes "0".
1”, the output of the NAND circuit 8 becomes “0”, and the basic space 4
is selected and "1" is set in the address expansion register 6, the output of the NAND circuit 9 becomes "0" and the expansion space 5 is switched.

However, in such an address extension method, the address extension register 6 is
When the value of is changed, the space changes at that moment, which has the drawback of branching to an unexpected address in the space. In order to solve this problem, a method has been proposed in which a part of the memory space is used as a shared memory section and the addresses are switched (Japanese Patent Laid-Open No. 59-1989-1).
No. 60663, reference).

In other words, this address extension method uses a microprocessor that can only send out a limited number of unique addresses, a different memory device to which some of the addresses are assigned redundantly, and a microprocessor that can send out only a limited number of unique addresses. a register for setting designation information for operating only one of the memory devices, information for designating the memory device to be operated is set in advance in the register, and the duplicate address is sent by the microprocessor. At this time, only one memory device designated by the designation information set in the register is operated.

[0007]

[Problem to be Solved by the Invention] However, in this address extension method, since a shared memory section is provided, hardware for controlling the shared address is required outside the microprocessor, which increases costs. There was a problem. The present invention has been made in view of these conventional problems, and is an address extension method that can realize address extension without adding hardware and can branch to a desired address. is intended to provide.

[0008]

[Means for Solving the Problems] FIG. 1 is a diagram illustrating the principle of the present invention. In FIG. 1, reference numeral 12 is provided within the microprocessor 11 having a limited number of unique addressing signal lines, whose values can be changed to address the basic space 16 of the memory 15.
Address expansion registers 22 and 23 are used to expand the address space by switching between the expansion space 17 and the expansion space 17.
, 17 is a rewriting instruction for the address extension register 12 arranged in the fixed areas 20, 21 of .

[0009]

[Operation] A fixed area is provided in each of the basic space and expansion space of the memory, and a rewrite instruction that rewrites the value of the address expansion register is placed in the fixed area. Execute and switch address spaces.

In the switched space, a branch instruction is executed to branch to a desired address. In this way, it is possible to expand the address space and branch to a desired address without adding any hardware.

[0011]

Embodiments Hereinafter, embodiments of the present invention will be explained based on the drawings. 2 and 3 are diagrams showing an embodiment of the present invention. In FIG. 2, 11 is a microprocessor;
An address extension register 12 is provided within the microprocessor 11 .

The limited number of unique address lines of the microprocessor 11 is 16, and the address extension register 12 has 1 bit, and the most significant 1 bit switches the space. 13 is a NAND circuit into which the chip select signal (CS) of the microprocessor 11 and the output of the address expansion register 12 are inputted via the inverter 14; the "0" output of the NAND circuit 13 causes the basic space 16 of the memory 15 to be selected.

18 is a NAND circuit to which the chip select signal (CS) of the microprocessor 11 and the output of the address extension register 12 are input;
``The output switches to the extended space 17 of the memory 14. 19 is a program counter provided in the microprocessor 11, and the program counter 19 sets the address of the basic space 16 or extended space 17.

Fixed areas 20 and 21 are provided in the basic space 16 and the expanded space 17, respectively.
1, rewrite instructions 22 and 23 for the address extension register 12 are arranged, respectively. Next, the operation will be explained. When "0" is set in the address extension register 12, the output of the NAND circuit 13 becomes "0" and the basic space 16 is selected.

Now, consider switching from a general program in the basic space 16 to the extended space 17. In FIG. 3, a branch instruction to address ADRS01 is executed at address ADRS00, and an instruction to write "1" to address extension register 12 is executed at address ADRS01.

[0016] As a result, from the basic space 16 to the extended space 1
7 is performed, and the address A in the extended space 17 is
Control is transferred to DRS11. Address ADRS11
A branch instruction to the address ADRS10 stored in is executed, and the program in the extended space 17 is executed. Here, to return from the extended space 17 to the basic space 16, branch to address ADRS11+1, and
+1 executes the instruction to write “0” to the address extension register 12, and the address ADRS01+ of the basic space 16 is executed.
Return to 1 and set address ADR at address ADRS01+1
Execute a branch instruction to branch to S00+1. Then, it returns to address ADRS00+1.

In this way, the address rewriting instruction (2
By executing steps 2) and (23), it is possible to branch to a desired address, and address expansion can be achieved without adding hardware. Next, FIGS. 4 and 5 show another embodiment of the present invention. In FIG. 4, 31
is a rewriting monitoring section that monitors rewriting of the address extension register 12, and the rewriting monitoring section 31 includes a D flip-flop 32 and an exclusive OR circuit 33.

Reference numeral 34 denotes a space switching section that does not switch the space for the next one instruction, but selects the previous space.The space switching section 34 switches four AND circuits 35 to 38 and two NOR circuits 39 and 40. have. Further, as shown in FIG. 5, in the basic space 16 and the expansion space 17, rewrite instructions 41 and 42 for the address expansion register 12 are arranged, respectively, and a branch is executed at the address next to these rewrite instructions 41 and 42. Instructions 43 and 44 are arranged respectively.

When "1" is set in the address extension register 12, the output of the AND circuit 35 becomes "1", the extension space 17 is selected, and in the next cycle, the output of the AND circuit 37 becomes "1". ”, and basic space 16 is selected. Here, the value of address extension register 12 is “1”.
” to “0”, the output of the AND circuit 38 becomes “
1", the basic space 16 is selected, and no space switching is performed. Then, in the next cycle, the AND circuit 3
The output of 6 becomes “1”, and from the basic space 16 to the extended space 1
At 7, the space is switched.

In this embodiment, it is possible to branch to a desired address and expand the address space with only a small addition of hardware.

[0021]

Effects of the Invention As described above, according to the present invention, it is possible to expand the address space without adding any hardware or with only a small amount of hardware, and to obtain a desired address. can be branched into.

[Brief explanation of the drawing]

[Fig. 1] Diagram explaining the principle of the present invention

[Fig. 2] A diagram showing an embodiment of the present invention.

[Figure 3] Explanatory diagram of address space

FIG. 4 is a diagram showing another embodiment of the present invention.

[Figure 5] Explanatory diagram of address space

[Figure 6] Diagram showing a conventional example

[Explanation of symbols]

11: Microprocessor 12: Address extension register 13, 18: NAND circuit 14: Inverter 15: Memory 16: Basic space 17: Expansion space 19: Program counter 20, 21: Fixed area 22, 23: Rewrite instruction 31: Rewriting monitoring section 32: D flip-flop 33: Exclusive OR circuit 34: Space switching section 35-38: AND circuit 39, 40: Noah circuit 41, 42: Rewrite instruction 43, 44: Branch instruction

Claims (2)

[Claims] [Claim 1] By changing the value of an address extension register (12) provided in a microprocessor (11) having a limited unique addressing signal line, a memory (15) can be used.
Switch between the basic space (16) and extended space (17),
In the address expansion method for expanding the address space, the fixed areas (20) and (2) of each of the spaces (16) and (17) are
1) An address extension method characterized in that instructions (22) and (23) for rewriting the address extension register (12) are placed in the address extension register (12). [Claim 2] By changing the value of an address expansion register (12) provided in a microprocessor (11) having a limited unique addressing signal line, the memory (15)
Switch between the basic space (16) and extended space (17),
In an address expansion method for expanding an address space, instructions (41), (42) for rewriting the address expansion register (12) are provided in each of the spaces (16), (17);
A branch instruction (
43) and (44), a rewrite monitoring unit (31) that monitors changes in rewriting of the address extension register (12), and a space that prevents space switching in the next cycle after rewriting. Switching part (3
4) An address extension method characterized by providing the following.