JPH02249028A - Micro program controller - Google Patents

Abstract

PURPOSE:To reduce the number of bits in a RAM decoder and to reduce the probability of the occurrence of a fault in a controller caused by the fault of RAM by adding a constant to the address of E1 instruction with an adder and generating the address of an E2 instruction. CONSTITUTION:At the time of reading the first step of a series of micro instructions for executing the instruction from a control storage part 14, the address supplied with an address supply means 101 is selected. At the time of reading the micro instruction of a second step in a series of the micro instructions for executing the instruction from the control storage part 14, the constant is added to the address of the E1 instruction to generate the address of the E2 instruction, and the address supplied with an addition means 23 is selected. At the time of reading the micro instruction subsequent to the third step of a series of the micro instructions for executing the instruction from the control storage part 14, the address shown by the branch address field of the micro instruction held in a read register 15 is selected and used. Thus, the number of the bits in RAM is reduced and the probability of the occurrence of the controller caused by the fault of RAM is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an information processing device, and particularly to generation of a read address of a control memory in a microprogram control device.

[Conventional technology]

In microprogram controllers, for ease of testing the memory storing the microprogram and for delay times, the address of the control memory is directly specified by the output of the address register, and the microinstruction read from the control memory is Once received in the read register, it may be configured to be used for control.

When a microinstruction branches in a microprogram control device having such a configuration, the microinstruction specifies the address of a microinstruction two steps later. This is because the address indicated by the address field of the microinstruction is transferred from the read register to the address register and then used to access the control memory.

An example of a conventional microprogram control device having such a configuration is shown in FIG. 3 and will be described.

In the figure, 11 is a RAM decoder, and the toy decoder 11 is an operating gy code (
Therefore, the address of the first step microinstruction (hereinafter referred to as E1 instruction) of a series of microinstructions for executing that instruction is output to the E1 address signal line 101, and The address of the second step microinstruction (hereinafter referred to as E2 instruction) is output to the E2 addressing line 111, and when the instruction is executed as a one-step microinstruction, the address is output to the IT instruction instruction signal line 102. This is a decoder using a RAM that outputs "1" and outputs rOJ to the IT command instruction signal line 102 when a microinstruction of two or more steps is required. 12 is a selector, and this selector 12 receives the signal #
When 106 is "1", the address of the E1 instruction supplied from the RAM decoder 11 via the E1 address signal line 101 is selected, and when the signal line 108 is "1", the address of the E2 instruction held in the E2 address register 20 is selected. It is a selector that selects an address and, when the signal line 110 is "1", selects the branch address field of the microinstruction held in the read register 15.

Reference numeral 13 denotes an address register that holds the address selected by the selector 12, and the output of this address register 13 directly accesses the control storage section 14. And this? l! II l+W 1m'flE 14 is a memory that stores a microprogram. Reference numeral 15 denotes a read register that holds microinstructions read from the control storage section 14.

16 is an 0R-NOR gate that outputs the logical sum (OR) of the output of the flip-flop (F/F) 21 and the start notice signal line 105 to the signal line 106, and also outputs the NOR to the signal line 107; 18 is an inverter that inverts and outputs the output of F/F 21, and 18 is the logical product (AND) of the output of the inverter 17 and the start signal line 104, and is connected to the signal line 1.
08, and also output NAND to signal line 10.
AND-NAND gate that outputs to 9, 19 is signal line 1
This is an MO gate that outputs the AND of 07 and the signal line 109 to the signal line 110.

The E2 address register 20 is a register that holds the address of the E2 instruction output from the RAM decoder 11. F/F' 21 is a flip-flop that holds the IT command instruction signal output from the RAM decoder 11. And this E2 address register 20 and F/F 21
are both updated when the logical sum of the start notice signal line 105 and the F/F 21 is "1". Further, the OP code sent from the advance control unit via the OP code line 112 is updated by the logical sum of the start notice signal line 105 and Fall' 21, and the E1 command is read from the control storage unit 14.
Before the clock cycle, the address of the E1 instruction, the address of the E2 instruction, and information as to whether the instruction will be executed in one step are read from the RAM decoder 11.

Next, reading of microinstructions in the microprogram control IT shown in FIG. 3 will be explained with reference to FIG. 4.

FIG. 4 is a time chart showing the microinstruction reading operation in the microprogram control device shown in FIG. Signal line 101, (c)
is the E2 address signal line 111, (d) is the F/F 21, (
e) is the E2 address register 20, (f) is the address register 13, (g) is the read register 15, (h) is the start notice signal line 105, (i) is the start signal line 1
04 is shown.

Now, the penultimate instruction (hereinafter referred to as EA) of a series of microinstructions for executing instruction A is written to the read register 15.
The address register 13 holds the address of the last instruction (hereinafter referred to as the EAn instruction) in a series of microinstructions for executing instruction A. shall be taken as a thing.

First, the EAn-1 command is sent to the start notice signal line 105 with "
1” and outputs “0” to the start signal line 104. At this time, since the instruction A is executed by a microinstruction of two or more steps, "0" is held in the F/F 21. In addition, the command A is connected to the OP code signal line 112.
Since the OP code of instruction B to be executed next is output, the E1 address signal line 101 contains a microinstruction (hereinafter referred to as EB1 instruction) of the first step of a series of microinstructions for executing instruction B. ) address is output.

Here, assuming that instruction B is executed by only one step of microinstruction, "1" is output to the IT instruction instruction signal line 102. Selector 12 is signal line 106
is "1", so the address of the FBI instruction is selected.

Next, at the timing when the EAn instruction is held in the read register 15, the address of the FBI instruction is held in the address register 13, and "1" of the IT instruction instruction signal line 102 is held in the F/F 21. At this time, the OP code of the next instruction C is output to the OP code signal line 112, so the OP code of the next instruction C is output to the E1 address signal line 101. (referred to as an instruction) is output, and the address of E
Similarly, the address of the second step microinstruction (hereinafter referred to as EC2 instruction) is output to the 2-address signal line 111, and "0" is output to the IT instruction instruction signal line 102. However, it is assumed that instruction C is executed by a microinstruction of four or more steps.

Then, the EAn instruction held in the read register 15 outputs "0" to the start notice signal line 105 and "1" to the start signal line 104, but the F/F 21 outputs "1".
” is output, so the signal line 106 becomes “1”.

When the signal line 108 becomes "0", the selector 12 selects the E1 address, that is, the address of the EC1 instruction. E
At the timing when the B1 instruction is held in the read register 15, the address of the Ecl instruction is held in the address register 13, "0" is held in the F/F 21, and the E2
The address of the 11Ec2 instruction is held in the address register 20. FBI held in read register 15
The command outputs "0" to the start notice signal line 105 and "1" to the start signal line 104. Also, F/F
21 outputs "0", the signal line 106 becomes "0", and the signal line 108 becomes "1", so the selector 12 selects the E2 address, that is, the address of the EC2 instruction. At the timing when the Ecl instruction is held in the read register 15, the address of the EC2 instruction is held in the address register 13. F/F 21 and E2 address register 20 are not updated. And read register 1
The Ecl command held at 5 is connected to the start signal line 104.
In order to output "O" to the start notice signal line 105, the selector 12 selects the branch address. Thereafter, the selector 12 selects a branch address until the microinstruction held in the readout register 15 outputs a start notice signal, so the readout address of the control memory is determined by the microinstruction itself. In addition, until the start notice signal is output, F/F 21 and E2 address register 2
0 is not updated.

[Problem to be solved by the invention]

In the conventional microprogram control device described above, E2
The instruction address is stored in RAM according to the instruction OP code.
Since the decoder supplies the RAM, the number of bits in the RAM is large, and the number of LSIs in the RAM is also large.Therefore, there is a problem in that there is a high probability of equipment failure due to a failure of the RAM.

[Means to solve the problem]

The microprogram control system of the present invention includes a control i storage section that stores a microprogram, a read register that holds microinstructions read from the control storage section, and an address that holds a read address of the control storage section. a register, an address supply means for supplying an address of a first step microinstruction of a series of microinstructions for executing an instruction, an addition means for adding a constant value to an address held in the address register, and an instruction. When reading the first step of a series of microinstructions for executing an instruction from the control storage section, the address supplied by the address supply means is selected, and the second step of a series of microinstructions for executing an instruction is selected. When reading a microinstruction of a step from the control storage section, the address supplied by the addition means is selected, and the microinstruction after the third step of a series of microinstructions for executing the instruction is read out from the control storage section. When reading from the microinstruction register, the microinstruction controller is equipped with address selection means for selecting an address indicated by the branch address field of the microinstruction held in the read register and outputting the selected address to the address register.

[Effect]

In the present invention, an adder adds a constant C to the address of the E1 instruction to generate the address of the E2 instruction.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail based on the drawings.

FIG. 1 is a block diagram showing one embodiment of a microprogram controlled snowmaking system according to the present invention.

In FIG. 1, the same reference numerals as in FIG.
If the instruction is executed by a microinstruction of one step, it outputs “1” to the IT instruction instruction signal line 102, and if it is executed by a microinstruction of two or more steps, it outputs “0”. This RAM decoder 22 is a RAM decoder using a RAM that outputs . . 2
Reference numeral 3 denotes an adder that adds a constant C to the address held in the address register 25, and this adder 23 constitutes an addition means that adds a constant value to the address held in the address register 25. 24, the signal line 106 is
1”, E1 address code line 1 from fare decoder 22
Selects the address of the E1 instruction supplied by 01, selects the address supplied by the adder 23 when the signal line 108 is "1", and holds it in the read-1 raster 15 when the signal line 110 is "1". This selector selects the branch address field of the microinstruction being executed.

25 is an address register that holds the read address of the open side 1 storage section 14, and this address register 25 is a register that holds the address selected by the selector 24, and the control storage section 14 is directly accessed by the output of this register. .

And 0R-NOR gate 16. Inverter 17°A
ND-NAND game) 18, AND gate 19 and F
/F21 and the selector 24 select the address supplied by the address supply means when reading the first step of a series of microinstructions for executing an instruction from the control storage unit 14, and execute the instruction. The second step microinstruction of the series of microinstructions is stored in the control storage unit 1.
4, the address supplied by the addition means is selected, and the microinstructions from the third step onward of the series of microinstructions for executing the instructions are read from the control storage unit 1.
When reading from the microinstruction 4, the microinstruction register 25 selects the address indicated by the branch address field of the microinstruction held in the read register 15 and outputs the selected address to the address register 25.

In the embodiment shown in FIG. 1, a case will be considered in which instructions A, B, and C are executed in sequence, similar to the description of the prior art described above.

In the prior art shown in FIG. 3, the address of the Ec2 instruction is RA
After being output from the M decoder 11, it is temporarily held in the E2 address register 20 and then held in the address register 13, whereas in the embodiment shown in FIG. The difference is that it is generated by adding a constant C to , but otherwise the operation is exactly the same. (See Fig. 2) Fig. 2 is a time chart showing the read operation in the microprogram control device shown in Fig. 1, and (a) is an IT
This shows the command instruction signal line 102, and cb) is E.
1 address signal line 101, (C) is F/F 21, (d
) is the adder 23, (e) is the address register 25, (f
'1 indicates the read register 15, (g) the start notice signal line 105, and (h) the start signal line 104.

+C in the adder 23 shown in (d) represents adding a constant C to the address.

〔Effect of the invention〕

As explained above, the present invention adds the constant C to the address of the E1 instruction in an adder to generate the address of the E2 instruction, thereby reducing the number of bits of the RAM decoder and
This has the effect of realizing a microprogram control device with a low probability of occurrence of device failure due to failure of M.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of a microprogram control device according to the present invention, FIG. 2 is a time chart showing a microinstruction read operation in the microprogram control device shown in FIG. A block diagram showing an example of a microprogram control device, FIG.
3 is a time chart showing a microinstruction read operation in the microprogram control device shown in the figure. 14... φ Control storage section, 15... Read register, 16... 0R-NOR gate, 17000. Inverter, 18...-AND/NAND gate, 19
・-・・AND gate, 21・・・・Flip-flop, 22・・・RAM decoder, 23・
...Fist adder, 24...e selector, 25...address register. Patent applicant: NEC Corporation Kofu NEC Corporation

Claims (1)

[Claims] a control memory section for storing a microprogram, a continuation register for holding microinstructions read from the control memory section, an address register for holding a read address of the control memory section, and a series of instructions for executing instructions. address supply means for supplying the address of the microinstruction of the first step of the microinstruction; and addition means for adding a constant value to the address held in the address register;
When reading the first step of a series of microinstructions for executing an instruction from the control storage section, an address supplied by the address supply means is selected, and the first step of a series of microinstructions for executing an instruction is selected. When reading the second step microinstruction from the control storage section, the address supplied by the adding means is selected, and the microinstruction in the third and subsequent steps of the series of microinstructions for executing the instruction is selected. and address selection means for selecting an address indicated by a branch address field of a microinstruction held in the read register and outputting the selected address to the address register when reading the microinstruction from the control storage section. Microprogram control device.