JPH0513456A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To enable a semiconductor device of LDD structure to be manufactured through a technique similar to a T gate method and set large in an optional range of distance between a gate electrode and a source.drain region. CONSTITUTION:Three dummy gates 4a, 5a, and 6a are provided onto an N-type active layer 3 of a GaAs substrate 1, where the gates are set smaller in width as they are located closer to the surface of the substrate 1. N-type ions of high concentration are implanted using the dummy gates 4a, 5a, and 6a as a mask to form an N<+> implanted layer 8. In succession, after the uppermost dummy gate 6a is removed, ions are implanted using the dummy gates 4a and 5a as a mask to form an N' layer 9 smaller than the N<+> implanted layer 8 in dose. Lastly, a Schottky electrode 13a identical to the dummy gates 4a and 5a in shape is provided.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device. Specifically, the present invention relates to a method for manufacturing a semiconductor device having an LDD structure.

[0002]

2. Description of the Related Art Conventionally, LDD (Lightly Doped Drai)
n) A semiconductor device having a structure such as MESFET or HEMT has been proposed. As shown in FIG. 22D, this is an n-type active layer (channel region) under the gate electrode 53.
52 and an n ⁺ implantation layer (source / drain region) 55 having a high impurity density, an n ′ layer 56 having an impurity density intermediate between the two regions is formed.
It is intended to suppress the short channel effect while increasing the mutual conductance g _m of ESFET or the like.

As a process for forming an LDD structure, a heat resistant gate method and a dummy gate method (T-type gate method, sidewall gate method) are known.

22A to 22D show a manufacturing process of a GaAs MESFET having an LDD structure by a heat resistant gate method. First, as shown in FIG. 22A, the semi-insulating Ga
An n-type active layer 52 is formed by ion implantation in the element formation region on the surface of the As substrate 51, and a gate electrode 53 is provided on the n-type active layer 52 with a heat resistant metal. Furthermore, FIG.
As shown in (b), sidewalls 54 made of an insulating film are provided on both side surfaces of the gate electrode 53, and the gate electrode 53 and the sidewalls 54 are used as a mask to perform ion implantation into the element formation region of the GaAs substrate 51 to perform n-type activation. An n ⁺ implantation layer 55 is formed on both sides of the layer 52. Next, after removing the sidewalls 54, ions are implanted into the element formation region using the gate electrode 53 as a mask, and as shown in FIG. 22C, a space between the n ⁺ implantation layer 55 and the n-type active layer 52 is formed. An n'layer 56 having an intermediate impurity density is formed. After that, the source electrode 57 and the drain electrode 58 are formed on the n ⁺ implantation layer 55, and heat treatment for alloying is performed to manufacture a GaAs MESFET having an LDD structure as shown in FIG.

[0005]

In the heat-resistant gate method as described above, the length of the n'layer must be adjusted by the thickness of the sidewall, but the sidewall is formed on the gate electrode wall portion. The thickness of the n ⁺ implantation layer (particularly, the thickness of the n ⁺ -implanted layer (particularly, It was difficult to secure a sufficient distance between the drain side) and the gate electrode. Further, since it is necessary to select a heat resistant metal as the gate electrode material, there is a drawback that the selection range of the material of the gate electrode is limited.

Also, in the side wall gate method, it is difficult to form a thick side wall, so that it is difficult to secure a sufficient distance between the n ⁺ implantation layer (particularly on the drain side) and the gate electrode. Furthermore, in the sidewall gate method, LD
There is a drawback that the process for realizing the D structure is extremely complicated.

Further, in the standard process of the conventional T gate method,
It was impossible to realize the LDD structure due to the process.

The present invention has been made in view of the drawbacks of the above conventional example, and an object thereof is to enable the manufacture of a semiconductor device having an LDD structure by a method similar to the T gate method, This is to allow a greater degree of freedom in the distance between the electrode and the source / drain region.

[0009]

In the method of manufacturing a semiconductor device according to the present invention, an ion implantation region having a lower impurity density than the source and drain regions is provided between the source and drain regions and the side wall of the gate electrode. In the method of manufacturing a semiconductor device having the LDD structure, three layers of dummy gates are stacked on the surface of the channel region of the semiconductor substrate so that the width of the dummy gates in each layer becomes smaller on the side closer to the semiconductor substrate.
Ion implantation is performed on both sides of the channel region by using the dummy gate of the layer as a mask to form source and drain regions, and then ion implantation is performed on both sides of the channel region by using the two-layer dummy gate from which the uppermost dummy gate is removed as a mask. Is performed to form the ion-implanted region having the low impurity density, and a gate electrode having the same shape as the two-layer dummy gate is provided on the surface of the channel region.

[0010]

In the present invention, by using the dummy gates of three layers having different widths, the LD can be manufactured by a relatively simple process.
Since the semiconductor device having the D structure can be manufactured, the short channel effect can be suppressed while increasing the mutual conductance g _m .

In addition, for example, when a three-layer dummy gate is formed by dry etching or the like, the width of the dummy gate of each layer can be greatly varied by selecting the optimum conditions, and therefore the dummy gate of the uppermost layer can be made different. By increasing the width, the distance between the gate electrode and the source / drain regions can be increased.

The material of the gate electrode is not limited to the heat resistant metal.

Further, since the cross-sectional shape of the gate electrode is a mushroom type so-called "mushroom gate", the gate resistance is reduced, and it is also very effective in reducing the noise of the field effect semiconductor device.

[0014]

1 to 11 show one embodiment of the present invention,
It is sectional drawing which shows the main processes for manufacturing a self-aligned MESFET using the ion implantation method.

First, the field portion of the semi-insulating GaAs substrate 1 is covered with a photoresist 2, and the photoresist 2 is covered.
Using as a mask, selective ion implantation is performed on the surface of the GaAs substrate 1 to form an n-type active layer (channel region) 3 [FIG. 1].

Then, after removing the photoresist 2,
On the surface of the GaAs substrate 1, a nitride film 4 such as SiNx and Si
An oxide film 5 of O ₂ or the like is continuously formed by using a plasma CVD apparatus, and further, a metal film 6 such as an aluminum film is formed at a substantially central portion of the n-type active layer 3 by a lift-off method or etching [FIG. ]. The nitride film 4, the oxide film 5 and the metal film 6 have different etching ratios from each other, and the etching ratios are gradually reduced from the lower layer to the upper layer.

Next, by anisotropic reactive ion etching (RIE) using a CHF ₃ / O ₂ system gas,
Three-layer dummy gates 4a, 5a, 6a having a structure as shown in FIG.
make.

Next, the nitride film 4 and the oxide film 5 are isotropically etched by reactive ion etching (RIE) using a gas such as CF ₄ / O ₂ and the first layer dummy gate 4 is formed.
a, second layer dummy gate 5a and third layer dummy gate 6
get a. At this time, the first layer dummy gate (SiNx film) 4a is adjusted by adjusting the amount of N ₂ added in the gas.
And the etching ratio of the second-layer dummy gate (SiO ₂ film) 5a can be changed, the width of the first-layer dummy gate 4a (width in the gate length direction) is shortest, and the width of the third-layer dummy gate 6a is shortest. Long three-layer dummy gates 4a, 5a, 6
a can be formed (FIG. 4). Actually, the etching rate of the third-layer dummy gate 6a is extremely smaller than that of the first-layer and second-layer dummy gates 4a and 5a.
It suffices to consider only a, which is not so difficult. After that, a photomask 7 is formed in the field portion, high-concentration n-type ion implantation is performed using the photomask 7 and the three-layer dummy gates 4a, 5a, and 6a as masks, and n ⁺ implantation layers (source and drain regions) 8 is formed.

As shown in FIG. 5, the third-layer dummy gate 6a is removed by wet etching with a phosphoric acid-based etching solution, and then the photomask 7 and the two-layer dummy gates 4a and 5a are used as masks. Ion implantation with a dose slightly smaller than that of the ⁺ implantation layer 8 is performed to form an n'layer 9 between the n ⁺ implantation layer 8 and the n-type active layer 3. Then, after removing the photomask 7, As partial pressure of 3 Torr, 8
Capless annealing is performed for 15 minutes at 50 ° C. to activate each region.

Next, by photolithography process,
After forming an ohmic electrode (source electrode and drain electrode) 10 of uGe / Ni / Au on the n ⁺ implantation layer 8 and alloying the same [FIG. 6], the viscosity of the photoresist 11 and the spin coating The photoresist 11 is coated on the surface of the GaAs substrate 1 so as to cover the dummy gates 4a and 5a and the ohmic electrode 10 by adjusting the rotation speed [FIG. 7]. Subsequently, the photoresist 11 is etched by reactive ion etching using O ₂ gas until the top surface of the second-layer dummy gate 5a is exposed [FIG. 8].

Next, using the photoresist 11 as a mask, the first and second layer dummy gates 4a and 5a are etched and removed by reactive ion etching, and the traces after the dummy gates 4a and 5a are removed in the photoresist 11 are removed. A mushroom-shaped contact hole 12 is formed [FIG. 9]. After that, Ti / Pt / Au Schottky electrode metal 13 is deposited [FIG. 10], and then the photoresist 1 is formed.
1 is removed and a mushroom-shaped gate electrode 13a is formed by the lift-off method [FIG. 11].

According to the above manufacturing method, however, the gate electrode 13a can be formed by self-alignment, so that the gate electrode 13a having a short gate length can be accurately formed and the mutual conductance g _m can be increased. .. Moreover, the gate electrode 13a and the n ⁺ implantation layer 8
Since the n'layer 9 is formed between the two to form the LDD structure,
At the same time, the short channel effect can be prevented.

12 to 21 are sectional views showing a method of manufacturing a semiconductor device according to another embodiment of the present invention. Also in this embodiment, first, the GaA having the n-type active layer 3 formed thereon is formed.
A nitride film 4, an oxide film 5 and a metal film 6 are formed on the surface of the substrate 1 [FIGS. 12 and 13].

Next, by anisotropic reactive ion etching using a CHF ₃ / O ₂ system gas, the nitride film 4 is formed.
Are processed to leave dummy gates 4a, 5a, 6a having a three-layer structure as shown in FIG.

Further, a nitride film 4 such as a SiNx film is formed by about 10
The nitride film 4 and the oxide film 5 are isotropically etched by reactive ion etching so as to leave 00Å. By this step, three layers of dummy gates 4a, 5a, 6a having different widths in the gate length direction are obtained, and at the same time, the protective film 4b is formed by the remaining portion of the nitride film 4 [FIG. 15]. The reactive ion etching at this time is isotropic etching using CF ₄ + O ₂ plasma, and the end point of the etching depth is detected by the laser interference method of the monitor part.

After that, high-concentration n-type ion implantation is performed using the photomask 7 and the three-layer dummy gates 4a, 5a, and 6a as masks to form an n ⁺ -implanted layer 8 [FIG. 16], and wet etching is performed to form a first layer. After removing the three-layer dummy gate 6a, the photomask 7 and the two-layer dummy gates 4a,
Ion implantation with a dose slightly smaller than that of the n ⁺ implantation layer 8 is performed using 5a as a mask to form an n'layer 9 [FIG.
7].

Then, after removing the photomask 7, N
₂ Annealing is performed at 850 ° C. for 15 minutes in an atmosphere to activate each region.

After partially removing the protective film 4b and forming the ohmic electrode 10 on the n ⁺ implantation layer 8 [FIG. 18],
A photoresist 11 is coated on the surface of the GaAs substrate 1 [FIG. 19], and then the photoresist 11 is etched to expose the top surface of the second-layer dummy gate 5a, and the photoresist 11 is used as a mask by reactive ion etching. First layer and second layer dummy gates 4a, 5
A is removed by etching to form a mushroom-shaped contact hole 12 [FIG. 20], and a gate electrode 13a made of a metal for a Schottky electrode is formed by a lift-off method [FIG. 21].

According to this embodiment, since the nitride film 4 for dummy gate can be used as the protective film 4b for annealing, the annealing can be performed in the N ₂ atmosphere,
It is not necessary to use an atmospheric gas containing toxic As.

[0030]

According to the present invention, a semiconductor device having an LDD structure can be manufactured by a relatively simple process, and the distance between the gate electrode and the source / drain region can be made larger than that of the conventional one. The suppression of the channel effect and the reduction of the source resistance (increase of the mutual conductance g _m ) can both be achieved, and a highly reliable field effect type semiconductor device having high mutual conductance can be manufactured.

The material of the gate electrode is not limited to heat resistant metal.

Furthermore, since the gate electrode serves as a mushroom gate, the gate resistance is reduced and the noise is greatly reduced.

[Brief description of drawings]

1 to 11 are cross-sectional views showing a method of manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a partial diagram of FIG.

FIG. 3 is a partial diagram of FIG.

FIG. 4 is a partial diagram of FIG.

5 is a partial diagram of FIG. 1. FIG.

FIG. 6 is a partial diagram of FIG. 1.

FIG. 7 is a partial diagram of FIG. 1.

FIG. 8 is a partial diagram of FIG.

FIG. 9 is a partial diagram of FIG.

FIG. 10 is a partial diagram of FIG. 1.

FIG. 11 is a partial diagram of FIG. 1.

12 to 21 are sectional views showing a method of manufacturing a semiconductor device according to another embodiment of the present invention.

13 is a partial diagram of FIG.

FIG. 14 is a partial diagram of FIG.

FIG. 15 is a partial diagram of FIG.

16 is a partial diagram of FIG.

FIG. 17 is a partial diagram of FIG.

FIG. 18 is a partial diagram of FIG. 12.

FIG. 19 is a partial diagram of FIG. 12.

20 is a partial diagram of FIG.

FIG. 21 is a partial diagram of FIG. 12.

22A to 22D are sectional views showing a method for manufacturing a semiconductor device according to a conventional example.

[Explanation of symbols]

1 GaAs substrate 3 n-type active layer 4a first layer dummy gate 5a second layer dummy gate 6a third layer dummy gate 8 n ⁺ injection layer 9 n'layer 10 ohmic electrode 13a Schottky electrode

Claims (1)

Claim: What is claimed is: 1. A method of manufacturing a semiconductor device having an LDD structure in which an ion-implanted region having a lower impurity density than that of the source and drain regions is provided between the source and drain regions and a sidewall portion of the gate electrode. In addition, three layers of dummy gates are stacked on the surface of the channel region of the semiconductor substrate such that the widths of the dummy gates of the respective layers are sequentially shortened on the side closer to the semiconductor substrate, and the channel region is formed using the three layers of dummy gates as a mask. After the source and drain regions are formed by implanting ions on both sides of the channel, ion implantation is performed on both sides of the channel region using the two layers of dummy gates, which have been removed from the uppermost dummy gate, as masks. A semiconductor characterized by forming an injection region and further providing a gate electrode having the same shape as the two layers of dummy gates on the surface of the channel region. Method of manufacturing location.