JPH04167530A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To avoid the deterioration in inverse breakdown strength by a method wherein an n<+> type conductor layer as well as a p-type conductor layer are formed while a gate metal is provided. CONSTITUTION:A high impurity concentration n<+> type conductor layer 23 is formed on an n-type conductor layer 22 previously formed on a semiinsulating compound semiconductor substrate 21. Next, a window part 24A is made in a diffused mask layer 24 formed on the layer 23 and then an impurity is diffused in the n-type conductor layer 22 from the window part 24A through the n<+> type conductor layer 23 so as to form a P<+> type conductor region 26. Next, part of the diffused mask layer 24 around a gate metal 27 formed on the region 26, n<+> type conductor layer 23 and the n-type conductor layer 22 is removed leaving the gate metal 27 and regions which are to serve as a source and a drain to form an insulating protective layer 29 on the whole exposed surface. Furthermore, window parts 29A, 29B are made in the regions to serve as the source and drain so as to form a source electrode 30 and a drain electrode 31. Through these procedures, the variation in saturated current can be reduced thereby enabling the deterioration in reverse breakdown strength to be avoided.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of manufacturing a junction field effect transistor (J-FET).

(Prior Art) A semiconductor device manufactured by a conventional manufacturing method will be described.

FIG. 2 is a cross-sectional process diagram for explaining the manufacturing process of a conventional semiconductor device (junction field effect transistor). In the figure, 1 is an insulating compound semiconductor substrate (semi-insulating GaAs substrate), 2 is a buffer layer, 3 is a conductive layer (n-type GaAs epitaxial layer), 3A is an inner wall surface (inside), and 3B is a Inside! Bottom surface (part), 4 is source electrode,
5 is a drain electrode, 6.11 is a gate portion, 7 is a first insulating layer, 9 is an opening, and lO is a second insulating layer.

This will be explained below with reference to FIG.

Step 1: A buffer layer 2 is formed on the semi-insulating GaAs substrate 1.
and n-type GaAs substrate 3 are laminated in order, and further n-type GaAs substrate 3 is laminated in order.
A Si3N4 film 7 having a thickness of approximately 0.2 μm is formed as an insulating film on the As substrate 3.

Step 2: A photoresist film 8 formed by photolithography, which is used in normal semiconductor device manufacturing processes, is made of Si 3 N.
After forming the a film 7 to a desired thickness, the gate 'r4[
i! The photoresist film 8 corresponding to the portion where the photoresist film 8 is to be formed is removed by etching. Furthermore, by wet etching or reactive ion etching, S i 3 N A ! corresponding to the portion where the gate portion is to be formed is etched. 117 is removed to form an opening 9 with a width of about 1 μm.

Step 3: Using Si3NtM7 as an etching mask, etching the n-type GaAs substrate 3 in the area where the gate portion is to be formed to a depth of about 0.4 μm from the top surface using a citric acid-based etching solution. .

Step 4, surface of Si 3 N 4 film 7 and n-type GaA
A second S layer is formed as an insulating film on the inner wall surface 3A of the S substrate 3.
An i 3 Na film 10 is formed.

The thickness of S i 3 N 41Ij10 is S i 3 N
a film 7 and time.

Step 5: By using an anisotropic reactive ion etching method, Si 3Na is etched until only the previously etched portion where the gate portion is to be formed (the bottom surface 3B of the inner wall of the n-type GaAs substrate 3) is opened. The film 10 is etched.

Step 6: An impurity such as Zn is diffused by selective thermal diffusion to form a gate portion 11 which is a P-type GaAs layer extending from the bottom surface 3B of the inner wall of the n-type GaAs substrate 3 to the inside thereof. Here, the thickness of the Si3N4 film 10 may be a thickness that can prevent diffusion of impurities.

Step 7: After opening a window in each part of the Si3NtM10 where the source electrode 4 and drain electrode 5 are to be formed by wet etching or reactive ion etching, the source electrode 4 and the train electrode 5 are formed by vacuum evaporation. .

Step 8: After forming the photoresist film 12 on the surface of the Si 3 Na film 7, only the necessary portions are removed by etching.
After this, the surface of the photoresist film 12, Si 3 Na
Gold beryllium alloy (AuBe), gold zinc alloy (Au
An ohmic metal 13 such as Zn) is deposited.

Step 9: In order to leave only the ohmic metal 13 deposited on the gate portion 11, the remaining portions are removed by wet etching, reactive ion etching, or the like.

In this manner, a conventional junction field effect transistor can be manufactured through the steps 1 to 9 described above.

Further, FIG. 3 is a cross-sectional view showing another conventional semiconductor device of 41N structure, in which 3-1 is an n+ type conductive layer (
3-2 is an n-type conductive layer (n-type GaAs epitaxial layer), and FIG. 2 shows an n-type conductive layer on the semi-insulating compound semiconductor substrate 1. FIG. 3 shows a structure in which an n-type conductive layer and an n-type conductive layer are laminated on a semi-insulating compound semiconductor substrate 1, and the other layers are laminated on a semi-insulating compound semiconductor substrate 1.
The configuration is the same as that shown in the figure, and the explanation will be omitted.

(Problems to be Solved by the Invention) As described above, when an n-type conductive layer is used in the semiconductor device 1, it is necessary to increase the layer thickness in order to reduce the source resistance Rs6. When an n-type conductive layer is laminated, etching is performed from the n-type conductive layer to the n-type conductive layer, being careful not to cause the n-type conductive layer to come into contact with the Zn diffusion layer and deteriorate the withstand voltage between the source and gate. There is a need.

Furthermore, the portion of the P-type conductive layer other than the portion in contact with the n-type conductive layer is removed before forming the P-type conductive layer and diffused into the n-type conductive layer, resulting in uneven etching. Due to the saturation of the FET, the fluctuation of the flow increases. Further, there was a problem that the diffusion mask was likely to crack at the stepped portion of the underlying surface on which the diffusion mask layer was formed.

Furthermore, when forming the P-type conductive layer by diffusion, it is necessary to determine the etching depth in consideration of the thickness of the n+-type conductive layer.

(Means for Solving the Problems) The present invention has been made to solve the above problems, and includes a step of forming an n-type conductive layer on a semi-insulating compound semiconductor substrate, and a step of forming an n-type conductive layer on the n-type conductive layer. forming an n-type conductive layer with a high impurity concentration; forming a diffusion mask layer on the n-type conductive layer; forming a window in the diffusion mask layer; a step of diffusing an impurity into the n-type conductive layer through the n-type conductive layer to form a P-type conductive region; a step of forming a gate metal on the P-type conductive region; the gate metal; removing a portion of the diffusion mask layer, the 'nn pear-shaped conductive layer, and the n-type conductive layer around the gate metal, leaving portions that will become the source and drain masked with a photoresist layer; a step of forming an insulating protective layer on the entire surface exposed in the process; a step of forming a window in a portion of the insulating protective layer that will become a source and a drain; and a step of forming a source electrode and a drain electrode in the window. It is an object of the present invention to provide a method for manufacturing a semiconductor device characterized by the following.

(Example) The use of an n-type conductive layer to reduce the contact resistance of an electrode to an n-type conductive layer of a semiconductor device is an important technique for improving the performance of a semiconductor device 1.

For example, in a J-FET, reducing contact resistance has a large effect on reducing resistive noise.

This n+ type conductive layer uses a substrate epitaxially grown in consideration of reducing the noise of the semiconductor device, and it is necessary to form a P type conductive layer, electrodes, etc. after forming the n+ type conductive layer on the entire surface of the wafer. However, the P-type conductive layer (gate part) and the n
Direct seeding contact between the ten-shaped conductive layers must be avoided because the reverse withstand voltage between the gate and source drain of the FET will deteriorate.

The present invention provides a method for manufacturing a semiconductor device that has an n÷-type conductive layer and a P-type conductive layer, prevents deterioration of reverse breakdown voltage of an FET, and has good characteristics by having a gate metal. It is something to do.

FIG. 1 is a process diagram illustrating an embodiment of the method for manufacturing a semiconductor device of the present invention, in which 21 is a semi-insulating compound semiconductor substrate (semi-insulating GaAs substrate), 22 is an n-type GaAs epitaxial layer, and 23 is an n-type GaAs epitaxial layer. Ten-type GaAs epitaxial layer, 24
24A is a diffusion mask layer, 24A is a window portion, 26 is a P-shaped gate diffusion layer, 27 is a gate metal, 28 is a resist pattern,
29 is an insulating protective layer, 30 is a source electrode, and 31 is a drain electrode.

The process will be explained below using the same process diagram.

Step 1: Semi-insulating compound semiconductor substrate (semi-insulating GaAs
An n-type GaAs epitaxial layer (III
Thickness 0.1-0.4 μm, No. 1-3 X10'7
] -3) 22 and an n + type GaAs epitaxial layer (
Film thickness 0.1-0.4, LZ m, N O2X I
A silicon nitride film is formed as a diffusion mask layer 24 on this n+ type GaAs epitaxial layer 23 by plasma CVD or the like.

Step 2: A window is opened in a part of the diffusion mask layer 24 by a photoetching method, a dry etching method, etc. to form a window portion 24.
A is formed, and a P-type forming impurity such as Zn is passed through the window 24A through the n+ type GaAs epitaxial layer 23 into the n-type GaAs epitaxial layer 22.
P+ consisting of P-type GaAs (N^101B~1020 C11-3) is thermally diffused into
A type gate diffusion portion 26 is formed. At this time, since control in the depth direction of diffusion is performed by a diffusion time that takes into account the thickness of the n-type GaAs epitaxial layer 22 and the n+-type GaAs epitaxial layer 23, the channel layer formed under the P+ type gate diffusion part 26 The thickness of is always constant. Incidentally, unlike etching, diffusion of impurities takes a relatively long time, so the amount of diffusion can be easily controlled. Also, n-type G
Since the n÷ type GaAs epitaxial layer 23 is stacked to reduce the contact resistance of the electrode to the aAs epitaxial layer 22, the overall thickness of the n type GaAs epitaxial layer 22 and the n+ type GaAs epitaxial layer 23 can be reduced. It is also possible to diffuse the P÷ type gate diffusion layer 26, which results in a short gate length, if necessary.

Step 3: Gold beryllium alloy (AuBe) is applied to cover the window 24A of the SiN layer in which the P+ type gate diffusion region 26 is formed.
A gate metal 27 is formed by a lift-off method or dry etching.

Step 4: A resist pattern 28 is formed using a resist slightly larger than the gate metal 27, and using this resist pattern 28 and the gate metal 27 as a mask, the SiN layer between the resist pattern 28 and the gate metal 27 is coated with CF2 or the like. A window is opened by plasma etching of
Dry etching is performed using a phosphoric acid-based etching solution or a C1-based gas so as to reach the inside of the GaAs epitaxial layer 22.

Step 5: After covering the entire surface with an insulating protection layer 29 such as SiN, a Si
Window portions 29A and 29B are formed in the same manner as in steps 2 and 3 for the N layer.
form.

Step 6: A source electrode 30 is formed using a gold germanium nickel alloy (AuGeNi, etc.) in the windows 29A and 29B.
, to form the drain electrode 31.

According to the method for manufacturing a semiconductor device of the present invention described above, it is possible to manufacture a semiconductor device that has little variation in saturation current, prevents deterioration of reverse breakdown voltage, and has good characteristics.

In addition, although the above describes a method for manufacturing a junction field effect transistor using a compound semiconductor such as GaAs, the method for manufacturing the semiconductor ts1 according to the present invention is a method for manufacturing a junction field effect transistor using a compound semiconductor other than this. Needless to say, the present invention can also be applied to a method of manufacturing an effect transistor.

(Effects of the Invention) As described above, there is a step of forming an n-type conductive layer on a semi-insulating compound semiconductor substrate, and a step of forming a high impurity layer on the n-type conductive layer! l! forming an n-type conductive layer with a concentration of J; forming a diffusion mask layer on the n-type conductive layer; forming a window in the diffusion mask layer; a step of diffusing an impurity into the n-type conductive layer through the green conductive layer to form a P-type conductive region; a step of forming a gate metal on the P-type conductive region; and a step of forming a gate metal and a photoresist. removing a portion of the diffusion mask layer, the n-type conductive layer, and the n-type conductive layer around the gate metal, leaving portions that will become the source and drain masked by the layer; A step of forming an insulating protective layer on the entire exposed surface, a step of forming a window in a portion of the insulating protective layer that will become a source and a drain, and a step of forming a source electrode and a drain electrode in the window. According to the manufacturing method of the semiconductor device 1, the n+ type GaAs epitaxial layer forming the diffusion mask layer has a flat surface, and there is no cracking in the diffusion mask layer as in the conventional method. Since the gate part is separated by etching, the distance between the source and gate can be shortened, which is effective in reducing resistance, reduces saturation flow variation, prevents deterioration of reverse breakdown voltage, and
The semiconductor device 1 having excellent characteristics can be manufactured with high productivity.

[Brief explanation of drawings]

FIG. 1 is a process diagram for explaining an embodiment of the method for manufacturing a semiconductor device of the present invention, FIG. 2 is a process diagram showing a cross section for explaining the manufacturing process of a conventional semiconductor device 1, and FIG. FIG. 3 is a cross-sectional view showing the structure of another semiconductor device 1 of FIG. 21... Semi-insulating compound semiconductor substrate (semi-insulating GaA
s substrate), 22... n-type GaAs epitaxial layer,
23...n-type GaAs epitaxial layer, 24...
- Diffusion mask layer, 24A... Window portion, 26... P+ type gate diffusion layer, 27... Gate metal, 28... Resist pattern, 29... Insulating protective layer, 30... Source electrode , 31... drain electrode. Patent applicant: Victor Japan Co., Ltd. Figure 2, Figure 3

Claims (1)

[Claims] A step of forming an n-type conductive layer 22 on a semi-insulating compound semiconductor substrate 21, and a step of forming an n^+-type conductive layer 23 with a high impurity concentration on the n-type conductive layer 22. , forming a diffusion mask layer 24 on the n^+ type conductive layer 23, forming a window 24A on the diffusion mask layer 24, and passing through the n^+ type conductive layer 23 from the window 24A. a step of diffusing impurities into the n-type conductive layer 22 to form a P^+ type conductive region 26; a step of forming a gate metal 27 on the P^+ type conductive region 26; and the gate metal 27. The diffusion mask layer 24 around the gate metal 27 and the n
a step of removing a part of the +-type conductive layer 23 and the n-type conductive layer 22; a step of forming an insulating protective layer 29 on the entire surface exposed in the step; and a step of removing the source and drain of the insulating protective layer 29. a step of forming window portions 29A, 29B in the portions where the window portions 29A, 29B are formed;
29B. A method for manufacturing a semiconductor device, comprising a step of forming a source electrode 30 and a drain electrode 31 on the substrate 29B.